0001-Add-new-instructions-for-RISC-V-and-Sparc-targets.patch

From 8505152177a9e6ff11396b2dd94ca22c46bf713f Mon Sep 17 00:00:00 2001
From: Roman Bartosinski <roman@daiteq.com>
Date: Mon, 28 Mar 2022 14:26:25 +0200
Subject: [PATCH] Add new instructions for RISC-V and Sparc targets

Signed-off-by: Roman Bartosinski <roman@daiteq.com>
---
 bfd/elfxx-riscv.c          |   2 +-
 binutils/readelf.c         |   9 ++
 gas/config/tc-riscv.c      |  14 ++
 gas/config/tc-sparc.c      |  64 ++++++++
 include/elf/sparc.h        |   5 +
 include/opcode/riscv-opc.h | 292 +++++++++++++++++++++++++++++++++++++
 include/opcode/riscv.h     |   3 +
 include/opcode/sparc.h     |   4 +
 opcodes/riscv-opc.c        | 285 ++++++++++++++++++++++++++++++++++++
 opcodes/sparc-opc.c        | 132 ++++++++++++++++-
 10 files changed, 807 insertions(+), 3 deletions(-)

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 39b69e2..782e0e3 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1077,7 +1077,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
 
 static const char * const riscv_std_z_ext_strtab[] =
 {
-  "zba", "zbb", "zbc", "zicsr", "zifencei", "zihintpause", NULL
+  "zba", "zbb", "zbc", /*"zfh",*/ "zicsr", "zifencei", "zihintpause", NULL
 };
 
 static const char * const riscv_std_s_ext_strtab[] =
diff --git a/binutils/readelf.c b/binutils/readelf.c
index a6073f7..ba68aa4 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -16642,6 +16642,15 @@ display_sparc_hwcaps2 (unsigned int mask)
 	printf ("%sfjdes", first ? "" : "|"), first = false;
       if (mask & ELF_SPARC_HWCAP2_FJAES)
 	printf ("%sfjaes", first ? "" : "|"), first = false;
+
+      if (mask & ELF_SPARC_HWCAP2_DQSWAR)
+	printf ("%sdqswar", first ? "" : "|"), first = false;
+      if (mask & ELF_SPARC_HWCAP2_DQFHALF)
+	printf ("%sdqfhalf", first ? "" : "|"), first = false;
+      if (mask & ELF_SPARC_HWCAP2_DQFCMPLX)
+	printf ("%sdqfcplx", first ? "" : "|"), first = false;
+      if (mask & ELF_SPARC_HWCAP2_DQFPACK)
+	printf ("%sdqfpack", first ? "" : "|"), first = false;
     }
   else
     fputc ('0', stdout);
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 70cbc81..60030f3 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -143,6 +143,7 @@ static const struct riscv_ext_version ext_version_table[] =
   {"zba",   ISA_SPEC_CLASS_DRAFT, 0, 93},
   {"zbc",   ISA_SPEC_CLASS_DRAFT, 0, 93},
 
+  {"zfh",   ISA_SPEC_CLASS_DRAFT, 0, 1},
   /* Terminate the list.  */
   {NULL, 0, 0, 0}
 };
@@ -343,6 +344,9 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
     case INSN_CLASS_ZBC:
       return riscv_subset_supports ("zbc");
 
+    case INSN_CLASS_ZFH:
+      return riscv_subset_supports ("zfh");
+
     default:
       as_fatal ("internal: unreachable");
       return false;
@@ -1655,6 +1659,11 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
 		  BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
       break;
 
+    case M_FLH:
+      pcrel_load (rd, rs1, imm_expr, "flh",
+		  BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
+      break;
+
     case M_FLW:
       pcrel_load (rd, rs1, imm_expr, "flw",
 		  BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
@@ -1685,6 +1694,11 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
 		   BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
       break;
 
+    case M_FSH:
+      pcrel_store (rs2, rs1, imm_expr, "fsh",
+		   BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
+      break;
+
     case M_FSW:
       pcrel_store (rs2, rs1, imm_expr, "fsw",
 		   BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
diff --git a/gas/config/tc-sparc.c b/gas/config/tc-sparc.c
index b872381..9606a8d 100644
--- a/gas/config/tc-sparc.c
+++ b/gas/config/tc-sparc.c
@@ -38,6 +38,8 @@ static int parse_sparc_asi (char **, const sparc_asi **);
 static int parse_keyword_arg (int (*) (const char *), char **, int *);
 static int parse_const_expr_arg (char **, int *);
 static int get_expression (char *);
+static const char *get_hwcap_name (bfd_uint64_t mask);
+
 
 /* Default architecture.  */
 /* ??? The default value should be V8, but sparclite support was added
@@ -80,6 +82,14 @@ static bfd_uint64_t hwcap_seen;
 
 static bfd_uint64_t hwcap_allowed;
 
+/* daiteq spec.ISE: for direct checking allowed instructions */
+static bfd_uint64_t hwcap_required;
+static bfd_uint64_t hwcap2_required;
+/* This shouldn't be global but it should be architecture specific */
+#define HWCAP_FOR_CHECKING 0
+#define HWCAP2_FOR_CHECKING (HWCAP2_DQSWAR | HWCAP2_DQFHALF |                  \
+                             HWCAP2_DQFCMPLX | HWCAP2_DQFPACK)
+
 static int architecture_requested;
 static int warn_on_bump;
 
@@ -315,6 +325,9 @@ init_default_arch (void)
   default_arch_size = sparc_arch_size = sa->default_arch_size;
   default_init_p = 1;
   default_arch_type = sa->arch_type;
+
+  hwcap_required = 0;
+  hwcap2_required = 0;
 }
 
 /* Called by TARGET_MACH.  */
@@ -439,6 +452,16 @@ struct option md_longopts[] = {
   {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
 #define OPTION_DCTI_COUPLES_DETECT (OPTION_MD_BASE + 16)
   {"dcti-couples-detect", no_argument, NULL, OPTION_DCTI_COUPLES_DETECT},
+
+#define OPTION_DQSWAR (OPTION_MD_BASE + 17)
+  {"has-swar", no_argument, NULL, OPTION_DQSWAR},
+#define OPTION_DQFHALF (OPTION_MD_BASE + 18)
+  {"has-fhalf", no_argument, NULL, OPTION_DQFHALF},
+#define OPTION_DQFCPLX (OPTION_MD_BASE + 19)
+  {"has-fcplx", no_argument, NULL, OPTION_DQFCPLX},
+#define OPTION_DQFPACK (OPTION_MD_BASE + 20)
+  {"has-fpack", no_argument, NULL, OPTION_DQFPACK},
+
   {NULL, no_argument, NULL, 0}
 };
 
@@ -624,6 +647,19 @@ md_parse_option (int c, const char *arg)
       dcti_couples_detect = 1;
       break;
 
+    case OPTION_DQSWAR:
+      hwcap2_required |= HWCAP2_DQSWAR;
+      break;
+    case OPTION_DQFHALF:
+      hwcap2_required |= HWCAP2_DQFHALF;
+      break;
+    case OPTION_DQFCPLX:
+      hwcap2_required |= HWCAP2_DQFCMPLX;
+      break;
+    case OPTION_DQFPACK:
+      hwcap2_required |= HWCAP2_DQFPACK;
+      break;
+
     default:
       return 0;
     }
@@ -707,6 +743,12 @@ md_show_usage (FILE *stream)
 --little-endian-data	generate code for a machine having big endian\n\
                         instructions and little endian data.\n"));
 #endif
+  fprintf (stream, _("\
+--has-swar		generate code for SWAR instructions\n\
+--has-fhalf		generate code for FP half precision instructions\n\
+--has-fcplx		generate code for FP complex numbers\n\
+--has-fpack		generate code for FP packed numbers\n"));
+
 }
 
 /* Native operand size opcode translation.  */
@@ -1515,6 +1557,20 @@ md_assemble (char *str)
   if (insn == NULL)
     return;
 
+  /* checking for required hwcaps */
+  if ((insn->hwcaps & HWCAP_FOR_CHECKING) ||
+      (insn->hwcaps2 & HWCAP2_FOR_CHECKING)) {
+    /* checked hwcap is not allowed */
+    if ((insn->hwcaps & ~hwcap_required) ||
+        (insn->hwcaps2 & ~hwcap2_required)) {
+      bfd_uint64_t rmsk = (insn->hwcaps & ~hwcap_required) |
+                          ((insn->hwcaps2 & ~hwcap2_required)<<32);
+      const char *hwnm = get_hwcap_name(rmsk);
+      as_bad(_("Required instruction (%s) is not allowed. HWcap \"%s\" has to be enabled."), insn->name, hwnm);
+      return;
+    }
+  }
+
   /* Certain instructions may not appear on delay slots.  Check for
      these situations.  */
   if (last_insn != NULL
@@ -1701,6 +1757,14 @@ get_hwcap_name (bfd_uint64_t mask)
     return "rle";
   if (mask & HWCAP2_SHA3)
     return "sha3";
+  if (mask & HWCAP2_DQSWAR)
+    return "dqswar";
+  if (mask & HWCAP2_DQFHALF)
+    return "dqfhalf";
+  if (mask & HWCAP2_DQFCMPLX)
+    return "dqfcplx";
+  if (mask & HWCAP2_DQFPACK)
+    return "dqfpack";
 
   return "UNKNOWN";
 }
diff --git a/include/elf/sparc.h b/include/elf/sparc.h
index 5dcc047..73b4a1d 100644
--- a/include/elf/sparc.h
+++ b/include/elf/sparc.h
@@ -258,4 +258,9 @@ enum
 #define ELF_SPARC_HWCAP2_RLE       0x00800000 /* Run-length encoded burst and length */
 #define ELF_SPARC_HWCAP2_SHA3      0x01000000 /* SHA3 instruction */
 
+#define ELF_SPARC_HWCAP2_DQSWAR    0x10000000 /* daiteq IP core extensions SWAR instructions */
+#define ELF_SPARC_HWCAP2_DQFHALF   0x20000000 /* daiteq IP core extensions FP instructions for half precision */
+#define ELF_SPARC_HWCAP2_DQFCMPLX  0x40000000 /* daiteq IP core extensions FP instructions with complex numbers */
+#define ELF_SPARC_HWCAP2_DQFPACK   0x80000000 /* daiteq IP core extensions FP instructions with packed numbers */
+
 #endif /* _ELF_SPARC_H */
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 9999da6..92c5b60 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -423,6 +423,288 @@
 #define MASK_FCVT_Q_LU  0xfff0007f
 #define MATCH_FMV_Q_X 0xf6000053
 #define MASK_FMV_Q_X  0xfff0707f
+
+/* half FP instructions */
+#define MATCH_FLH       0x1007
+#define MASK_FLH        0x707f
+#define MATCH_FSH       0x1027
+#define MASK_FSH        0x707f
+
+#define MATCH_FMV_X_H   0xe4000053
+#define MASK_FMV_X_H    0xfff0707f
+#define MATCH_FMV_H_X   0xf4000053
+#define MASK_FMV_H_X    0xfff0707f
+#define MATCH_FSGNJ_H   0x24000053
+#define MASK_FSGNJ_H    0xfe00707f
+#define MATCH_FSGNJN_H  0x24001053
+#define MASK_FSGNJN_H   0xfe00707f
+#define MATCH_FSGNJX_H  0x24002053
+#define MASK_FSGNJX_H   0xfe00707f
+#define MATCH_FADD_H    0x4000053
+#define MASK_FADD_H     0xfe00007f
+#define MATCH_FSUB_H    0xc000053
+#define MASK_FSUB_H     0xfe00007f
+#define MATCH_FMUL_H    0x14000053
+#define MASK_FMUL_H     0xfe00007f
+#define MATCH_FDIV_H    0x1c000053
+#define MASK_FDIV_H     0xfe00007f
+#define MATCH_FSQRT_H   0x5c000053
+#define MASK_FSQRT_H    0xfff0007f
+#define MATCH_FMIN_H    0x2c000053
+#define MASK_FMIN_H     0xfe00707f
+#define MATCH_FMAX_H    0x2c001053
+#define MASK_FMAX_H     0xfe00707f
+#define MATCH_FMADD_H   0x4000043
+#define MASK_FMADD_H    0x600007f
+#define MATCH_FMSUB_H   0x4000047
+#define MASK_FMSUB_H    0x600007f
+#define MATCH_FNMSUB_H  0x400004b
+#define MASK_FNMSUB_H   0x600007f
+#define MATCH_FNMADD_H  0x400004f
+#define MASK_FNMADD_H   0x600007f
+#define MATCH_FCVT_W_H  0xc4000053
+#define MASK_FCVT_W_H   0xfff0007f
+#define MATCH_FCVT_WU_H 0xc4100053
+#define MASK_FCVT_WU_H  0xfff0007f
+#define MATCH_FCVT_L_H  0xc4200053
+#define MASK_FCVT_L_H   0xfff0007f
+#define MATCH_FCVT_LU_H 0xc4300053
+#define MASK_FCVT_LU_H  0xfff0007f
+#define MATCH_FCVT_H_W  0xd4000053
+#define MASK_FCVT_H_W   0xfff0007f
+#define MATCH_FCVT_H_WU 0xd4100053
+#define MASK_FCVT_H_WU  0xfff0007f
+#define MATCH_FCVT_H_L  0xd4200053
+#define MASK_FCVT_H_L   0xfff0007f
+#define MATCH_FCVT_H_LU 0xd4300053
+#define MASK_FCVT_H_LU  0xfff0007f
+#define MATCH_FCLASS_H  0xe4001053
+#define MASK_FCLASS_H   0xfff0707f
+#define MATCH_FEQ_H     0xa4002053
+#define MASK_FEQ_H      0xfe00707f
+#define MATCH_FLT_H     0xa4001053
+#define MASK_FLT_H      0xfe00707f
+#define MATCH_FLE_H     0xa4000053
+#define MASK_FLE_H      0xfe00707f
+
+#define MATCH_FCVT_S_H  0x40200053
+#define MASK_FCVT_S_H   0xfff0007f
+#define MATCH_FCVT_D_H  0x42200053
+#define MASK_FCVT_D_H   0xfff0007f
+#define MATCH_FCVT_Q_H  0x46200053
+#define MASK_FCVT_Q_H   0xfff0007f
+#define MATCH_FCVT_H_S  0x44000053
+#define MASK_FCVT_H_S   0xfff0007f
+#define MATCH_FCVT_H_D  0x44100053
+#define MASK_FCVT_H_D   0xfff0007f
+#define MATCH_FCVT_H_Q  0x44300053
+#define MASK_FCVT_H_Q   0xfff0007f
+
+/* half packed FP instructions - opcode modifier#2 is the same as for float.single */
+#define MATCH_FSGNJ_PH  0x20004053
+#define MASK_FSGNJ_PH   0xfe00707f
+#define MATCH_FSGNJN_PH 0x20005053
+#define MASK_FSGNJN_PH  0xfe00707f
+#define MATCH_FSGNJX_PH 0x20006053
+#define MASK_FSGNJX_PH  0xfe00707f
+#define MATCH_FCLASS_PH 0xe0005053
+#define MASK_FCLASS_PH  0xfff0707f
+#define MATCH_FEQ_PH    0xa0006053
+#define MASK_FEQ_PH     0xfe00707f
+#define MATCH_FLT_PH    0xa0005053
+#define MASK_FLT_PH     0xfe00707f
+#define MATCH_FLE_PH    0xa0004053
+#define MASK_FLE_PH     0xfe00707f
+
+#define MATCH_FADD_PH   0x80000053
+#define MASK_FADD_PH    0xfe00007f
+#define MATCH_FSUB_PH   0x88000053
+#define MASK_FSUB_PH    0xfe00007f
+#define MATCH_FMUL_PH   0x90000053
+#define MASK_FMUL_PH    0xfe00007f
+#define MATCH_FDIV_PH   0x98000053
+#define MASK_FDIV_PH    0xfe00007f
+#define MATCH_FSQRT_PH  0xd8000053
+#define MASK_FSQRT_PH   0xfff0007f
+#define MATCH_FMIN_PH   0x28004053
+#define MASK_FMIN_PH    0xfe00707f
+#define MATCH_FMAX_PH   0x28005053
+#define MASK_FMAX_PH    0xfe00707f
+
+#define MATCH_FADDX_PH  0x60000053
+#define MASK_FADDX_PH   0xfe00007f
+#define MATCH_FSUBX_PH  0x68000053
+#define MASK_FSUBX_PH   0xfe00007f
+#define MATCH_FMULX_PH  0x70000053
+#define MASK_FMULX_PH   0xfe00007f
+#define MATCH_FDIVX_PH  0x78000053
+#define MASK_FDIVX_PH   0xfe00007f
+
+#define MATCH_FADDR_PH  0xa8000053
+#define MASK_FADDR_PH   0xfe00007f
+#define MATCH_FSUBR_PH  0xb0000053
+#define MASK_FSUBR_PH   0xfe00007f
+#define MATCH_FMULR_PH  0xb8000053
+#define MASK_FMULR_PH   0xfe00007f
+#define MATCH_FDIVR_PH  0xc8000053
+#define MASK_FDIVR_PH   0xfe00007f
+#define MATCH_FADDSUBR_PH  0x30000053
+#define MASK_FADDSUBR_PH   0xfe00007f
+#define MATCH_FSUBADDR_PH  0x38000053
+#define MASK_FSUBADDR_PH   0xfe00007f
+
+#define MATCH_FMVUU_PH   0xe8000053
+#define MASK_FMVUU_PH    0xfe00707f
+#define MATCH_FMVLL_PH   0xe8001053
+#define MASK_FMVLL_PH    0xfe00707f
+#define MATCH_FMVUL_PH   0xe8002053
+#define MASK_FMVUL_PH    0xfe00707f
+#define MATCH_FMVLU_PH   0xe8003053
+#define MASK_FMVLU_PH    0xfe00707f
+#define MATCH_FMVZU_PH   0xe8004053
+#define MASK_FMVZU_PH    0xfff0707f
+#define MATCH_FMVZL_PH   0xe8005053
+#define MASK_FMVZL_PH    0xfff0707f
+
+/* single packed FP instructions - opcode modifier#2 is the same as for float.double */
+#define MATCH_FSGNJ_PS  0x22004053
+#define MASK_FSGNJ_PS   0xfe00707f
+#define MATCH_FSGNJN_PS 0x22005053
+#define MASK_FSGNJN_PS  0xfe00707f
+#define MATCH_FSGNJX_PS 0x22006053
+#define MASK_FSGNJX_PS  0xfe00707f
+#define MATCH_FCLASS_PS 0xe2005053
+#define MASK_FCLASS_PS  0xfff0707f
+#define MATCH_FEQ_PS    0xa2006053
+#define MASK_FEQ_PS     0xfe00707f
+#define MATCH_FLT_PS    0xa2005053
+#define MASK_FLT_PS     0xfe00707f
+#define MATCH_FLE_PS    0xa2004053
+#define MASK_FLE_PS     0xfe00707f
+
+#define MATCH_FADD_PS   0x82000053
+#define MASK_FADD_PS    0xfe00007f
+#define MATCH_FSUB_PS   0x8a000053
+#define MASK_FSUB_PS    0xfe00007f
+#define MATCH_FMUL_PS   0x92000053
+#define MASK_FMUL_PS    0xfe00007f
+#define MATCH_FDIV_PS   0x9a000053
+#define MASK_FDIV_PS    0xfe00007f
+#define MATCH_FSQRT_PS  0xda000053
+#define MASK_FSQRT_PS   0xfff0007f
+#define MATCH_FMIN_PS   0x2a004053
+#define MASK_FMIN_PS    0xfe00707f
+#define MATCH_FMAX_PS   0x2a005053
+#define MASK_FMAX_PS    0xfe00707f
+
+#define MATCH_FADDX_PS  0x62000053
+#define MASK_FADDX_PS   0xfe00007f
+#define MATCH_FSUBX_PS  0x6a000053
+#define MASK_FSUBX_PS   0xfe00007f
+#define MATCH_FMULX_PS  0x72000053
+#define MASK_FMULX_PS   0xfe00007f
+#define MATCH_FDIVX_PS  0x7a000053
+#define MASK_FDIVX_PS   0xfe00007f
+
+#define MATCH_FADDR_PS  0xaa000053
+#define MASK_FADDR_PS   0xfe00007f
+#define MATCH_FSUBR_PS  0xb2000053
+#define MASK_FSUBR_PS   0xfe00007f
+#define MATCH_FMULR_PS  0xba000053
+#define MASK_FMULR_PS   0xfe00007f
+#define MATCH_FDIVR_PS  0xca000053
+#define MASK_FDIVR_PS   0xfe00007f
+#define MATCH_FADDSUBR_PS  0x32000053
+#define MASK_FADDSUBR_PS   0xfe00007f
+#define MATCH_FSUBADDR_PS  0x3a000053
+#define MASK_FSUBADDR_PS   0xfe00007f
+
+#define MATCH_FMVUU_PS   0xea000053
+#define MASK_FMVUU_PS    0xfe00707f
+#define MATCH_FMVLL_PS   0xea001053
+#define MASK_FMVLL_PS    0xfe00707f
+#define MATCH_FMVUL_PS   0xea002053
+#define MASK_FMVUL_PS    0xfe00707f
+#define MATCH_FMVLU_PS   0xea003053
+#define MASK_FMVLU_PS    0xfe00707f
+#define MATCH_FMVZU_PS   0xea004053
+#define MASK_FMVZU_PS    0xfff0707f
+#define MATCH_FMVZL_PS   0xea005053
+#define MASK_FMVZL_PS    0xfff0707f
+
+/* double packed FP instructions - opcode modifier#2 is the same as for float.quad */
+#define MATCH_FSGNJ_PD  0x26004053
+#define MASK_FSGNJ_PD   0xfe00707f
+#define MATCH_FSGNJN_PD 0x26005053
+#define MASK_FSGNJN_PD  0xfe00707f
+#define MATCH_FSGNJX_PD 0x26006053
+#define MASK_FSGNJX_PD  0xfe00707f
+#define MATCH_FCLASS_PD 0xe6005053
+#define MASK_FCLASS_PD  0xfff0707f
+#define MATCH_FEQ_PD    0xa6006053
+#define MASK_FEQ_PD     0xfe00707f
+#define MATCH_FLT_PD    0xa6005053
+#define MASK_FLT_PD     0xfe00707f
+#define MATCH_FLE_PD    0xa6004053
+#define MASK_FLE_PD     0xfe00707f
+
+#define MATCH_FADD_PD   0x86000053
+#define MASK_FADD_PD    0xfe00007f
+#define MATCH_FSUB_PD   0x8e000053
+#define MASK_FSUB_PD    0xfe00007f
+#define MATCH_FMUL_PD   0x96000053
+#define MASK_FMUL_PD    0xfe00007f
+#define MATCH_FDIV_PD   0x9e000053
+#define MASK_FDIV_PD    0xfe00007f
+#define MATCH_FSQRT_PD  0xde000053
+#define MASK_FSQRT_PD   0xfff0007f
+#define MATCH_FMIN_PD   0x2e004053
+#define MASK_FMIN_PD    0xfe00707f
+#define MATCH_FMAX_PD   0x2e005053
+#define MASK_FMAX_PD    0xfe00707f
+
+#define MATCH_FADDX_PD  0x66000053
+#define MASK_FADDX_PD   0xfe00007f
+#define MATCH_FSUBX_PD  0x6e000053
+#define MASK_FSUBX_PD   0xfe00007f
+#define MATCH_FMULX_PD  0x76000053
+#define MASK_FMULX_PD   0xfe00007f
+#define MATCH_FDIVX_PD  0x7e000053
+#define MASK_FDIVX_PD   0xfe00007f
+
+#define MATCH_FADDR_PD  0xae000053
+#define MASK_FADDR_PD   0xfe00007f
+#define MATCH_FSUBR_PD  0xb6000053
+#define MASK_FSUBR_PD   0xfe00007f
+#define MATCH_FMULR_PD  0xbe000053
+#define MASK_FMULR_PD   0xfe00007f
+#define MATCH_FDIVR_PD  0xce000053
+#define MASK_FDIVR_PD   0xfe00007f
+#define MATCH_FADDSUBR_PD  0x36000053
+#define MASK_FADDSUBR_PD   0xfe00007f
+#define MATCH_FSUBADDR_PD  0x3e000053
+#define MASK_FSUBADDR_PD   0xfe00007f
+
+#define MATCH_FMVUU_PD   0xee000053
+#define MASK_FMVUU_PD    0xfe00707f
+#define MATCH_FMVLL_PD   0xee001053
+#define MASK_FMVLL_PD    0xfe00707f
+#define MATCH_FMVUL_PD   0xee002053
+#define MASK_FMVUL_PD    0xfe00707f
+#define MATCH_FMVLU_PD   0xee003053
+#define MASK_FMVLU_PD    0xfe00707f
+#define MATCH_FMVZU_PD   0xee004053
+#define MASK_FMVZU_PD    0xfff0707f
+#define MATCH_FMVZL_PD   0xee005053
+#define MASK_FMVZL_PD    0xfff0707f
+
+/* SWAR instructions */
+#define MATCH_SWARI     0x0B
+#define MASK_SWARI      0x707f
+#define MATCH_SWAR      0x2B
+#define MASK_SWAR       0xfe00707f
+
+
 #define MATCH_CLZ 0x60001013
 #define MASK_CLZ  0xfff0707f
 #define MATCH_CTZ 0x60101013
@@ -868,6 +1150,10 @@
 #define CSR_TCONTROL 0x7a5
 #define CSR_MCONTEXT 0x7a8
 #define CSR_SCONTEXT 0x7aa
+/* CSR for SWAR extension */
+#define CSR_SWARCTRLSTAT  0x400
+#define CSR_SWARACC       0x410
+#define CSR_SWARACCHI     0x411
 #endif /* RISCV_ENCODING_H */
 #ifdef DECLARE_INSN
 DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
@@ -1285,6 +1571,11 @@ DECLARE_CSR(pmpaddr12, CSR_PMPADDR12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SP
 DECLARE_CSR(pmpaddr13, CSR_PMPADDR13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
 DECLARE_CSR(pmpaddr14, CSR_PMPADDR14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
 DECLARE_CSR(pmpaddr15, CSR_PMPADDR15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
+
+DECLARE_CSR(swarctrlstat, CSR_SWARCTRLSTAT, CSR_CLASS_I, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(swaracc, CSR_SWARACC, CSR_CLASS_I, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(swaracchi, CSR_SWARACCHI, CSR_CLASS_I_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_DRAFT)
+
 DECLARE_CSR(mcycle, CSR_MCYCLE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
 DECLARE_CSR(minstret, CSR_MINSTRET, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
 DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
@@ -1427,3 +1718,4 @@ DECLARE_CSR_ALIAS(etrigger, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, P
 DECLARE_CSR_ALIAS(textra32, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR_ALIAS(textra64, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 #endif /* DECLARE_CSR_ALIAS */
+
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index fdf3df4..e0b98be 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -319,6 +319,7 @@ enum riscv_insn_class
   INSN_CLASS_ZBA,
   INSN_CLASS_ZBB,
   INSN_CLASS_ZBC,
+  INSN_CLASS_ZFH,
 };
 
 /* This structure holds information for a particular instruction.  */
@@ -409,9 +410,11 @@ enum
   M_SH,
   M_SW,
   M_SD,
+  M_FLH,
   M_FLW,
   M_FLD,
   M_FLQ,
+  M_FSH,
   M_FSW,
   M_FSD,
   M_FSQ,
diff --git a/include/opcode/sparc.h b/include/opcode/sparc.h
index 2f2e149..06dfebe 100644
--- a/include/opcode/sparc.h
+++ b/include/opcode/sparc.h
@@ -194,6 +194,10 @@ typedef struct
 #define HWCAP2_RLE       0x00800000 /* Run-length encoded burst and length */
 #define HWCAP2_SHA3      0x01000000 /* SHA3 instruction */
 
+#define HWCAP2_DQSWAR    0x10000000 /* IP core extensions SWAR instructions */
+#define HWCAP2_DQFHALF   0x20000000 /* IP core extensions FP instructions for half precision */
+#define HWCAP2_DQFCMPLX  0x40000000 /* IP core extensions FP instructions with complex numbers */
+#define HWCAP2_DQFPACK   0x80000000 /* IP core extensions FP instructions with packed numbers */
 
 /* All sparc opcodes are 32 bits, except for the `set' instruction (really a
    macro), which is 64 bits. It is handled as a special case.
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index f55a01b..865f017 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -702,6 +702,291 @@ const struct riscv_opcode riscv_opcodes[] =
 {"fcvt.q.lu", 64, INSN_CLASS_Q,   "D,s",       MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
 {"fcvt.q.lu", 64, INSN_CLASS_Q,   "D,s,m",     MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 },
 
+
+
+/* Half-precision floating-point instruction subset (Zfh extension). */
+{"flh",        0, INSN_CLASS_F,   "D,o(s)",    MATCH_FLH, MASK_FLH, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"flh",        0, INSN_CLASS_F,   "D,A,s",     0, (int) M_FLH, match_never, INSN_MACRO },
+{"fsh",        0, INSN_CLASS_F,   "T,q(s)",    MATCH_FSH, MASK_FSH, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"fsh",        0, INSN_CLASS_F,   "T,A,s",     0, (int) M_FSH, match_never, INSN_MACRO },
+
+{"fmv.x.h",    0, INSN_CLASS_F,   "d,S",       MATCH_FMV_X_H, MASK_FMV_X_H, match_opcode, 0 },
+{"fmv.h.x",    0, INSN_CLASS_F,   "D,s",       MATCH_FMV_H_X, MASK_FMV_H_X, match_opcode, 0 },
+{"fmv.h",      0, INSN_CLASS_F,   "D,U",       MATCH_FSGNJ_H, MASK_FSGNJ_H, match_rs1_eq_rs2, INSN_ALIAS },
+{"fneg.h",     0, INSN_CLASS_F,   "D,U",       MATCH_FSGNJN_H, MASK_FSGNJN_H, match_rs1_eq_rs2, INSN_ALIAS },
+{"fabs.h",     0, INSN_CLASS_F,   "D,U",       MATCH_FSGNJX_H, MASK_FSGNJX_H, match_rs1_eq_rs2, INSN_ALIAS },
+{"fsgnj.h",    0, INSN_CLASS_F,   "D,S,T",     MATCH_FSGNJ_H, MASK_FSGNJ_H, match_opcode, 0 },
+{"fsgnjn.h",   0, INSN_CLASS_F,   "D,S,T",     MATCH_FSGNJN_H, MASK_FSGNJN_H, match_opcode, 0 },
+{"fsgnjx.h",   0, INSN_CLASS_F,   "D,S,T",     MATCH_FSGNJX_H, MASK_FSGNJX_H, match_opcode, 0 },
+{"fadd.h",     0, INSN_CLASS_F,   "D,S,T",     MATCH_FADD_H|MASK_RM, MASK_FADD_H|MASK_RM, match_opcode, 0 },
+{"fadd.h",     0, INSN_CLASS_F,   "D,S,T,m",   MATCH_FADD_H, MASK_FADD_H, match_opcode, 0 },
+{"fsub.h",     0, INSN_CLASS_F,   "D,S,T",     MATCH_FSUB_H|MASK_RM, MASK_FSUB_H|MASK_RM, match_opcode, 0 },
+{"fsub.h",     0, INSN_CLASS_F,   "D,S,T,m",   MATCH_FSUB_H, MASK_FSUB_H, match_opcode, 0 },
+{"fmul.h",     0, INSN_CLASS_F,   "D,S,T",     MATCH_FMUL_H|MASK_RM, MASK_FMUL_H|MASK_RM, match_opcode, 0 },
+{"fmul.h",     0, INSN_CLASS_F,   "D,S,T,m",   MATCH_FMUL_H, MASK_FMUL_H, match_opcode, 0 },
+{"fdiv.h",     0, INSN_CLASS_F,   "D,S,T",     MATCH_FDIV_H|MASK_RM, MASK_FDIV_H|MASK_RM, match_opcode, 0 },
+{"fdiv.h",     0, INSN_CLASS_F,   "D,S,T,m",   MATCH_FDIV_H, MASK_FDIV_H, match_opcode, 0 },
+{"fsqrt.h",    0, INSN_CLASS_F,   "D,S",       MATCH_FSQRT_H|MASK_RM, MASK_FSQRT_H|MASK_RM, match_opcode, 0 },
+{"fsqrt.h",    0, INSN_CLASS_F,   "D,S,m",     MATCH_FSQRT_H, MASK_FSQRT_H, match_opcode, 0 },
+{"fmin.h",     0, INSN_CLASS_F,   "D,S,T",     MATCH_FMIN_H, MASK_FMIN_H, match_opcode, 0 },
+{"fmax.h",     0, INSN_CLASS_F,   "D,S,T",     MATCH_FMAX_H, MASK_FMAX_H, match_opcode, 0 },
+{"fmadd.h",    0, INSN_CLASS_F,   "D,S,T,R",   MATCH_FMADD_H|MASK_RM, MASK_FMADD_H|MASK_RM, match_opcode, 0 },
+{"fmadd.h",    0, INSN_CLASS_F,   "D,S,T,R,m", MATCH_FMADD_H, MASK_FMADD_H, match_opcode, 0 },
+{"fnmadd.h",   0, INSN_CLASS_F,   "D,S,T,R",   MATCH_FNMADD_H|MASK_RM, MASK_FNMADD_H|MASK_RM, match_opcode, 0 },
+{"fnmadd.h",   0, INSN_CLASS_F,   "D,S,T,R,m", MATCH_FNMADD_H, MASK_FNMADD_H, match_opcode, 0 },
+{"fmsub.h",    0, INSN_CLASS_F,   "D,S,T,R",   MATCH_FMSUB_H|MASK_RM, MASK_FMSUB_H|MASK_RM, match_opcode, 0 },
+{"fmsub.h",    0, INSN_CLASS_F,   "D,S,T,R,m", MATCH_FMSUB_H, MASK_FMSUB_H, match_opcode, 0 },
+{"fnmsub.h",   0, INSN_CLASS_F,   "D,S,T,R",   MATCH_FNMSUB_H|MASK_RM, MASK_FNMSUB_H|MASK_RM, match_opcode, 0 },
+{"fnmsub.h",   0, INSN_CLASS_F,   "D,S,T,R,m", MATCH_FNMSUB_H, MASK_FNMSUB_H, match_opcode, 0 },
+
+{"fcvt.w.h",   0, INSN_CLASS_F,   "d,S",       MATCH_FCVT_W_H|MASK_RM, MASK_FCVT_W_H|MASK_RM, match_opcode, 0 },
+{"fcvt.w.h",   0, INSN_CLASS_F,   "d,S,m",     MATCH_FCVT_W_H, MASK_FCVT_W_H, match_opcode, 0 },
+{"fcvt.wu.h",  0, INSN_CLASS_F,   "d,S",       MATCH_FCVT_WU_H|MASK_RM, MASK_FCVT_WU_H|MASK_RM, match_opcode, 0 },
+{"fcvt.wu.h",  0, INSN_CLASS_F,   "d,S,m",     MATCH_FCVT_WU_H, MASK_FCVT_WU_H, match_opcode, 0 },
+{"fcvt.h.w",   0, INSN_CLASS_F,   "D,s",       MATCH_FCVT_H_W|MASK_RM, MASK_FCVT_H_W|MASK_RM, match_opcode, 0 },
+{"fcvt.h.w",   0, INSN_CLASS_F,   "D,s,m",     MATCH_FCVT_H_W, MASK_FCVT_H_W, match_opcode, 0 },
+{"fcvt.h.wu",  0, INSN_CLASS_F,   "D,s",       MATCH_FCVT_H_WU|MASK_RM, MASK_FCVT_H_W|MASK_RM, match_opcode, 0 },
+{"fcvt.h.wu",  0, INSN_CLASS_F,   "D,s,m",     MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 },
+{"fcvt.l.h",  64, INSN_CLASS_F,   "d,S",       MATCH_FCVT_L_H|MASK_RM, MASK_FCVT_L_H|MASK_RM, match_opcode, 0 },
+{"fcvt.l.h",  64, INSN_CLASS_F,   "d,S,m",     MATCH_FCVT_L_H, MASK_FCVT_L_H, match_opcode, 0 },
+{"fcvt.lu.h", 64, INSN_CLASS_F,   "d,S",       MATCH_FCVT_LU_H|MASK_RM, MASK_FCVT_LU_H|MASK_RM, match_opcode, 0 },
+{"fcvt.lu.h", 64, INSN_CLASS_F,   "d,S,m",     MATCH_FCVT_LU_H, MASK_FCVT_LU_H, match_opcode, 0 },
+{"fcvt.h.l",  64, INSN_CLASS_F,   "D,s",       MATCH_FCVT_H_L|MASK_RM, MASK_FCVT_H_L|MASK_RM, match_opcode, 0 },
+{"fcvt.h.l",  64, INSN_CLASS_F,   "D,s,m",     MATCH_FCVT_H_L, MASK_FCVT_H_L, match_opcode, 0 },
+{"fcvt.h.lu", 64, INSN_CLASS_F,   "D,s",       MATCH_FCVT_H_LU|MASK_RM, MASK_FCVT_H_L|MASK_RM, match_opcode, 0 },
+{"fcvt.h.lu", 64, INSN_CLASS_F,   "D,s,m",     MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 },
+
+{"fcvt.s.h",   0, INSN_CLASS_F,   "D,S",       MATCH_FCVT_S_H, MASK_FCVT_S_H|MASK_RM, match_opcode, 0 },
+{"fcvt.d.h",   0, INSN_CLASS_F,   "D,S",       MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, 0 },
+{"fcvt.q.h",   0, INSN_CLASS_F,   "D,S",       MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, 0 },
+{"fcvt.h.s",   0, INSN_CLASS_F,   "D,S",       MATCH_FCVT_H_S|MASK_RM, MASK_FCVT_H_S|MASK_RM, match_opcode, 0 },
+{"fcvt.h.s",   0, INSN_CLASS_F,   "D,S,m",     MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 },
+{"fcvt.h.d",   0, INSN_CLASS_F,   "D,S",       MATCH_FCVT_H_D|MASK_RM, MASK_FCVT_H_D|MASK_RM, match_opcode, 0 },
+{"fcvt.h.d",   0, INSN_CLASS_F,   "D,S,m",     MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, 0 },
+{"fcvt.h.q",   0, INSN_CLASS_F,   "D,S",       MATCH_FCVT_H_Q|MASK_RM, MASK_FCVT_H_Q|MASK_RM, match_opcode, 0 },
+{"fcvt.h.q",   0, INSN_CLASS_F,   "D,S,m",     MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, 0 },
+
+{"fclass.h",   0, INSN_CLASS_F,   "d,S",       MATCH_FCLASS_H, MASK_FCLASS_H, match_opcode, 0 },
+{"feq.h",      0, INSN_CLASS_F,   "d,S,T",     MATCH_FEQ_H, MASK_FEQ_H, match_opcode, 0 },
+{"flt.h",      0, INSN_CLASS_F,   "d,S,T",     MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
+{"fle.h",      0, INSN_CLASS_F,   "d,S,T",     MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 },
+{"fgt.h",      0, INSN_CLASS_F,   "d,T,S",     MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
+{"fge.h",      0, INSN_CLASS_F,   "d,T,S",     MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 },
+
+/* Packed half floating-point instruction subset */
+{"flph",      32, INSN_CLASS_F_AND_C, "D,Cm(Cc)",  MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
+{"flph",      32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
+{"flph",       0, INSN_CLASS_F,   "D,o(s)",    MATCH_FLW, MASK_FLW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
+{"flph",       0, INSN_CLASS_F,   "D,A,s",     0, (int) M_FLW, match_never, INSN_ALIAS|INSN_MACRO },
+{"fsph",      32, INSN_CLASS_F_AND_C, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
+{"fsph",      32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
+{"fsph",       0, INSN_CLASS_F,   "T,q(s)",    MATCH_FSW, MASK_FSW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
+{"fsph",       0, INSN_CLASS_F,   "T,A,s",     0, (int) M_FSW, match_never, INSN_ALIAS|INSN_MACRO },
+
+{"fmv.x.ph",   0, INSN_CLASS_F,   "d,S",       MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, INSN_ALIAS },
+{"fmv.ph.x",   0, INSN_CLASS_F,   "D,s",       MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, INSN_ALIAS },
+
+{"fmv.ph",     0, INSN_CLASS_F,   "D,U",       MATCH_FSGNJ_PH, MASK_FSGNJ_PH, match_rs1_eq_rs2, INSN_ALIAS },
+{"fneg.ph",    0, INSN_CLASS_F,   "D,U",       MATCH_FSGNJN_PH, MASK_FSGNJN_PH, match_rs1_eq_rs2, INSN_ALIAS },
+{"fabs.ph",    0, INSN_CLASS_F,   "D,U",       MATCH_FSGNJX_PH, MASK_FSGNJX_PH, match_rs1_eq_rs2, INSN_ALIAS },
+{"fsgnj.ph",   0, INSN_CLASS_F,   "D,S,T",     MATCH_FSGNJ_PH, MASK_FSGNJ_PH, match_opcode, 0 },
+{"fsgnjn.ph",  0, INSN_CLASS_F,   "D,S,T",     MATCH_FSGNJN_PH, MASK_FSGNJN_PH, match_opcode, 0 },
+{"fsgnjx.ph",  0, INSN_CLASS_F,   "D,S,T",     MATCH_FSGNJX_PH, MASK_FSGNJX_PH, match_opcode, 0 },
+{"fclass.ph",  0, INSN_CLASS_F,   "d,S",       MATCH_FCLASS_PH, MASK_FCLASS_PH, match_opcode, 0 },
+{"feq.ph",     0, INSN_CLASS_F,   "d,S,T",     MATCH_FEQ_PH, MASK_FEQ_PH, match_opcode, 0 },
+{"flt.ph",     0, INSN_CLASS_F,   "d,S,T",     MATCH_FLT_PH, MASK_FLT_PH, match_opcode, 0 },
+{"fle.ph",     0, INSN_CLASS_F,   "d,S,T",     MATCH_FLE_PH, MASK_FLE_PH, match_opcode, 0 },
+{"fgt.ph",     0, INSN_CLASS_F,   "d,T,S",     MATCH_FLT_PH, MASK_FLT_PH, match_opcode, 0 },
+{"fge.ph",     0, INSN_CLASS_F,   "d,T,S",     MATCH_FLE_PH, MASK_FLE_PH, match_opcode, 0 },
+
+{"fadd.ph",    0, INSN_CLASS_F,   "D,S,T",     MATCH_FADD_PH|MASK_RM, MASK_FADD_PH|MASK_RM, match_opcode, 0 },
+{"fadd.ph",    0, INSN_CLASS_F,   "D,S,T,m",   MATCH_FADD_PH, MASK_FADD_PH, match_opcode, 0 },
+{"fsub.ph",    0, INSN_CLASS_F,   "D,S,T",     MATCH_FSUB_PH|MASK_RM, MASK_FSUB_PH|MASK_RM, match_opcode, 0 },
+{"fsub.ph",    0, INSN_CLASS_F,   "D,S,T,m",   MATCH_FSUB_PH, MASK_FSUB_PH, match_opcode, 0 },
+{"fmul.ph",    0, INSN_CLASS_F,   "D,S,T",     MATCH_FMUL_PH|MASK_RM, MASK_FMUL_PH|MASK_RM, match_opcode, 0 },
+{"fmul.ph",    0, INSN_CLASS_F,   "D,S,T,m",   MATCH_FMUL_PH, MASK_FMUL_PH, match_opcode, 0 },
+{"fdiv.ph",    0, INSN_CLASS_F,   "D,S,T",     MATCH_FDIV_PH|MASK_RM, MASK_FDIV_PH|MASK_RM, match_opcode, 0 },
+{"fdiv.ph",    0, INSN_CLASS_F,   "D,S,T,m",   MATCH_FDIV_PH, MASK_FDIV_PH, match_opcode, 0 },
+{"fsqrt.ph",   0, INSN_CLASS_F,   "D,S",       MATCH_FSQRT_PH|MASK_RM, MASK_FSQRT_PH|MASK_RM, match_opcode, 0 },
+{"fsqrt.ph",   0, INSN_CLASS_F,   "D,S,m",     MATCH_FSQRT_PH, MASK_FSQRT_PH, match_opcode, 0 },
+{"fmin.ph",    0, INSN_CLASS_F,   "D,S,T",     MATCH_FMIN_PH, MASK_FMIN_PH, match_opcode, 0 },
+{"fmax.ph",    0, INSN_CLASS_F,   "D,S,T",     MATCH_FMAX_PH, MASK_FMAX_PH, match_opcode, 0 },
+
+{"faddx.ph",   0, INSN_CLASS_F,   "D,S,T",     MATCH_FADDX_PH|MASK_RM, MASK_FADDX_PH|MASK_RM, match_opcode, 0 },
+{"faddx.ph",   0, INSN_CLASS_F,   "D,S,T,m",   MATCH_FADDX_PH, MASK_FADDX_PH, match_opcode, 0 },
+{"fsubx.ph",   0, INSN_CLASS_F,   "D,S,T",     MATCH_FSUBX_PH|MASK_RM, MASK_FSUBX_PH|MASK_RM, match_opcode, 0 },
+{"fsubx.ph",   0, INSN_CLASS_F,   "D,S,T,m",   MATCH_FSUBX_PH, MASK_FSUBX_PH, match_opcode, 0 },
+{"fmulx.ph",   0, INSN_CLASS_F,   "D,S,T",     MATCH_FMULX_PH|MASK_RM, MASK_FMULX_PH|MASK_RM, match_opcode, 0 },
+{"fmulx.ph",   0, INSN_CLASS_F,   "D,S,T,m",   MATCH_FMULX_PH, MASK_FMULX_PH, match_opcode, 0 },
+{"fdivx.ph",   0, INSN_CLASS_F,   "D,S,T",     MATCH_FDIVX_PH|MASK_RM, MASK_FDIVX_PH|MASK_RM, match_opcode, 0 },
+{"fdivx.ph",   0, INSN_CLASS_F,   "D,S,T,m",   MATCH_FDIVX_PH, MASK_FDIVX_PH, match_opcode, 0 },
+
+{"faddr.ph",   0, INSN_CLASS_F,   "D,S,T",     MATCH_FADDR_PH|MASK_RM, MASK_FADDR_PH|MASK_RM, match_opcode, 0 },
+{"faddr.ph",   0, INSN_CLASS_F,   "D,S,T,m",   MATCH_FADDR_PH, MASK_FADDR_PH, match_opcode, 0 },
+{"fsubr.ph",   0, INSN_CLASS_F,   "D,S,T",     MATCH_FSUBR_PH|MASK_RM, MASK_FSUBR_PH|MASK_RM, match_opcode, 0 },
+{"fsubr.ph",   0, INSN_CLASS_F,   "D,S,T,m",   MATCH_FSUBR_PH, MASK_FSUBR_PH, match_opcode, 0 },
+{"fmulr.ph",   0, INSN_CLASS_F,   "D,S,T",     MATCH_FMULR_PH|MASK_RM, MASK_FMULR_PH|MASK_RM, match_opcode, 0 },
+{"fmulr.ph",   0, INSN_CLASS_F,   "D,S,T,m",   MATCH_FMULR_PH, MASK_FMULR_PH, match_opcode, 0 },
+{"fdivr.ph",   0, INSN_CLASS_F,   "D,S,T",     MATCH_FDIVR_PH|MASK_RM, MASK_FDIVR_PH|MASK_RM, match_opcode, 0 },
+{"fdivr.ph",   0, INSN_CLASS_F,   "D,S,T,m",   MATCH_FDIVR_PH, MASK_FDIVR_PH, match_opcode, 0 },
+
+{"faddsubr.ph", 0, INSN_CLASS_F,   "D,S,T",     MATCH_FADDSUBR_PH|MASK_RM, MASK_FADDSUBR_PH|MASK_RM, match_opcode, 0 },
+{"faddsubr.ph", 0, INSN_CLASS_F,   "D,S,T,m",   MATCH_FADDSUBR_PH, MASK_FADDSUBR_PH, match_opcode, 0 },
+{"fsubaddr.ph", 0, INSN_CLASS_F,   "D,S,T",     MATCH_FSUBADDR_PH|MASK_RM, MASK_FSUBADDR_PH|MASK_RM, match_opcode, 0 },
+{"fsubaddr.ph", 0, INSN_CLASS_F,   "D,S,T,m",   MATCH_FSUBADDR_PH, MASK_FSUBADDR_PH, match_opcode, 0 },
+
+{"fswap.ph",    0, INSN_CLASS_F,   "D,U",      MATCH_FMVLU_PH, MASK_FMVLU_PH, match_rs1_eq_rs2, INSN_ALIAS },
+{"fmvuu.ph",    0, INSN_CLASS_F,   "D,S,T",    MATCH_FMVUU_PH, MASK_FMVUU_PH, match_opcode, 0 },
+{"fmvll.ph",    0, INSN_CLASS_F,   "D,S,T",    MATCH_FMVLL_PH, MASK_FMVLL_PH, match_opcode, 0 },
+{"fmvul.ph",    0, INSN_CLASS_F,   "D,S,T",    MATCH_FMVUL_PH, MASK_FMVUL_PH, match_opcode, 0 },
+{"fmvlu.ph",    0, INSN_CLASS_F,   "D,S,T",    MATCH_FMVLU_PH, MASK_FMVLU_PH, match_opcode, 0 },
+{"fmvzu.ph",    0, INSN_CLASS_F,   "D,S",      MATCH_FMVZU_PH, MASK_FMVZU_PH, match_opcode, 0 },
+{"fmvzl.ph",    0, INSN_CLASS_F,   "D,S",      MATCH_FMVZL_PH, MASK_FMVZL_PH, match_opcode, 0 },
+
+/* Packed single floating-point instruction subset */
+{"flps",       0, INSN_CLASS_D_AND_C, "D,Cn(Cc)",  MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
+{"flps",       0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
+{"flps",       0, INSN_CLASS_D,   "D,o(s)",    MATCH_FLD, MASK_FLD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
+{"flps",       0, INSN_CLASS_D,   "D,A,s",     0, (int) M_FLD, match_never, INSN_ALIAS|INSN_MACRO },
+{"fsps",       0, INSN_CLASS_D_AND_C, "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
+{"fsps",       0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
+{"fsps",       0, INSN_CLASS_D,   "T,q(s)",    MATCH_FSD, MASK_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
+{"fsps",       0, INSN_CLASS_D,   "T,A,s",     0, (int) M_FSD, match_never, INSN_ALIAS|INSN_MACRO },
+
+{"fmv.x.ps",   0, INSN_CLASS_D,   "d,S",       MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, INSN_ALIAS },
+{"fmv.ps.x",   0, INSN_CLASS_D,   "D,s",       MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, INSN_ALIAS },
+
+{"fmv.ps",     0, INSN_CLASS_D,   "D,U",       MATCH_FSGNJ_PS, MASK_FSGNJ_PS, match_rs1_eq_rs2, INSN_ALIAS },
+{"fneg.ps",    0, INSN_CLASS_D,   "D,U",       MATCH_FSGNJN_PS, MASK_FSGNJN_PS, match_rs1_eq_rs2, INSN_ALIAS },
+{"fabs.ps",    0, INSN_CLASS_D,   "D,U",       MATCH_FSGNJX_PS, MASK_FSGNJX_PS, match_rs1_eq_rs2, INSN_ALIAS },
+{"fsgnj.ps",   0, INSN_CLASS_D,   "D,S,T",     MATCH_FSGNJ_PS, MASK_FSGNJ_PS, match_opcode, 0 },
+{"fsgnjn.ps",  0, INSN_CLASS_D,   "D,S,T",     MATCH_FSGNJN_PS, MASK_FSGNJN_PS, match_opcode, 0 },
+{"fsgnjx.ps",  0, INSN_CLASS_D,   "D,S,T",     MATCH_FSGNJX_PS, MASK_FSGNJX_PS, match_opcode, 0 },
+{"fclass.ps",  0, INSN_CLASS_D,   "d,S",       MATCH_FCLASS_PS, MASK_FCLASS_PS, match_opcode, 0 },
+{"feq.ps",     0, INSN_CLASS_D,   "d,S,T",     MATCH_FEQ_PS, MASK_FEQ_PS, match_opcode, 0 },
+{"flt.ps",     0, INSN_CLASS_D,   "d,S,T",     MATCH_FLT_PS, MASK_FLT_PS, match_opcode, 0 },
+{"fle.ps",     0, INSN_CLASS_D,   "d,S,T",     MATCH_FLE_PS, MASK_FLE_PS, match_opcode, 0 },
+{"fgt.ps",     0, INSN_CLASS_D,   "d,T,S",     MATCH_FLT_PS, MASK_FLT_PS, match_opcode, 0 },
+{"fge.ps",     0, INSN_CLASS_D,   "d,T,S",     MATCH_FLE_PS, MASK_FLE_PS, match_opcode, 0 },
+
+{"fadd.ps",    0, INSN_CLASS_D,   "D,S,T",     MATCH_FADD_PS|MASK_RM, MASK_FADD_PS|MASK_RM, match_opcode, 0 },
+{"fadd.ps",    0, INSN_CLASS_D,   "D,S,T,m",   MATCH_FADD_PS, MASK_FADD_PS, match_opcode, 0 },
+{"fsub.ps",    0, INSN_CLASS_D,   "D,S,T",     MATCH_FSUB_PS|MASK_RM, MASK_FSUB_PS|MASK_RM, match_opcode, 0 },
+{"fsub.ps",    0, INSN_CLASS_D,   "D,S,T,m",   MATCH_FSUB_PS, MASK_FSUB_PS, match_opcode, 0 },
+{"fmul.ps",    0, INSN_CLASS_D,   "D,S,T",     MATCH_FMUL_PS|MASK_RM, MASK_FMUL_PS|MASK_RM, match_opcode, 0 },
+{"fmul.ps",    0, INSN_CLASS_D,   "D,S,T,m",   MATCH_FMUL_PS, MASK_FMUL_PS, match_opcode, 0 },
+{"fdiv.ps",    0, INSN_CLASS_D,   "D,S,T",     MATCH_FDIV_PS|MASK_RM, MASK_FDIV_PS|MASK_RM, match_opcode, 0 },
+{"fdiv.ps",    0, INSN_CLASS_D,   "D,S,T,m",   MATCH_FDIV_PS, MASK_FDIV_PS, match_opcode, 0 },
+{"fsqrt.ps",   0, INSN_CLASS_D,   "D,S",       MATCH_FSQRT_PS|MASK_RM, MASK_FSQRT_PS|MASK_RM, match_opcode, 0 },
+{"fsqrt.ps",   0, INSN_CLASS_D,   "D,S,m",     MATCH_FSQRT_PS, MASK_FSQRT_PS, match_opcode, 0 },
+{"fmin.ps",    0, INSN_CLASS_D,   "D,S,T",     MATCH_FMIN_PS, MASK_FMIN_PS, match_opcode, 0 },
+{"fmax.ps",    0, INSN_CLASS_D,   "D,S,T",     MATCH_FMAX_PS, MASK_FMAX_PS, match_opcode, 0 },
+
+{"faddx.ps",   0, INSN_CLASS_D,   "D,S,T",     MATCH_FADDX_PS|MASK_RM, MASK_FADDX_PS|MASK_RM, match_opcode, 0 },
+{"faddx.ps",   0, INSN_CLASS_D,   "D,S,T,m",   MATCH_FADDX_PS, MASK_FADDX_PS, match_opcode, 0 },
+{"fsubx.ps",   0, INSN_CLASS_D,   "D,S,T",     MATCH_FSUBX_PS|MASK_RM, MASK_FSUBX_PS|MASK_RM, match_opcode, 0 },
+{"fsubx.ps",   0, INSN_CLASS_D,   "D,S,T,m",   MATCH_FSUBX_PS, MASK_FSUBX_PS, match_opcode, 0 },
+{"fmulx.ps",   0, INSN_CLASS_D,   "D,S,T",     MATCH_FMULX_PS|MASK_RM, MASK_FMULX_PS|MASK_RM, match_opcode, 0 },
+{"fmulx.ps",   0, INSN_CLASS_D,   "D,S,T,m",   MATCH_FMULX_PS, MASK_FMULX_PS, match_opcode, 0 },
+{"fdivx.ps",   0, INSN_CLASS_D,   "D,S,T",     MATCH_FDIVX_PS|MASK_RM, MASK_FDIVX_PS|MASK_RM, match_opcode, 0 },
+{"fdivx.ps",   0, INSN_CLASS_D,   "D,S,T,m",   MATCH_FDIVX_PS, MASK_FDIVX_PS, match_opcode, 0 },
+
+{"faddr.ps",   0, INSN_CLASS_D,   "D,S,T",     MATCH_FADDR_PS|MASK_RM, MASK_FADDR_PS|MASK_RM, match_opcode, 0 },
+{"faddr.ps",   0, INSN_CLASS_D,   "D,S,T,m",   MATCH_FADDR_PS, MASK_FADDR_PS, match_opcode, 0 },
+{"fsubr.ps",   0, INSN_CLASS_D,   "D,S,T",     MATCH_FSUBR_PS|MASK_RM, MASK_FSUBR_PS|MASK_RM, match_opcode, 0 },
+{"fsubr.ps",   0, INSN_CLASS_D,   "D,S,T,m",   MATCH_FSUBR_PS, MASK_FSUBR_PS, match_opcode, 0 },
+{"fmulr.ps",   0, INSN_CLASS_D,   "D,S,T",     MATCH_FMULR_PS|MASK_RM, MASK_FMULR_PS|MASK_RM, match_opcode, 0 },
+{"fmulr.ps",   0, INSN_CLASS_D,   "D,S,T,m",   MATCH_FMULR_PS, MASK_FMULR_PS, match_opcode, 0 },
+{"fdivr.ps",   0, INSN_CLASS_D,   "D,S,T",     MATCH_FDIVR_PS|MASK_RM, MASK_FDIVR_PS|MASK_RM, match_opcode, 0 },
+{"fdivr.ps",   0, INSN_CLASS_D,   "D,S,T,m",   MATCH_FDIVR_PS, MASK_FDIVR_PS, match_opcode, 0 },
+
+{"faddsubr.ps", 0, INSN_CLASS_D,   "D,S,T",     MATCH_FADDSUBR_PS|MASK_RM, MASK_FADDSUBR_PS|MASK_RM, match_opcode, 0 },
+{"faddsubr.ps", 0, INSN_CLASS_D,   "D,S,T,m",   MATCH_FADDSUBR_PS, MASK_FADDSUBR_PS, match_opcode, 0 },
+{"fsubaddr.ps", 0, INSN_CLASS_D,   "D,S,T",     MATCH_FSUBADDR_PS|MASK_RM, MASK_FSUBADDR_PS|MASK_RM, match_opcode, 0 },
+{"fsubaddr.ps", 0, INSN_CLASS_D,   "D,S,T,m",   MATCH_FSUBADDR_PS, MASK_FSUBADDR_PS, match_opcode, 0 },
+
+{"fswap.ps",    0, INSN_CLASS_D,   "D,U",      MATCH_FMVLU_PS, MASK_FMVLU_PS, match_rs1_eq_rs2, INSN_ALIAS },
+{"fmvuu.ps",    0, INSN_CLASS_D,   "D,S,T",    MATCH_FMVUU_PS, MASK_FMVUU_PS, match_opcode, 0 },
+{"fmvll.ps",    0, INSN_CLASS_D,   "D,S,T",    MATCH_FMVLL_PS, MASK_FMVLL_PS, match_opcode, 0 },
+{"fmvul.ps",    0, INSN_CLASS_D,   "D,S,T",    MATCH_FMVUL_PS, MASK_FMVUL_PS, match_opcode, 0 },
+{"fmvlu.ps",    0, INSN_CLASS_D,   "D,S,T",    MATCH_FMVLU_PS, MASK_FMVLU_PS, match_opcode, 0 },
+{"fmvzu.ps",    0, INSN_CLASS_D,   "D,S",      MATCH_FMVZU_PS, MASK_FMVZU_PS, match_opcode, 0 },
+{"fmvzl.ps",    0, INSN_CLASS_D,   "D,S",      MATCH_FMVZL_PS, MASK_FMVZL_PS, match_opcode, 0 },
+
+/* Packed double floating-point instruction subset */
+{"flpd",       0, INSN_CLASS_Q,   "D,o(s)",    MATCH_FLQ, MASK_FLQ, match_opcode, INSN_ALIAS|INSN_DREF|INSN_16_BYTE },
+{"flpd",       0, INSN_CLASS_Q,   "D,A,s",     0, (int) M_FLQ, match_never, INSN_ALIAS|INSN_MACRO },
+{"fspd",       0, INSN_CLASS_Q,   "T,q(s)",    MATCH_FSQ, MASK_FSQ, match_opcode, INSN_ALIAS|INSN_DREF|INSN_16_BYTE },
+{"fspd",       0, INSN_CLASS_Q,   "T,A,s",     0, (int) M_FSQ, match_never, INSN_ALIAS|INSN_MACRO },
+
+{"fmv.x.pd",   64, INSN_CLASS_Q,   "d,S",       MATCH_FMV_X_Q, MASK_FMV_X_Q, match_opcode, INSN_ALIAS },
+{"fmv.pd.x",   64, INSN_CLASS_Q,   "D,s",       MATCH_FMV_Q_X, MASK_FMV_Q_X, match_opcode, INSN_ALIAS },
+
+{"fmv.pd",     0, INSN_CLASS_Q,   "D,U",       MATCH_FSGNJ_PD, MASK_FSGNJ_PD, match_rs1_eq_rs2, INSN_ALIAS },
+{"fneg.pd",    0, INSN_CLASS_Q,   "D,U",       MATCH_FSGNJN_PD, MASK_FSGNJN_PD, match_rs1_eq_rs2, INSN_ALIAS },
+{"fabs.pd",    0, INSN_CLASS_Q,   "D,U",       MATCH_FSGNJX_PD, MASK_FSGNJX_PD, match_rs1_eq_rs2, INSN_ALIAS },
+{"fsgnj.pd",   0, INSN_CLASS_Q,   "D,S,T",     MATCH_FSGNJ_PD, MASK_FSGNJ_PD, match_opcode, 0 },
+{"fsgnjn.pd",  0, INSN_CLASS_Q,   "D,S,T",     MATCH_FSGNJN_PD, MASK_FSGNJN_PD, match_opcode, 0 },
+{"fsgnjx.pd",  0, INSN_CLASS_Q,   "D,S,T",     MATCH_FSGNJX_PD, MASK_FSGNJX_PD, match_opcode, 0 },
+{"fclass.pd",  0, INSN_CLASS_Q,   "d,S",       MATCH_FCLASS_PD, MASK_FCLASS_PD, match_opcode, 0 },
+{"feq.pd",     0, INSN_CLASS_Q,   "d,S,T",     MATCH_FEQ_PD, MASK_FEQ_PD, match_opcode, 0 },
+{"flt.pd",     0, INSN_CLASS_Q,   "d,S,T",     MATCH_FLT_PD, MASK_FLT_PD, match_opcode, 0 },
+{"fle.pd",     0, INSN_CLASS_Q,   "d,S,T",     MATCH_FLE_PD, MASK_FLE_PD, match_opcode, 0 },
+{"fgt.pd",     0, INSN_CLASS_Q,   "d,T,S",     MATCH_FLT_PD, MASK_FLT_PD, match_opcode, 0 },
+{"fge.pd",     0, INSN_CLASS_Q,   "d,T,S",     MATCH_FLE_PD, MASK_FLE_PD, match_opcode, 0 },
+
+{"fadd.pd",    0, INSN_CLASS_Q,   "D,S,T",     MATCH_FADD_PD|MASK_RM, MASK_FADD_PD|MASK_RM, match_opcode, 0 },
+{"fadd.pd",    0, INSN_CLASS_Q,   "D,S,T,m",   MATCH_FADD_PD, MASK_FADD_PD, match_opcode, 0 },
+{"fsub.pd",    0, INSN_CLASS_Q,   "D,S,T",     MATCH_FSUB_PD|MASK_RM, MASK_FSUB_PD|MASK_RM, match_opcode, 0 },
+{"fsub.pd",    0, INSN_CLASS_Q,   "D,S,T,m",   MATCH_FSUB_PD, MASK_FSUB_PD, match_opcode, 0 },
+{"fmul.pd",    0, INSN_CLASS_Q,   "D,S,T",     MATCH_FMUL_PD|MASK_RM, MASK_FMUL_PD|MASK_RM, match_opcode, 0 },
+{"fmul.pd",    0, INSN_CLASS_Q,   "D,S,T,m",   MATCH_FMUL_PD, MASK_FMUL_PD, match_opcode, 0 },
+{"fdiv.pd",    0, INSN_CLASS_Q,   "D,S,T",     MATCH_FDIV_PD|MASK_RM, MASK_FDIV_PD|MASK_RM, match_opcode, 0 },
+{"fdiv.pd",    0, INSN_CLASS_Q,   "D,S,T,m",   MATCH_FDIV_PD, MASK_FDIV_PD, match_opcode, 0 },
+{"fsqrt.pd",   0, INSN_CLASS_Q,   "D,S",       MATCH_FSQRT_PD|MASK_RM, MASK_FSQRT_PD|MASK_RM, match_opcode, 0 },
+{"fsqrt.pd",   0, INSN_CLASS_Q,   "D,S,m",     MATCH_FSQRT_PD, MASK_FSQRT_PD, match_opcode, 0 },
+{"fmin.pd",    0, INSN_CLASS_Q,   "D,S,T",     MATCH_FMIN_PD, MASK_FMIN_PD, match_opcode, 0 },
+{"fmax.pd",    0, INSN_CLASS_Q,   "D,S,T",     MATCH_FMAX_PD, MASK_FMAX_PD, match_opcode, 0 },
+
+{"faddx.pd",   0, INSN_CLASS_Q,   "D,S,T",     MATCH_FADDX_PD|MASK_RM, MASK_FADDX_PD|MASK_RM, match_opcode, 0 },
+{"faddx.pd",   0, INSN_CLASS_Q,   "D,S,T,m",   MATCH_FADDX_PD, MASK_FADDX_PD, match_opcode, 0 },
+{"fsubx.pd",   0, INSN_CLASS_Q,   "D,S,T",     MATCH_FSUBX_PD|MASK_RM, MASK_FSUBX_PD|MASK_RM, match_opcode, 0 },
+{"fsubx.pd",   0, INSN_CLASS_Q,   "D,S,T,m",   MATCH_FSUBX_PD, MASK_FSUBX_PD, match_opcode, 0 },
+{"fmulx.pd",   0, INSN_CLASS_Q,   "D,S,T",     MATCH_FMULX_PD|MASK_RM, MASK_FMULX_PD|MASK_RM, match_opcode, 0 },
+{"fmulx.pd",   0, INSN_CLASS_Q,   "D,S,T,m",   MATCH_FMULX_PD, MASK_FMULX_PD, match_opcode, 0 },
+{"fdivx.pd",   0, INSN_CLASS_Q,   "D,S,T",     MATCH_FDIVX_PD|MASK_RM, MASK_FDIVX_PD|MASK_RM, match_opcode, 0 },
+{"fdivx.pd",   0, INSN_CLASS_Q,   "D,S,T,m",   MATCH_FDIVX_PD, MASK_FDIVX_PD, match_opcode, 0 },
+
+{"faddr.pd",   0, INSN_CLASS_Q,   "D,S,T",     MATCH_FADDR_PD|MASK_RM, MASK_FADDR_PD|MASK_RM, match_opcode, 0 },
+{"faddr.pd",   0, INSN_CLASS_Q,   "D,S,T,m",   MATCH_FADDR_PD, MASK_FADDR_PD, match_opcode, 0 },
+{"fsubr.pd",   0, INSN_CLASS_Q,   "D,S,T",     MATCH_FSUBR_PD|MASK_RM, MASK_FSUBR_PD|MASK_RM, match_opcode, 0 },
+{"fsubr.pd",   0, INSN_CLASS_Q,   "D,S,T,m",   MATCH_FSUBR_PD, MASK_FSUBR_PD, match_opcode, 0 },
+{"fmulr.pd",   0, INSN_CLASS_Q,   "D,S,T",     MATCH_FMULR_PD|MASK_RM, MASK_FMULR_PD|MASK_RM, match_opcode, 0 },
+{"fmulr.pd",   0, INSN_CLASS_Q,   "D,S,T,m",   MATCH_FMULR_PD, MASK_FMULR_PD, match_opcode, 0 },
+{"fdivr.pd",   0, INSN_CLASS_Q,   "D,S,T",     MATCH_FDIVR_PD|MASK_RM, MASK_FDIVR_PD|MASK_RM, match_opcode, 0 },
+{"fdivr.pd",   0, INSN_CLASS_Q,   "D,S,T,m",   MATCH_FDIVR_PD, MASK_FDIVR_PD, match_opcode, 0 },
+
+{"faddsubr.pd", 0, INSN_CLASS_Q,   "D,S,T",     MATCH_FADDSUBR_PD|MASK_RM, MASK_FADDSUBR_PD|MASK_RM, match_opcode, 0 },
+{"faddsubr.pd", 0, INSN_CLASS_Q,   "D,S,T,m",   MATCH_FADDSUBR_PD, MASK_FADDSUBR_PD, match_opcode, 0 },
+{"fsubaddr.pd", 0, INSN_CLASS_Q,   "D,S,T",     MATCH_FSUBADDR_PD|MASK_RM, MASK_FSUBADDR_PD|MASK_RM, match_opcode, 0 },
+{"fsubaddr.pd", 0, INSN_CLASS_Q,   "D,S,T,m",   MATCH_FSUBADDR_PD, MASK_FSUBADDR_PD, match_opcode, 0 },
+
+{"fswap.pd",    0, INSN_CLASS_Q,   "D,U",      MATCH_FMVLU_PD, MASK_FMVLU_PD, match_rs1_eq_rs2, INSN_ALIAS },
+{"fmvuu.pd",    0, INSN_CLASS_Q,   "D,S,T",    MATCH_FMVUU_PD, MASK_FMVUU_PD, match_opcode, 0 },
+{"fmvll.pd",    0, INSN_CLASS_Q,   "D,S,T",    MATCH_FMVLL_PD, MASK_FMVLL_PD, match_opcode, 0 },
+{"fmvul.pd",    0, INSN_CLASS_Q,   "D,S,T",    MATCH_FMVUL_PD, MASK_FMVUL_PD, match_opcode, 0 },
+{"fmvlu.pd",    0, INSN_CLASS_Q,   "D,S,T",    MATCH_FMVLU_PD, MASK_FMVLU_PD, match_opcode, 0 },
+{"fmvzu.pd",    0, INSN_CLASS_Q,   "D,S",      MATCH_FMVZU_PD, MASK_FMVZU_PD, match_opcode, 0 },
+{"fmvzl.pd",    0, INSN_CLASS_Q,   "D,S",      MATCH_FMVZL_PD, MASK_FMVZL_PD, match_opcode, 0 },
+
+/* SWAR instruction subset */
+{"swari",       0, INSN_CLASS_I, "d,s,j",     MATCH_SWARI, MASK_SWARI, match_opcode, 0 },
+{"swar",        0, INSN_CLASS_I, "d,s,t",     MATCH_SWAR, MASK_SWAR, match_opcode, 0 },
+{"swar",        0, INSN_CLASS_I, "d,s,t,1",   MATCH_SWAR, MASK_SWAR, match_opcode, 0 },
+{"swar",        0, INSN_CLASS_I, "d,s,j",     MATCH_SWARI, MASK_SWARI, match_opcode, INSN_ALIAS },
+
+
+
 /* Compressed instructions.  */
 {"c.unimp",    0, INSN_CLASS_C,   "",          0, 0xffffU,  match_opcode, 0 },
 {"c.ebreak",   0, INSN_CLASS_C,   "",          MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, 0 },
diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c
index a967842..a20f48a 100644
--- a/opcodes/sparc-opc.c
+++ b/opcodes/sparc-opc.c
@@ -126,6 +126,7 @@
   | HWCAP2_SPARC6 | HWCAP2_ONADDSUB | HWCAP2_ONMUL | HWCAP2_ONDIV \
   | HWCAP2_DICTUNP | HWCAP2_FPCMPSHL | HWCAP2_RLE | HWCAP2_SHA3
 
+#define HWS2_V8 HWCAP2_DQSWAR | HWCAP2_DQFHALF | HWCAP2_DQFCMPLX | HWCAP2_DQFPACK
 
 /* Table of opcode architectures.
    The order is defined in opcode/sparc.h.  */
@@ -134,8 +135,8 @@ const struct sparc_opcode_arch sparc_opcode_archs[] =
 {
   { "v6", MASK_V6, 0, 0 },
   { "v7", MASK_V6 | MASK_V7, 0, 0 },
-  { "v8", MASK_V6 | MASK_V7 | MASK_V8, HWS_V8, 0 },
-  { "leon", MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON, HWS_V8, 0 },
+  { "v8", MASK_V6 | MASK_V7 | MASK_V8, HWS_V8, HWS2_V8 },
+  { "leon", MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON, HWS_V8, HWS2_V8 },
   { "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET, HWS_V8, 0 },
   { "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE, HWS_V8, 0 },
   /* ??? Don't some v8 priviledged insns conflict with v9?  */
@@ -375,6 +376,13 @@ const struct sparc_opcode sparc_opcodes[] = {
 { "lduh",	F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0,	"[i],d", 0, 0, 0, v6 },
 { "lduh",	F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0),	"[1],d", 0, 0, 0, v6 }, /* lduh [rs1+0],d */
 
+{ "ldh",	F3(3, 0x2A, 0), F3(~3, ~0x2A, ~0),		"[1+2],g", 0, 0, 0, v6 },
+{ "ldh",	F3(3, 0x2A, 0), F3(~3, ~0x2A, ~0)|RS2_G0,	"[1],g", 0, 0, 0, v6 }, /* ld [rs1+%g0],d */
+{ "ldh",	F3(3, 0x2A, 1), F3(~3, ~0x2A, ~1),		"[1+i],g", 0, 0, 0, v6 },
+{ "ldh",	F3(3, 0x2A, 1), F3(~3, ~0x2A, ~1),		"[i+1],g", 0, 0, 0, v6 },
+{ "ldh",	F3(3, 0x2A, 1), F3(~3, ~0x2A, ~1)|RS1_G0,	"[i],g", 0, 0, 0, v6 },
+{ "ldh",	F3(3, 0x2A, 1), F3(~3, ~0x2A, ~1)|SIMM13(~0),	"[1],g", 0, 0, 0, v6 }, /* ld [rs1+0],d */
+
 { "ldx",	F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0),	"[1+2],d", 0, 0, 0, v9 },
 { "ldx",	F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0),	"[1],d", 0, 0, 0, v9 }, /* ldx [rs1+%g0],d */
 { "ldx",	F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1),		"[1+i],d", 0, 0, 0, v9 },
@@ -721,6 +729,13 @@ ldtxa (0xEB), /* #ASI_TWINX_SL  */
 { "sth",	F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0,	"d,[i]", 0, 0, 0, v6 },
 { "sth",	F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0),	"d,[1]", 0, 0, 0, v6 }, /* sth d,[rs1+0] */
 
+{ "sth",	F3(3, 0x2E, 0), F3(~3, ~0x2E, ~0)|ASI(~0),		"g,[1+2]", 0, 0, 0, v6 },
+{ "sth",	F3(3, 0x2E, 0), F3(~3, ~0x2E, ~0)|ASI_RS2(~0),		"g,[1]", 0, 0, 0, v6 }, /* st d[rs1+%g0] */
+{ "sth",	F3(3, 0x2E, 1), F3(~3, ~0x2E, ~1),			"g,[1+i]", 0, 0, 0, v6 },
+{ "sth",	F3(3, 0x2E, 1), F3(~3, ~0x2E, ~1),			"g,[i+1]", 0, 0, 0, v6 },
+{ "sth",	F3(3, 0x2E, 1), F3(~3, ~0x2E, ~1)|RS1_G0,		"g,[i]", 0, 0, 0, v6 },
+{ "sth",	F3(3, 0x2E, 1), F3(~3, ~0x2E, ~1)|SIMM13(~0),		"g,[1]", 0, 0, 0, v6 }, /* st d,[rs1+0] */
+
 { "stsh",	F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0),	"d,[1+2]", F_ALIAS, 0, 0, v6 },
 { "stsh",	F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0),	"d,[1]", F_ALIAS, 0, 0, v6 }, /* sth d,[rs1+%g0] */
 { "stsh",	F3(3, 0x06, 1), F3(~3, ~0x06, ~1),		"d,[1+i]", F_ALIAS, 0, 0, v6 },
@@ -1255,6 +1270,13 @@ wrhpr (31, HWCAP_VIS, 0, v9a), /* wrhpr ...,%hstick_cmpr  */
 { "addccc",	F3(2, 0x18, 1), F3(~2, ~0x18, ~1),		"1,i,d", 0, 0, 0, v9 },
 { "addccc",	F3(2, 0x18, 1), F3(~2, ~0x18, ~1),		"i,1,d", 0, 0, 0, v9 },
 
+{ "swar",	F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0),	"1,2,d", 0, 0, HWCAP2_DQSWAR, v8 },
+{ "swar",	F3(2, 0x09, 1), F3(~2, ~0x09, ~1),		"1,i,d", 0, 0, HWCAP2_DQSWAR, v8 },
+{ "swar",	F3(2, 0x09, 1), F3(~2, ~0x09, ~1),		"i,1,d", 0, 0, HWCAP2_DQSWAR, v8 },
+{ "swarcc",	F3(2, 0x19, 0), F3(~2, ~0x19, ~0)|ASI(~0),	"1,2,d", 0, 0, HWCAP2_DQSWAR, v8 },
+{ "swarcc",	F3(2, 0x19, 1), F3(~2, ~0x19, ~1),		"1,i,d", 0, 0, HWCAP2_DQSWAR, v8 },
+{ "swarcc",	F3(2, 0x19, 1), F3(~2, ~0x19, ~1),		"i,1,d", 0, 0, HWCAP2_DQSWAR, v8 },
+
 { "smul",	F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0),	"1,2,d", 0, HWCAP_MUL32, 0, v8 },
 { "smul",	F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1),		"1,i,d", 0, HWCAP_MUL32, 0, v8 },
 { "smul",	F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1),		"i,1,d", 0, HWCAP_MUL32, 0, v8 },
@@ -1769,6 +1791,7 @@ CONDFC  ("fbule", "cb013", 0xe, F_CONDBR),
 { "fdtoi",	F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g", F_FLOAT, 0, 0, v6 },
 { "fstoi",	F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, 0, 0, v6 },
 { "fqtoi",	F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, 0, 0, v8 },
+{ "fhtoi",	F3F(2, 0x34, 0x0d0), F3F(~2, ~0x34, ~0x0d0)|RS1_G0, "f,g", F_FLOAT, 0, HWCAP2_DQFHALF, v8 },
 
 { "fdtox",	F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,H", F_FLOAT, 0, 0, v9 },
 { "fstox",	F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,H", F_FLOAT, 0, 0, v9 },
@@ -1777,6 +1800,7 @@ CONDFC  ("fbule", "cb013", 0xe, F_CONDBR),
 { "fitod",	F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, 0, 0, v6 },
 { "fitos",	F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, 0, 0, v6 },
 { "fitoq",	F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, 0, 0, v8 },
+{ "fitoh",	F3F(2, 0x34, 0x0c0), F3F(~2, ~0x34, ~0x0c0)|RS1_G0, "f,g", F_FLOAT, 0, HWCAP2_DQFHALF, v8 },
 
 { "fxtod",	F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "B,H", F_FLOAT, 0, 0, v9 },
 { "fxtos",	F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "B,g", F_FLOAT, 0, 0, v9 },
@@ -1788,46 +1812,117 @@ CONDFC  ("fbule", "cb013", 0xe, F_CONDBR),
 { "fqtos",	F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", F_FLOAT, 0, 0, v8 },
 { "fstod",	F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H", F_FLOAT, 0, 0, v6 },
 { "fstoq",	F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J", F_FLOAT, 0, 0, v8 },
+{ "fhtos",	F3F(2, 0x34, 0x0c5), F3F(~2, ~0x34, ~0x0c5)|RS1_G0, "f,g", F_FLOAT, 0, HWCAP2_DQFHALF, v8 },
+{ "fstoh",	F3F(2, 0x34, 0x0c1), F3F(~2, ~0x34, ~0x0c1)|RS1_G0, "f,g", F_FLOAT, 0, HWCAP2_DQFHALF, v8 },
 
 { "fdivd",	F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", F_FLOAT, 0, 0, v6 },
 { "fdivq",	F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT, 0, 0, v8 },
 { "fdivx",	F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT|F_ALIAS, 0, 0, v8 },
 { "fdivs",	F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", F_FLOAT, 0, 0, v6 },
+{ "fdivh",	F3F(2, 0x34, 0x04c), F3F(~2, ~0x34, ~0x04c), "e,f,g", F_FLOAT, 0, HWCAP2_DQFHALF, v8 },
+{ "fdivrph",	F3F(2, 0x34, 0x08d), F3F(~2, ~0x34, ~0x08d), "e,f,g", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fdivrps",	F3F(2, 0x34, 0x08e), F3F(~2, ~0x34, ~0x08e), "v,B,H", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fdivph",	F3F(2, 0x34, 0x09d), F3F(~2, ~0x34, ~0x09d), "e,f,g", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fdivps",	F3F(2, 0x34, 0x09e), F3F(~2, ~0x34, ~0x09e), "v,B,H", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fdivxph",	F3F(2, 0x34, 0x0bd), F3F(~2, ~0x34, ~0x0bd), "e,f,g", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fdivxps",	F3F(2, 0x34, 0x0be), F3F(~2, ~0x34, ~0x0be), "v,B,H", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fdivch",	F3F(2, 0x34, 0x05d), F3F(~2, ~0x34, ~0x05d), "e,f,g", F_FLOAT, 0, HWCAP2_DQFCMPLX, v8 },
+{ "fdivcs",	F3F(2, 0x34, 0x05e), F3F(~2, ~0x34, ~0x05e), "v,B,H", F_FLOAT, 0, HWCAP2_DQFCMPLX, v8 },
+
 { "fmuld",	F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", F_FLOAT, 0, 0, v6 },
 { "fmulq",	F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT, 0, 0, v8 },
 { "fmulx",	F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT|F_ALIAS, 0, 0, v8 },
 { "fmuls",	F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", F_FLOAT, 0, 0, v6 },
+{ "fmulh",	F3F(2, 0x34, 0x048), F3F(~2, ~0x34, ~0x048), "e,f,g", F_FLOAT, 0, HWCAP2_DQFHALF, v8 },
+{ "fmulrph",	F3F(2, 0x34, 0x089), F3F(~2, ~0x34, ~0x089), "e,f,g", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fmulrps",	F3F(2, 0x34, 0x08a), F3F(~2, ~0x34, ~0x08a), "v,B,H", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fmulph",	F3F(2, 0x34, 0x099), F3F(~2, ~0x34, ~0x099), "e,f,g", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fmulps",	F3F(2, 0x34, 0x09a), F3F(~2, ~0x34, ~0x09a), "v,B,H", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fmulxph",	F3F(2, 0x34, 0x0b9), F3F(~2, ~0x34, ~0x0b9), "e,f,g", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fmulxps",	F3F(2, 0x34, 0x0ba), F3F(~2, ~0x34, ~0x0ba), "v,B,H", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fmulch",	F3F(2, 0x34, 0x059), F3F(~2, ~0x34, ~0x059), "e,f,g", F_FLOAT, 0, HWCAP2_DQFCMPLX, v8 },
+{ "fmulcs",	F3F(2, 0x34, 0x05a), F3F(~2, ~0x34, ~0x05a), "v,B,H", F_FLOAT, 0, HWCAP2_DQFCMPLX, v8 },
 
 { "fdmulq",	F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT, 0, 0, v8 },
 { "fdmulx",	F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT|F_ALIAS, 0, 0, v8 },
 { "fsmuld",	F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", F_FLOAT, HWCAP_FSMULD, 0, v8 },
+{ "fhmuls",	F3F(2, 0x34, 0x068), F3F(~2, ~0x34, ~0x068), "e,f,g", F_FLOAT, 0, HWCAP2_DQFHALF, v8 },
 
 { "fsqrtd",	F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", F_FLOAT, 0, 0, v7 },
 { "fsqrtq",	F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT, 0, 0, v8 },
 { "fsqrtx",	F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, 0, v8 },
 { "fsqrts",	F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", F_FLOAT, 0, 0, v7 },
+{ "fsqrth",	F3F(2, 0x34, 0x028), F3F(~2, ~0x34, ~0x028)|RS1_G0, "f,g", F_FLOAT, 0, HWCAP2_DQFHALF, v8 },
+{ "fsqrtph",	F3F(2, 0x34, 0x0A9), F3F(~2, ~0x34, ~0x0A9)|RS1_G0, "f,g", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fsqrtps",	F3F(2, 0x34, 0x0Aa), F3F(~2, ~0x34, ~0x0Aa)|RS1_G0, "B,H", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
 
 { "fabsd",	F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0, "B,H", F_FLOAT, 0, 0, v9 },
 { "fabsq",	F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT, 0, 0, v9 },
 { "fabsx",	F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, 0, v9 },
 { "fabss",	F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g", F_FLOAT, 0, 0, v6 },
+{ "fabsh",	F3F(2, 0x34, 0x008), F3F(~2, ~0x34, ~0x008)|RS1_G0, "f,g", F_FLOAT, 0, HWCAP2_DQFHALF, v8 },
+{ "fabsch",	F3F(2, 0x34, 0x0e9), F3F(~2, ~0x34, ~0x0e9)|RS1_G0, "f,g", F_FLOAT, 0, HWCAP2_DQFCMPLX, v8 },
+{ "fabscs",	F3F(2, 0x34, 0x0ea), F3F(~2, ~0x34, ~0x0ea)|RS1_G0, "B,H", F_FLOAT, 0, HWCAP2_DQFCMPLX, v8 },
+
 { "fmovd",	F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0, "B,H", F_FLOAT, 0, 0, v9 },
 { "fmovq",	F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT, 0, 0, v9 },
 { "fmovx",	F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, 0, v9 },
 { "fmovs",	F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", F_FLOAT, 0, 0, v6 },
+{ "fmovh",	F3F(2, 0x34, 0x000), F3F(~2, ~0x34, ~0x000)|RS1_G0, "f,g", F_FLOAT, 0, HWCAP2_DQFHALF, v8 },
+{ "fmovch",	F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", F_FLOAT|F_ALIAS, 0, HWCAP2_DQFCMPLX, v8 },
+{ "fmovcs",	F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0, "B,H", F_FLOAT|F_ALIAS, 0, HWCAP2_DQFCMPLX, v8 },
+
+{ "fmovhu",	F3F(2, 0x34, 0x020), F3F(~2, ~0x34, ~0x020), "e,f,g", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fmovhl",	F3F(2, 0x34, 0x021), F3F(~2, ~0x34, ~0x021), "e,f,g", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fmovhul",	F3F(2, 0x34, 0x022), F3F(~2, ~0x34, ~0x022), "e,f,g", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fmovhlu",	F3F(2, 0x34, 0x023), F3F(~2, ~0x34, ~0x023), "e,f,g", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fswaph",	F3F(2, 0x34, 0x024), F3F(~2, ~0x34, ~0x024)|RS1_G0, "f,g", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fmovhzu",	F3F(2, 0x34, 0x025), F3F(~2, ~0x34, ~0x025)|RS1_G0, "f,g", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fmovhzl",	F3F(2, 0x34, 0x026), F3F(~2, ~0x34, ~0x026)|RS1_G0, "f,g", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+
 { "fnegd",	F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0, "B,H", F_FLOAT, 0, 0, v9 },
 { "fnegq",	F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT, 0, 0, v9 },
 { "fnegx",	F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, 0, v9 },
 { "fnegs",	F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g", F_FLOAT, 0, 0, v6 },
+{ "fnegh",	F3F(2, 0x34, 0x004), F3F(~2, ~0x34, ~0x004)|RS1_G0, "f,g", F_FLOAT, 0, HWCAP2_DQFHALF, v8 },
 
 { "faddd",	F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", F_FLOAT, 0, 0, v6 },
 { "faddq",	F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT, 0, 0, v8 },
 { "faddx",	F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT|F_ALIAS, 0, 0, v8 },
 { "fadds",	F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", F_FLOAT, 0, 0, v6 },
+{ "faddh",	F3F(2, 0x34, 0x040), F3F(~2, ~0x34, ~0x040), "e,f,g", F_FLOAT, 0, HWCAP2_DQFHALF, v8 },
+{ "faddrph",	F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081), "e,f,g", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "faddrps",	F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082), "v,B,H", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "faddph",	F3F(2, 0x34, 0x091), F3F(~2, ~0x34, ~0x091), "e,f,g", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "faddps",	F3F(2, 0x34, 0x092), F3F(~2, ~0x34, ~0x092), "v,B,H", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "faddsubrph",	F3F(2, 0x34, 0x0a1), F3F(~2, ~0x34, ~0x0a1), "e,f,g", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "faddsubrps",	F3F(2, 0x34, 0x0a2), F3F(~2, ~0x34, ~0x0a2), "e,f,g", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "faddxph",	F3F(2, 0x34, 0x0b1), F3F(~2, ~0x34, ~0x0b1), "e,f,g", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "faddxps",	F3F(2, 0x34, 0x0b2), F3F(~2, ~0x34, ~0x0b2), "v,B,H", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "faddch",	F3F(2, 0x34, 0x051), F3F(~2, ~0x34, ~0x051), "e,f,g", F_FLOAT, 0, HWCAP2_DQFCMPLX, v8 },
+{ "faddcs",	F3F(2, 0x34, 0x052), F3F(~2, ~0x34, ~0x052), "v,B,H", F_FLOAT, 0, HWCAP2_DQFCMPLX, v8 },
+
 { "fsubd",	F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", F_FLOAT, 0, 0, v6 },
 { "fsubq",	F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT, 0, 0, v8 },
 { "fsubx",	F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT|F_ALIAS, 0, 0, v8 },
 { "fsubs",	F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", F_FLOAT, 0, 0, v6 },
+{ "fsubh",	F3F(2, 0x34, 0x044), F3F(~2, ~0x34, ~0x044), "e,f,g", F_FLOAT, 0, HWCAP2_DQFHALF, v8 },
+{ "fsubrph",	F3F(2, 0x34, 0x085), F3F(~2, ~0x34, ~0x085), "e,f,g", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fsubrps",	F3F(2, 0x34, 0x086), F3F(~2, ~0x34, ~0x086), "v,B,H", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fsubph",	F3F(2, 0x34, 0x095), F3F(~2, ~0x34, ~0x095), "e,f,g", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fsubps",	F3F(2, 0x34, 0x096), F3F(~2, ~0x34, ~0x096), "v,B,H", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fsubaddrph",	F3F(2, 0x34, 0x0a5), F3F(~2, ~0x34, ~0x0a5), "e,f,g", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fsubaddrps",	F3F(2, 0x34, 0x0a6), F3F(~2, ~0x34, ~0x0a6), "v,B,H", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fsubxph",	F3F(2, 0x34, 0x0b5), F3F(~2, ~0x34, ~0x0b5), "e,f,g", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fsubxps",	F3F(2, 0x34, 0x0b6), F3F(~2, ~0x34, ~0x0b6), "v,B,H", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fsubch",	F3F(2, 0x34, 0x055), F3F(~2, ~0x34, ~0x055), "e,f,g", F_FLOAT, 0, HWCAP2_DQFCMPLX, v8 },
+{ "fsubcs",	F3F(2, 0x34, 0x056), F3F(~2, ~0x34, ~0x056), "v,B,H", F_FLOAT, 0, HWCAP2_DQFCMPLX, v8 },
+
+{ "fconjch",	F3F(2, 0x34, 0x0ed), F3F(~2, ~0x34, ~0x0ed)|RS1_G0, "f,g", F_FLOAT, 0, HWCAP2_DQFCMPLX, v8 },
+{ "fconjcs",	F3F(2, 0x34, 0x0ee), F3F(~2, ~0x34, ~0x0ee)|RS1_G0, "B,H", F_FLOAT, 0, HWCAP2_DQFCMPLX, v8 },
+{ "fargch",	F3F(2, 0x34, 0x0f9), F3F(~2, ~0x34, ~0x0f9)|RS1_G0, "f,g", F_FLOAT, 0, HWCAP2_DQFCMPLX, v8 },
+{ "fargcs",	F3F(2, 0x34, 0x0fa), F3F(~2, ~0x34, ~0x0fa)|RS1_G0, "B,H", F_FLOAT, 0, HWCAP2_DQFCMPLX, v8 },
+
 
 #define CMPFCC(x)	(((x)&0x3)<<25)
 
@@ -1872,6 +1967,39 @@ CONDFC  ("fbule", "cb013", 0xe, F_CONDBR),
 { "fcmpes",	CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055),	 "8,e,f", F_FLOAT, 0, 0, v9 },
 { "fcmpes",	CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055),	 "9,e,f", F_FLOAT, 0, 0, v9 },
 
+{ "fcmph",	          F3F(2, 0x35, 0x050),            F3F(~2, ~0x35, ~0x050)|RD_G0, "e,f",   F_FLOAT, 0, HWCAP2_DQFHALF, v8 },
+{ "fcmph",	CMPFCC(0)|F3F(2, 0x35, 0x050), CMPFCC(~0)|F3F(~2, ~0x35, ~0x050),	 "6,e,f", F_FLOAT, 0, HWCAP2_DQFHALF, v8 },
+{ "fcmph",	CMPFCC(1)|F3F(2, 0x35, 0x050), CMPFCC(~1)|F3F(~2, ~0x35, ~0x050),	 "7,e,f", F_FLOAT, 0, HWCAP2_DQFHALF, v8 },
+{ "fcmph",	CMPFCC(2)|F3F(2, 0x35, 0x050), CMPFCC(~2)|F3F(~2, ~0x35, ~0x050),	 "8,e,f", F_FLOAT, 0, HWCAP2_DQFHALF, v8 },
+{ "fcmph",	CMPFCC(3)|F3F(2, 0x35, 0x050), CMPFCC(~3)|F3F(~2, ~0x35, ~0x050),	 "9,e,f", F_FLOAT, 0, HWCAP2_DQFHALF, v8 },
+{ "fcmpeh",	          F3F(2, 0x35, 0x054),            F3F(~2, ~0x35, ~0x054)|RD_G0, "e,f",   F_FLOAT, 0, HWCAP2_DQFHALF, v8 },
+{ "fcmpeh",	CMPFCC(0)|F3F(2, 0x35, 0x054), CMPFCC(~0)|F3F(~2, ~0x35, ~0x054),	 "6,e,f", F_FLOAT, 0, HWCAP2_DQFHALF, v8 },
+{ "fcmpeh",	CMPFCC(1)|F3F(2, 0x35, 0x054), CMPFCC(~1)|F3F(~2, ~0x35, ~0x054),	 "7,e,f", F_FLOAT, 0, HWCAP2_DQFHALF, v8 },
+{ "fcmpeh",	CMPFCC(2)|F3F(2, 0x35, 0x054), CMPFCC(~2)|F3F(~2, ~0x35, ~0x054),	 "8,e,f", F_FLOAT, 0, HWCAP2_DQFHALF, v8 },
+{ "fcmpeh",	CMPFCC(3)|F3F(2, 0x35, 0x054), CMPFCC(~3)|F3F(~2, ~0x35, ~0x054),	 "9,e,f", F_FLOAT, 0, HWCAP2_DQFHALF, v8 },
+
+{ "fcmpph",	          F3F(2, 0x35, 0x059),            F3F(~2, ~0x35, ~0x059)|RD_G0, "e,f",   F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fcmpph",	CMPFCC(0)|F3F(2, 0x35, 0x059), CMPFCC(~0)|F3F(~2, ~0x35, ~0x059),	 "6,e,f", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fcmpph",	CMPFCC(1)|F3F(2, 0x35, 0x059), CMPFCC(~1)|F3F(~2, ~0x35, ~0x059),	 "7,e,f", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fcmpph",	CMPFCC(2)|F3F(2, 0x35, 0x059), CMPFCC(~2)|F3F(~2, ~0x35, ~0x059),	 "8,e,f", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fcmpph",	CMPFCC(3)|F3F(2, 0x35, 0x059), CMPFCC(~3)|F3F(~2, ~0x35, ~0x059),	 "9,e,f", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fcmpeph",	          F3F(2, 0x35, 0x05d),            F3F(~2, ~0x35, ~0x05d)|RD_G0, "e,f",   F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fcmpeph",	CMPFCC(0)|F3F(2, 0x35, 0x05d), CMPFCC(~0)|F3F(~2, ~0x35, ~0x05d),	 "6,e,f", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fcmpeph",	CMPFCC(1)|F3F(2, 0x35, 0x05d), CMPFCC(~1)|F3F(~2, ~0x35, ~0x05d),	 "7,e,f", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fcmpeph",	CMPFCC(2)|F3F(2, 0x35, 0x05d), CMPFCC(~2)|F3F(~2, ~0x35, ~0x05d),	 "8,e,f", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fcmpeph",	CMPFCC(3)|F3F(2, 0x35, 0x05d), CMPFCC(~3)|F3F(~2, ~0x35, ~0x05d),	 "9,e,f", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+
+{ "fcmpps",	          F3F(2, 0x35, 0x05a),            F3F(~2, ~0x35, ~0x05a)|RD_G0, "e,f",   F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fcmpps",	CMPFCC(0)|F3F(2, 0x35, 0x05a), CMPFCC(~0)|F3F(~2, ~0x35, ~0x05a),	 "6,e,f", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fcmpps",	CMPFCC(1)|F3F(2, 0x35, 0x05a), CMPFCC(~1)|F3F(~2, ~0x35, ~0x05a),	 "7,e,f", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fcmpps",	CMPFCC(2)|F3F(2, 0x35, 0x05a), CMPFCC(~2)|F3F(~2, ~0x35, ~0x05a),	 "8,e,f", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fcmpps",	CMPFCC(3)|F3F(2, 0x35, 0x05a), CMPFCC(~3)|F3F(~2, ~0x35, ~0x05a),	 "9,e,f", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fcmpeps",	          F3F(2, 0x35, 0x05e),            F3F(~2, ~0x35, ~0x05e)|RD_G0, "e,f",   F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fcmpeps",	CMPFCC(0)|F3F(2, 0x35, 0x05e), CMPFCC(~0)|F3F(~2, ~0x35, ~0x05e),	 "6,e,f", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fcmpeps",	CMPFCC(1)|F3F(2, 0x35, 0x05e), CMPFCC(~1)|F3F(~2, ~0x35, ~0x05e),	 "7,e,f", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fcmpeps",	CMPFCC(2)|F3F(2, 0x35, 0x05e), CMPFCC(~2)|F3F(~2, ~0x35, ~0x05e),	 "8,e,f", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+{ "fcmpeps",	CMPFCC(3)|F3F(2, 0x35, 0x05e), CMPFCC(~3)|F3F(~2, ~0x35, ~0x05e),	 "9,e,f", F_FLOAT, 0, HWCAP2_DQFPACK, v8 },
+
 /* These Extended FPop (FIFO) instructions are new in the Fujitsu
    MB86934, replacing the CPop instructions from v6 and later
    processors.  */
-- 
2.20.1