0001-daiteq-support-for-configurable-FPU-and-SWAR-extensi.txt

From df64710e0681422308ec38e8a1b46232f6a6df01 Mon Sep 17 00:00:00 2001
From: Roman Bartosinski <roman@daiteq.com>
Date: Wed, 5 May 2021 12:53:11 +0200
Subject: [PATCH] daiteq support for configurable FPU and SWAR extension for
 Leon CPU

Signed-off-by: Roman Bartosinski <roman@daiteq.com>
---
 clang/include/clang/AST/ASTContext.h          |    7 +
 clang/include/clang/AST/DeclBase.h            |   16 +
 clang/include/clang/AST/RecursiveASTVisitor.h |    7 +
 clang/include/clang/AST/Type.h                |   63 +
 clang/include/clang/AST/TypeLoc.h             |    5 +
 clang/include/clang/AST/TypeProperties.td     |   16 +
 clang/include/clang/ASTMatchers/ASTMatchers.h |    8 +
 clang/include/clang/Basic/Attr.td             |    7 +
 clang/include/clang/Basic/Builtins.def        |   16 +
 clang/include/clang/Basic/CodeGenOptions.def  |   11 +
 clang/include/clang/Basic/DiagnosticGroups.td |    2 +
 .../clang/Basic/DiagnosticSemaKinds.td        |   24 +
 clang/include/clang/Basic/LangOptions.def     |    3 +
 clang/include/clang/Basic/LangOptions.h       |    7 +
 clang/include/clang/Basic/TokenKinds.def      |    1 +
 clang/include/clang/Basic/TypeNodes.td        |    1 +
 clang/include/clang/Basic/TypeTraits.h        |    1 +
 clang/include/clang/Driver/Options.td         |   47 +
 clang/include/clang/Parse/Parser.h            |    5 +
 clang/include/clang/Sema/Initialization.h     |    5 +-
 clang/include/clang/Sema/Sema.h               |   28 +
 .../clang/Serialization/TypeBitCodes.def      |    1 +
 clang/lib/AST/ASTContext.cpp                  |   56 +
 clang/lib/AST/ASTStructuralEquivalence.cpp    |   12 +
 clang/lib/AST/Expr.cpp                        |    9 +
 clang/lib/AST/ExprConstant.cpp                |  248 +++-
 clang/lib/AST/ItaniumMangle.cpp               |   17 +
 clang/lib/AST/JSONNodeDumper.cpp              |    1 +
 clang/lib/AST/MicrosoftMangle.cpp             |    8 +
 clang/lib/AST/Type.cpp                        |   17 +
 clang/lib/AST/TypePrinter.cpp                 |   14 +
 clang/lib/Basic/Targets/Sparc.cpp             |   50 +
 clang/lib/Basic/Targets/Sparc.h               |  110 +-
 clang/lib/CodeGen/CGBuiltin.cpp               |   63 +
 clang/lib/CodeGen/CGCall.cpp                  |   17 +
 clang/lib/CodeGen/CGDebugInfo.cpp             |   23 +
 clang/lib/CodeGen/CGDebugInfo.h               |    3 +
 clang/lib/CodeGen/CGExpr.cpp                  |    8 +
 clang/lib/CodeGen/CGExprScalar.cpp            |   22 +
 clang/lib/CodeGen/CGValue.h                   |   12 +
 clang/lib/CodeGen/CodeGenFunction.cpp         |    4 +
 clang/lib/CodeGen/CodeGenTypes.cpp            |   17 +
 clang/lib/CodeGen/ItaniumCXXABI.cpp           |    6 +
 clang/lib/Driver/ToolChains/Arch/Sparc.cpp    |  364 ++++-
 clang/lib/Driver/ToolChains/Clang.cpp         |   71 +
 clang/lib/Format/FormatToken.h                |    2 +
 clang/lib/Format/TokenAnnotator.cpp           |    4 +-
 clang/lib/Frontend/CompilerInvocation.cpp     |  340 ++++-
 clang/lib/Parse/ParseExpr.cpp                 |   14 +-
 clang/lib/Parse/ParseObjc.cpp                 |    1 +
 clang/lib/Parse/ParsePragma.cpp               |  126 ++
 clang/lib/Parse/ParseTentative.cpp            |    1 +
 clang/lib/Sema/DeclSpec.cpp                   |    2 +-
 clang/lib/Sema/SemaAttr.cpp                   |   39 +
 clang/lib/Sema/SemaCast.cpp                   |    9 +-
 clang/lib/Sema/SemaChecking.cpp               |   10 +
 clang/lib/Sema/SemaExpr.cpp                   |  252 +++-
 clang/lib/Sema/SemaInit.cpp                   |   66 +
 clang/lib/Sema/SemaLookup.cpp                 |    1 +
 clang/lib/Sema/SemaStmt.cpp                   |  362 ++++-
 clang/lib/Sema/SemaTemplate.cpp               |    4 +
 clang/lib/Sema/SemaTemplateDeduction.cpp      |    7 +
 clang/lib/Sema/SemaType.cpp                   |  104 ++
 clang/lib/Sema/TreeTransform.h                |   39 +
 clang/lib/Serialization/ASTReader.cpp         |    4 +
 clang/lib/Serialization/ASTWriter.cpp         |    7 +
 clang/tools/libclang/CIndex.cpp               |    2 +
 llvm/include/llvm/ADT/Triple.h                |    3 +-
 llvm/include/llvm/CodeGen/SelectionDAGNodes.h |    5 +-
 llvm/include/llvm/CodeGen/TargetLowering.h    |    8 +
 llvm/include/llvm/CodeGen/ValueTypes.h        |   38 +-
 llvm/include/llvm/CodeGen/ValueTypes.td       |   17 +-
 llvm/include/llvm/IR/DIBuilder.h              |    8 +
 llvm/include/llvm/IR/DebugInfoFlags.def       |    4 +-
 llvm/include/llvm/IR/DebugInfoMetadata.h      |    1 +
 llvm/include/llvm/IR/DerivedTypes.h           |   32 +
 llvm/include/llvm/IR/InstrTypes.h             |    4 +
 llvm/include/llvm/IR/Instructions.h           |    8 +-
 llvm/include/llvm/IR/Intrinsics.td            |    9 +
 llvm/include/llvm/IR/RuntimeLibcalls.def      |   69 +
 llvm/include/llvm/IR/Type.h                   |    2 +
 llvm/include/llvm/Support/MachineValueType.h  |  129 +-
 llvm/include/llvm/Target/TargetOptions.h      |   51 +
 llvm/lib/Analysis/ValueTracking.cpp           |   14 +-
 llvm/lib/AsmParser/LLLexer.cpp                |    2 +
 llvm/lib/AsmParser/LLParser.cpp               |   63 +-
 llvm/lib/AsmParser/LLToken.h                  |    2 +
 llvm/lib/Bitcode/Reader/BitcodeReader.cpp     |   34 +-
 llvm/lib/Bitcode/Writer/BitcodeWriter.cpp     |   11 +-
 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp |   90 +-
 .../SelectionDAG/LegalizeIntegerTypes.cpp     |   10 +-
 .../lib/CodeGen/SelectionDAG/SelectionDAG.cpp |   75 +-
 .../SelectionDAG/SelectionDAGBuilder.cpp      |   27 +-
 llvm/lib/CodeGen/TargetLoweringBase.cpp       |    2 +
 llvm/lib/CodeGen/ValueTypes.cpp               |   51 +-
 llvm/lib/IR/AsmWriter.cpp                     |   18 +-
 llvm/lib/IR/ConstantFold.cpp                  |    6 +-
 llvm/lib/IR/Constants.cpp                     |   38 +-
 llvm/lib/IR/DIBuilder.cpp                     |   15 +
 llvm/lib/IR/Instructions.cpp                  |  117 +-
 llvm/lib/IR/Type.cpp                          |   36 +-
 llvm/lib/IR/Verifier.cpp                      |   59 +-
 llvm/lib/Support/Triple.cpp                   |    2 +
 llvm/lib/Target/Sparc/DelaySlotFiller.cpp     |    4 +-
 .../Sparc/Disassembler/SparcDisassembler.cpp  |  113 ++
 llvm/lib/Target/Sparc/LeonFeatures.td         |    7 +
 llvm/lib/Target/Sparc/LeonPasses.cpp          |   49 +
 llvm/lib/Target/Sparc/LeonPasses.h            |   13 +
 llvm/lib/Target/Sparc/Sparc.td                |  101 +-
 llvm/lib/Target/Sparc/SparcCallingConv.td     |   10 +-
 llvm/lib/Target/Sparc/SparcISelLowering.cpp   | 1238 ++++++++++++++++-
 llvm/lib/Target/Sparc/SparcISelLowering.h     |   40 +-
 llvm/lib/Target/Sparc/SparcInstrInfo.cpp      |   81 +-
 llvm/lib/Target/Sparc/SparcInstrInfo.td       |  599 +++++++-
 llvm/lib/Target/Sparc/SparcRegisterInfo.td    |   12 +
 llvm/lib/Target/Sparc/SparcSchedule.td        |   35 +
 llvm/lib/Target/Sparc/SparcSubtarget.cpp      |   71 +
 llvm/lib/Target/Sparc/SparcSubtarget.h        |   40 +-
 llvm/lib/Target/Sparc/SparcTargetMachine.cpp  |   94 ++
 llvm/utils/TableGen/CodeGenTarget.cpp         |    8 +
 120 files changed, 6137 insertions(+), 267 deletions(-)

diff --git a/clang/include/clang/AST/ASTContext.h b/clang/include/clang/AST/ASTContext.h
index d5ade9340c8e..19e8c273e400 100644
--- a/clang/include/clang/AST/ASTContext.h
+++ b/clang/include/clang/AST/ASTContext.h
@@ -187,6 +187,7 @@ class ASTContext : public RefCountedBase<ASTContext> {
       DependentAddressSpaceTypes;
   mutable llvm::FoldingSet<VectorType> VectorTypes;
   mutable llvm::FoldingSet<DependentVectorType> DependentVectorTypes;
+  mutable llvm::FoldingSet<SubwordType> SubwordTypes;
   mutable llvm::FoldingSet<FunctionNoProtoType> FunctionNoProtoTypes;
   mutable llvm::ContextualFoldingSet<FunctionProtoType, ASTContext&>
     FunctionProtoTypes;
@@ -1384,6 +1385,12 @@ public:
                                         Expr *AddrSpaceExpr,
                                         SourceLocation AttrLoc) const;
 
+  /// Return the unique reference to sub-word type of the specified type and bit width
+  QualType getSubwordType(QualType T, unsigned BitWidth,
+//                          unsigned PackSize, unsigned NumElems) const;
+                          unsigned Packing) const;
+
+
   /// Return a K&R style C function type like 'int()'.
   QualType getFunctionNoProtoType(QualType ResultTy,
                                   const FunctionType::ExtInfo &Info) const;
diff --git a/clang/include/clang/AST/DeclBase.h b/clang/include/clang/AST/DeclBase.h
index 91c372585b07..3f6098856506 100644
--- a/clang/include/clang/AST/DeclBase.h
+++ b/clang/include/clang/AST/DeclBase.h
@@ -1774,6 +1774,22 @@ protected:
 public:
   ~DeclContext();
 
+  // flags for SWAR operations lower 8 bits is the direct mask for swarctrl (asr22) cmd, upper 8 bits are bitmap
+  enum SwarFlags {
+    reduceFlg    = SWAR_CTRL_REDUCE,
+    saturateFlg  = SWAR_CTRL_SATURATE,
+    normalizeFlg = SWAR_CTRL_NORMALIZE,
+    manualFlg    = (1<<16), /* internal information flag which is not used in swar control word */
+    directMask   = 0xffff,
+  };
+  enum SwarIndices {
+    reduceIdx    = 0,
+    saturateIdx  = 1,
+    normalizeIdx = 2,
+    manualIdx    = 3,
+  };
+  SourceLocation swarPragmaLoc[5]; // 0=reduce, 1=saturate, 2=normalize, 3=manual
+
   Decl::Kind getDeclKind() const {
     return static_cast<Decl::Kind>(DeclContextBits.DeclKind);
   }
diff --git a/clang/include/clang/AST/RecursiveASTVisitor.h b/clang/include/clang/AST/RecursiveASTVisitor.h
index 19dd62b0fe0f..244cae7611cb 100644
--- a/clang/include/clang/AST/RecursiveASTVisitor.h
+++ b/clang/include/clang/AST/RecursiveASTVisitor.h
@@ -1000,6 +1000,9 @@ DEF_TRAVERSE_TYPE(VectorType, { TRY_TO(TraverseType(T->getElementType())); })
 
 DEF_TRAVERSE_TYPE(ExtVectorType, { TRY_TO(TraverseType(T->getElementType())); })
 
+/* the travesing type can be or element (should be) or basic type (the native type for the architecture) */
+DEF_TRAVERSE_TYPE(SubwordType, { TRY_TO(TraverseType(T->getBasicType())); })
+
 DEF_TRAVERSE_TYPE(FunctionNoProtoType,
                   { TRY_TO(TraverseType(T->getReturnType())); })
 
@@ -1235,6 +1238,10 @@ DEF_TRAVERSE_TYPELOC(ExtVectorType, {
   TRY_TO(TraverseType(TL.getTypePtr()->getElementType()));
 })
 
+DEF_TRAVERSE_TYPELOC(SubwordType, {
+  TRY_TO(TraverseType(TL.getTypePtr()->getBasicType()));
+})
+
 DEF_TRAVERSE_TYPELOC(FunctionNoProtoType,
                      { TRY_TO(TraverseTypeLoc(TL.getReturnLoc())); })
 
diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h
index f5955c45fafc..7eaa0f026618 100644
--- a/clang/include/clang/AST/Type.h
+++ b/clang/include/clang/AST/Type.h
@@ -2029,6 +2029,7 @@ public:
   bool isComplexIntegerType() const;            // GCC _Complex integer type.
   bool isVectorType() const;                    // GCC vector type.
   bool isExtVectorType() const;                 // Extended vector type.
+  bool isSubwordType() const;                   // SWAR sub-word type.
   bool isDependentAddressSpaceType() const;     // value-dependent address space qualifier
   bool isObjCObjectPointerType() const;         // pointer to ObjC object
   bool isObjCRetainableType() const;            // ObjC object or block pointer
@@ -3407,6 +3408,64 @@ public:
   }
 };
 
+
+/* -------------------------------------------------------------------------- */
+// subword control word
+#define SWAR_CTRL_SIGNED        (1<<8)
+#define SWAR_CTRL_REDUCE        (1<<9)
+#define SWAR_CTRL_SATURATE      (1<<10)
+#define SWAR_CTRL_NORMALIZE     (1<<11)
+#define SWAR_CTRL_AUDIO         (1<<12)
+#define SWAR_CTRL_VIDEO         (1<<13)
+#define SWAR_CTRL_ALU           (1<<14)
+#define SWAR_CTRL_OP_MASK       (0xFF)
+#define SWAR_CTRL_OP_ADD        (0)
+#define SWAR_CTRL_OP_SUB        (0x08)
+#define SWAR_CTRL_OP_MUL        (0x0C)
+
+/// SubwordType - represents a SWAR sub-word type. This type is created using
+/// __atribute__(__subword__(n,m)) where "n" specifies type width in bits and
+/// "m" specifies number of elements in the array
+class SubwordType : public Type, public llvm::FoldingSetNode {
+protected:
+  friend class ASTContext;
+  /// The basic type of the SWAR sub-word type.
+  QualType BasicType;     /* currently only uint32 */
+  unsigned BitWidth;      /* bit width of each element (1/2/3/4/8/16) */
+  unsigned Packing;       /* Number of elements in each BasicType (if =0, use full packing (size(basetype)/bitwidth) */
+
+public:
+  SubwordType(TypeClass tc, QualType canonType, QualType basicType, unsigned bitWidth);
+  SubwordType(TypeClass tc, QualType canonType, QualType basicType, unsigned bitWidth, unsigned packing);
+
+  /// Return basic type.
+  QualType getBasicType() const { return BasicType; } /* packing word (currently we use only u32) */
+  /// Return size of element in bits.
+  unsigned getBitWidth() const { return BitWidth; }   /* item size (1/2/3/4/8/16 bits) */
+  /// Return Number of elements in basic type.
+  unsigned getPacking() const { return Packing; }   /* packwordwidth (32) / bitwidth (1/2/3/4/8/16) = 32/16/10/8/4/2 */
+
+  bool isSugared() const { return false; }
+  QualType desugar() const { return QualType(this, 0); }
+
+  void Profile(llvm::FoldingSetNodeID &ID) {
+    Profile(ID, getBasicType(), getBitWidth(), getPacking(), getTypeClass());
+  }
+
+  static void Profile(llvm::FoldingSetNodeID &ID, QualType BasicType,
+                      unsigned BitWidth, unsigned Packing, TypeClass TypeClass) {
+    ID.AddPointer(BasicType.getAsOpaquePtr());
+    ID.AddInteger(BitWidth);
+    ID.AddInteger(Packing);
+    ID.AddInteger(TypeClass);
+  }
+
+  static bool classof(const Type *T) {
+    return T->getTypeClass() == Subword;
+  }
+};
+
+
 /// FunctionType - C99 6.7.5.3 - Function Declarators.  This is the common base
 /// class of FunctionNoProtoType and FunctionProtoType.
 class FunctionType : public Type {
@@ -6573,6 +6632,10 @@ inline bool Type::isExtVectorType() const {
   return isa<ExtVectorType>(CanonicalType);
 }
 
+inline bool Type::isSubwordType() const {
+  return isa<SubwordType>(CanonicalType);
+}
+
 inline bool Type::isDependentAddressSpaceType() const {
   return isa<DependentAddressSpaceType>(CanonicalType);
 }
diff --git a/clang/include/clang/AST/TypeLoc.h b/clang/include/clang/AST/TypeLoc.h
index c3baaa3e4174..92f9e9423b1d 100644
--- a/clang/include/clang/AST/TypeLoc.h
+++ b/clang/include/clang/AST/TypeLoc.h
@@ -1759,6 +1759,11 @@ class ExtVectorTypeLoc : public InheritingConcreteTypeLoc<VectorTypeLoc,
                                                           ExtVectorType> {
 };
 
+class SubwordTypeLoc : public InheritingConcreteTypeLoc<TypeSpecTypeLoc,
+                                                        SubwordTypeLoc,
+                                                        SubwordType> {
+};
+
 // FIXME: attribute locations.
 // For some reason, this isn't a subtype of VectorType.
 class DependentSizedExtVectorTypeLoc :
diff --git a/clang/include/clang/AST/TypeProperties.td b/clang/include/clang/AST/TypeProperties.td
index 4df2e2f77e2b..6cf054f24d8f 100644
--- a/clang/include/clang/AST/TypeProperties.td
+++ b/clang/include/clang/AST/TypeProperties.td
@@ -224,6 +224,22 @@ let Class = DependentSizedExtVectorType in {
   }]>;
 }
 
+let Class = SubwordType in {
+  def : Property<"basicType", QualType> {
+    let Read = [{ node->getBasicType() }];
+  }
+  def : Property<"bitWidth", UInt32> {
+    let Read = [{ node->getBitWidth() }];
+  }
+  def : Property<"packing", UInt32> {
+    let Read = [{ node->getPacking() }];
+  }
+
+  def : Creator<[{
+    return ctx.getSubwordType(basicType, bitWidth, packing);
+  }]>;
+}
+
 let Class = FunctionType in {
   def : Property<"returnType", QualType> {
     let Read = [{ node->getReturnType() }];
diff --git a/clang/include/clang/ASTMatchers/ASTMatchers.h b/clang/include/clang/ASTMatchers/ASTMatchers.h
index 7db5f7a5de82..e5dbd958096a 100644
--- a/clang/include/clang/ASTMatchers/ASTMatchers.h
+++ b/clang/include/clang/ASTMatchers/ASTMatchers.h
@@ -2589,6 +2589,14 @@ inline internal::Matcher<Stmt> sizeOfExpr(
       allOf(ofKind(UETT_SizeOf), InnerMatcher)));
 }
 
+/// Same as unaryExprOrTypeTraitExpr, but only matching
+/// sizeofswar.
+inline internal::Matcher<Stmt> sizeOfSwarExpr(
+    const internal::Matcher<UnaryExprOrTypeTraitExpr> &InnerMatcher) {
+  return stmt(unaryExprOrTypeTraitExpr(
+      allOf(ofKind(UETT_SizeOfSwar), InnerMatcher)));
+}
+
 /// Matches NamedDecl nodes that have the specified name.
 ///
 /// Supports specifying enclosing namespaces or classes by prefixing the name
diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td
index d9ca121b6510..7169798d8267 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -2356,6 +2356,13 @@ def Uuid : InheritableAttr {
   let Documentation = [Undocumented];
 }
 
+def Subword : TypeAttr {
+  let Spellings = [GCC<"subword">];
+  let Args = [ExprArgument<"BitWidth">, ExprArgument<"Packing", 1>];
+  let Documentation = [Undocumented];
+  let ASTNode = 0;
+}
+
 def VectorSize : TypeAttr {
   let Spellings = [GCC<"vector_size">];
   let Args = [ExprArgument<"NumBytes">];
diff --git a/clang/include/clang/Basic/Builtins.def b/clang/include/clang/Basic/Builtins.def
index 51d3500df8ae..61a809a9b3b6 100644
--- a/clang/include/clang/Basic/Builtins.def
+++ b/clang/include/clang/Basic/Builtins.def
@@ -1566,6 +1566,22 @@ BUILTIN(__builtin_ms_va_start, "vc*&.", "nt")
 BUILTIN(__builtin_ms_va_end, "vc*&", "n")
 BUILTIN(__builtin_ms_va_copy, "vc*&c*&", "n")
 
+
+// daiteq extensions
+BUILTIN(__builtin_fabsh , "hh"  , "ncF")
+BUILTIN(__builtin_sqrth , "hh"  , "Fne")
+LIBBUILTIN(fabsh, "hh", "fnc", "math.h", C_LANG )
+LIBBUILTIN(sqrth, "hh", "fne", "math.h", C_LANG )
+
+BUILTIN(__builtin_sqrtpf , "V2fV2f"  , "Fne")
+LIBBUILTIN(sqrtpf, "V2fV2f", "fne", "math.h", C_LANG )
+
+
+BUILTIN(__builtin_swarctrl , "vUi"  , "nr")       /* swar set control ASR register - void swarctrl(immconst); */
+BUILTIN(__builtin_swaraccum , "UiUi"  , "n")      /* swar get status/accumulator ASR register - uint32_t swarstat(immconst); uint32_t swarstat("uint32_t") */
+BUILTIN(__builtin_swar , "UiUiUi"  , "nt")        /* call universal swar function (swarctrl must be set manually - "uint32_t" swar("uint32_t","uint32_t")  */
+BUILTIN(__builtin_swarcc , "UiUiUi"  , "nt")      /* call universal swar function with conditions (swarctrl must be set manually - "uint32_t" swarcc("uint32_t","uint32_t") */
+
 #undef BUILTIN
 #undef LIBBUILTIN
 #undef LANGBUILTIN
diff --git a/clang/include/clang/Basic/CodeGenOptions.def b/clang/include/clang/Basic/CodeGenOptions.def
index 7f26ca8b4d61..506efa9ccdff 100644
--- a/clang/include/clang/Basic/CodeGenOptions.def
+++ b/clang/include/clang/Basic/CodeGenOptions.def
@@ -230,6 +230,17 @@ CODEGENOPT(SanitizeCoverageStackDepth, 1, 0) ///< Enable max stack depth tracing
 CODEGENOPT(SanitizeStats     , 1, 0) ///< Collect statistics for sanitizers.
 CODEGENOPT(SimplifyLibCalls  , 1, 1) ///< Set when -fbuiltin is enabled.
 CODEGENOPT(SoftFloat         , 1, 0) ///< -soft-float.
+
+CODEGENOPT(daiteqFPUType  , 32, 0) ///< -daiteq-fpu-enable.
+CODEGENOPT(EnabledSWARdaiteq , 1, 0) ///< -daiteq-swar-enable.
+CODEGENOPT(UseSWARUnit, 32, 0) ///< -daiteq-swar-force-config.
+
+CODEGENOPT(SoftFopsHalf      , 32, 0) /// < -soft-fp-half / -soft-fops-half
+CODEGENOPT(SoftFopsSingle    , 32, 0) /// < -soft-fp-single / -soft-fops-single
+CODEGENOPT(SoftFopsDouble    , 32, 0) /// < -soft-fp-double / -soft-fops-double
+CODEGENOPT(EnabledPackedHalf     , 1, 0) ///< -enable-packedsignle.
+CODEGENOPT(EnabledPackedSingle   , 1, 0) ///< -enable-packedhalf.
+
 CODEGENOPT(SpeculativeLoadHardening, 1, 0) ///< Enable speculative load hardening.
 CODEGENOPT(FineGrainedBitfieldAccesses, 1, 0) ///< Enable fine-grained bitfield accesses.
 CODEGENOPT(StrictEnums       , 1, 0) ///< Optimize based on strict enum definition.
diff --git a/clang/include/clang/Basic/DiagnosticGroups.td b/clang/include/clang/Basic/DiagnosticGroups.td
index 5b2183531a44..41b7ecd5231e 100644
--- a/clang/include/clang/Basic/DiagnosticGroups.td
+++ b/clang/include/clang/Basic/DiagnosticGroups.td
@@ -1149,3 +1149,5 @@ def CrossTU : DiagGroup<"ctu">;
 def CTADMaybeUnsupported : DiagGroup<"ctad-maybe-unsupported">;
 
 def FortifySource : DiagGroup<"fortify-source">;
+
+def SubwordExtension : DiagGroup<"daiteq-subword-extension">;
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index 54299a0409fd..57b5999d1c22 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -891,6 +891,9 @@ def err_pragma_attr_attr_no_push : Error<
   "'#pragma clang attribute' attribute with no matching "
   "'#pragma clang attribute push'">;
 
+def err_swar_pragma_outside_declctx : Error<
+  "'#pragma swar <attribute>' is outside of allowed blocks">;
+
 /// Objective-C parser diagnostics
 def err_duplicate_class_def : Error<
   "duplicate interface definition for class %0">;
@@ -2643,6 +2646,10 @@ def err_attribute_too_few_arguments : Error<
 def err_attribute_invalid_vector_type : Error<"invalid vector element type %0">;
 def err_attribute_bad_neon_vector_size : Error<
   "Neon vector size must be 64 or 128 bits">;
+
+def err_attribute_subword_disabled : Error<"subword type is not allowed (it can be enabled with the correct option)">;
+def err_attribute_subword_oversized : Error<"too many elements %0 with %1b size, basic type has only %2 bits">;
+
 def err_attribute_requires_positive_integer : Error<
   "%0 attribute requires a %select{positive|non-negative}1 "
   "integral compile time constant expression">;
@@ -2760,6 +2767,10 @@ def err_ext_vector_component_exceeds_length : Error<
   "vector component access exceeds type %0">;
 def err_ext_vector_component_name_illegal : Error<
   "illegal vector component name '%0'">;
+
+def err_typecheck_subword_length_not_equal : Error<
+   "subword operands do not have the same number of elements (%0 and %1)">;
+
 def err_attribute_address_space_negative : Error<
   "address space is negative">;
 def err_attribute_address_space_too_high : Error<
@@ -7744,6 +7755,10 @@ def warn_unused_volatile : Warning<
   "expression result unused; assign into a variable to force a volatile load">,
   InGroup<DiagGroup<"unused-volatile-lvalue">>;
 
+def warn_subword_crossover : Warning<
+  "Too many subword operations in a loop - crossover in using">,
+  InGroup<SubwordExtension>;
+
 def ext_cxx14_attr : Extension<
   "use of the %0 attribute is a C++14 extension">, InGroup<CXX14>;
 def ext_cxx17_attr : Extension<
@@ -7881,6 +7896,15 @@ def err_invalid_conversion_between_vector_and_integer : Error<
   "invalid conversion between vector type %0 and integer type %1 "
   "of different size">;
 
+def err_invalid_conversion_between_subwords : Error<
+  "invalid conversion between subword type%diff{ $ and $|}0,1 of different "
+  "size">;
+def err_invalid_conversion_between_subword_and_integer : Error<
+  "invalid conversion between subword type %0 and integer type %1 "
+  "of different size">;
+def err_invalid_conversion_between_subword_and_scalar : Error<
+  "invalid conversion between subword type %0 and scalar type %1">;
+
 def err_opencl_function_pointer : Error<
   "pointers to functions are not allowed">;
 
diff --git a/clang/include/clang/Basic/LangOptions.def b/clang/include/clang/Basic/LangOptions.def
index 82372b098991..fc2b6e74e79f 100644
--- a/clang/include/clang/Basic/LangOptions.def
+++ b/clang/include/clang/Basic/LangOptions.def
@@ -343,6 +343,9 @@ LANGOPT(PaddingOnUnsignedFixedPoint, 1, 0,
 
 LANGOPT(RegisterStaticDestructors, 1, 1, "Register C++ static destructors")
 
+LANGOPT(EnabledSWARdaiteq, 1, 0, "daiteq SWAR extension")
+LANGOPT(UseSWARUnit, 3, SWAR_Unit_ByType, "Use specific SWAR type")
+
 #undef LANGOPT
 #undef COMPATIBLE_LANGOPT
 #undef BENIGN_LANGOPT
diff --git a/clang/include/clang/Basic/LangOptions.h b/clang/include/clang/Basic/LangOptions.h
index ae4a4b2b9e87..f829d1704742 100644
--- a/clang/include/clang/Basic/LangOptions.h
+++ b/clang/include/clang/Basic/LangOptions.h
@@ -229,6 +229,13 @@ public:
     All,
   };
 
+  enum SWARUnit {
+    SWAR_Unit_ByType,
+    SWAR_Unit_Audio,
+    SWAR_Unit_Video,
+    SWAR_Unit_ALU,
+  };
+
 public:
   /// Set of enabled sanitizers.
   SanitizerSet Sanitize;
diff --git a/clang/include/clang/Basic/TokenKinds.def b/clang/include/clang/Basic/TokenKinds.def
index ae908bbdf3a8..cc2dd61c545e 100644
--- a/clang/include/clang/Basic/TokenKinds.def
+++ b/clang/include/clang/Basic/TokenKinds.def
@@ -292,6 +292,7 @@ KEYWORD(return                      , KEYALL)
 KEYWORD(short                       , KEYALL)
 KEYWORD(signed                      , KEYALL)
 KEYWORD(sizeof                      , KEYALL)
+KEYWORD(sizeofswar                  , KEYALL)
 KEYWORD(static                      , KEYALL)
 KEYWORD(struct                      , KEYALL)
 KEYWORD(switch                      , KEYALL)
diff --git a/clang/include/clang/Basic/TypeNodes.td b/clang/include/clang/Basic/TypeNodes.td
index 96d9472a488a..7cebeeb859c5 100644
--- a/clang/include/clang/Basic/TypeNodes.td
+++ b/clang/include/clang/Basic/TypeNodes.td
@@ -69,6 +69,7 @@ def DependentAddressSpaceType : TypeNode<Type>, AlwaysDependent;
 def VectorType : TypeNode<Type>;
 def DependentVectorType : TypeNode<Type>, AlwaysDependent;
 def ExtVectorType : TypeNode<VectorType>;
+def SubwordType : TypeNode<Type>;
 def FunctionType : TypeNode<Type, 1>;
 def FunctionProtoType : TypeNode<FunctionType>;
 def FunctionNoProtoType : TypeNode<FunctionType>;
diff --git a/clang/include/clang/Basic/TypeTraits.h b/clang/include/clang/Basic/TypeTraits.h
index 7c1b571f640c..82762eb99930 100644
--- a/clang/include/clang/Basic/TypeTraits.h
+++ b/clang/include/clang/Basic/TypeTraits.h
@@ -95,6 +95,7 @@ namespace clang {
   /// Names for the "expression or type" traits.
   enum UnaryExprOrTypeTrait {
     UETT_SizeOf,
+    UETT_SizeOfSwar,
     /// Used for C's _Alignof and C++'s alignof.
     /// _Alignof and alignof return the required ABI alignment.
     UETT_AlignOf,
diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td
index 86aee334436a..b16add50dd16 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -153,6 +153,9 @@ def m_x86_Features_Group : OptionGroup<"<x86 features group>">,
 def m_riscv_Features_Group : OptionGroup<"<riscv features group>">,
                              Group<m_Group>, DocName<"RISCV">;
 
+def m_sparc_Features_Group : OptionGroup<"<sparc features group>">,
+                             Group<m_Group>, DocName<"Sparc">;
+
 def m_libc_Group : OptionGroup<"<m libc group>">, Group<m_mips_Features_Group>,
                    Flags<[HelpHidden]>;
 
@@ -2465,6 +2468,50 @@ def msoft_float : Flag<["-"], "msoft-float">, Group<m_Group>, Flags<[CC1Option]>
 def mno_implicit_float : Flag<["-"], "mno-implicit-float">, Group<m_Group>,
   HelpText<"Don't generate implicit floating point instructions">;
 def mimplicit_float : Flag<["-"], "mimplicit-float">, Group<m_Group>;
+
+
+def msoft_fp_half : Flag<["-"], "msoft-fp-half">, Group<m_Group>, Flags<[CC1Option]>,
+  HelpText<"Use soft-float for all floating point operations with half precision numbers">;
+def msoft_fp_single : Flag<["-"], "msoft-fp-single">, Group<m_Group>, Flags<[CC1Option]>,
+  HelpText<"Use soft-float for all floating point operations with single precision numbers">;
+def msoft_fp_double : Flag<["-"], "msoft-fp-double">, Group<m_Group>, Flags<[CC1Option]>,
+  HelpText<"Use soft-float for all floating point operations with double precision numbers">;
+
+def mhard_fp_half : Flag<["-"], "mhard-fp-half">, Group<m_Group>, Flags<[CC1Option]>,
+  HelpText<"Use hard-float for all floating point operations with half precision numbers">;
+def mhard_fp_single : Flag<["-"], "mhard-fp-single">, Group<m_Group>, Flags<[CC1Option]>,
+  HelpText<"Use hard-float for all floating point operations with single precision numbers">;
+def mhard_fp_double : Flag<["-"], "mhard-fp-double">, Group<m_Group>, Flags<[CC1Option]>,
+  HelpText<"Use hard-float for all floating point operations with double precision numbers">;
+
+def msoft_fops_half : Joined<["-"], "msoft-fops-half=">, Group<m_Group>, Flags<[CC1Option]>,
+  HelpText<"Use soft-float for selected FP operations with half precision numbers">;
+def msoft_fops_single : Joined<["-"], "msoft-fops-single=">, Group<m_Group>, Flags<[CC1Option]>,
+  HelpText<"Use soft-float for selected FP operations with single precision numbers">;
+def msoft_fops_double : Joined<["-"], "msoft-fops-double=">, Group<m_Group>, Flags<[CC1Option]>,
+  HelpText<"Use soft-float for selected FP operations with double precision numbers">;
+
+def mhard_fops_half : Joined<["-"], "mhard-fops-half=">, Group<m_Group>, Flags<[CC1Option]>,
+  HelpText<"Use hard-float for selected FP operations with half precision numbers">;
+def mhard_fops_single : Joined<["-"], "mhard-fops-single=">, Group<m_Group>, Flags<[CC1Option]>,
+  HelpText<"Use hard-float for selected FP operations with single precision numbers">;
+def mhard_fops_double : Joined<["-"], "mhard-fops-double=">, Group<m_Group>, Flags<[CC1Option]>,
+  HelpText<"Use hard-float for selected FP operations with double precision numbers">;
+
+def menable_packedhalf : Flag<["-"], "menable-packedhalf">, Group<m_Group>, Flags<[CC1Option]>,
+  HelpText<"Enable packed type for hardware floating point half precision">;
+def menable_packedsingle : Flag<["-"], "menable-packedsingle">, Group<m_Group>, Flags<[CC1Option]>,
+  HelpText<"Enable packed type for hardware floating point single precision">;
+
+def daiteq_fpu_type : Joined<["-"], "daiteq-fpu-type=">, Group<m_Group>, Flags<[CC1Option]>,
+  HelpText<"Select which daiFPU is used (none/dpsp/sphp/dp/sp/hp/php/psp)">;
+def daiteq_swar_enable : Flag<["-"], "daiteq-swar-enable">, Group<m_Group>, Flags<[CC1Option]>,
+  HelpText<"Enable extension for the SWAR instruction extensions">;
+def daiteq_swar_type : Joined<["-"], "daiteq-swar-force-config=">, Group<m_Group>, Flags<[CC1Option]>,
+  Values<"infer,audio,video,alu">,HelpText<"Use specific kind of SWAR unit (infer/audio/video/alu)">;
+def munaligned_packed_fp : Flag<["-"], "munaligned-packed-fp">, Group<m_Group>, Flags<[CC1Option]>,
+  HelpText<"Allow unaligned packed FP variables">;
+
 def mrecip : Flag<["-"], "mrecip">, Group<m_Group>;
 def mrecip_EQ : CommaJoined<["-"], "mrecip=">, Group<m_Group>, Flags<[CC1Option]>;
 def mprefer_vector_width_EQ : Joined<["-"], "mprefer-vector-width=">, Group<m_Group>, Flags<[CC1Option]>,
diff --git a/clang/include/clang/Parse/Parser.h b/clang/include/clang/Parse/Parser.h
index 4778dc9d3df8..008a4de070a5 100644
--- a/clang/include/clang/Parse/Parser.h
+++ b/clang/include/clang/Parse/Parser.h
@@ -202,6 +202,11 @@ class Parser : public CodeCompletionHandler {
   std::unique_ptr<PragmaHandler> STDCUnknownHandler;
   std::unique_ptr<PragmaHandler> AttributePragmaHandler;
 
+  std::unique_ptr<PragmaHandler> SwarSaturateHandler;
+  std::unique_ptr<PragmaHandler> SwarReductionHandler;
+  std::unique_ptr<PragmaHandler> SwarNormalizeHandler;
+  std::unique_ptr<PragmaHandler> SwarManualHandler;
+
   std::unique_ptr<CommentHandler> CommentSemaHandler;
 
   /// Whether the '>' token acts as an operator or not. This will be
diff --git a/clang/include/clang/Sema/Initialization.h b/clang/include/clang/Sema/Initialization.h
index f726f3836307..31b5147759e1 100644
--- a/clang/include/clang/Sema/Initialization.h
+++ b/clang/include/clang/Sema/Initialization.h
@@ -89,6 +89,9 @@ public:
     /// or vector.
     EK_VectorElement,
 
+    /// The entity being initialized is an element of a subword.
+    EK_SubWordElement,
+
     /// The entity being initialized is a field of block descriptor for
     /// the copied-in c++ object.
     EK_BlockElement,
@@ -504,7 +507,7 @@ public:
   /// element, sets the element index.
   void setElementIndex(unsigned Index) {
     assert(getKind() == EK_ArrayElement || getKind() == EK_VectorElement ||
-           getKind() == EK_ComplexElement);
+           getKind() == EK_ComplexElement || getKind() == EK_SubWordElement);
     this->Index = Index;
   }
 
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index 2d7aa9462db1..03fb60f7d300 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -370,6 +370,9 @@ class Sema final {
                                       QualType ResultTy,
                                       ArrayRef<QualType> Args);
 
+  int theLastSubwordOperation = 0;
+  bool inForLoopSubwordChecking = false;
+
 public:
   typedef OpaquePtr<DeclGroupRef> DeclGroupPtrTy;
   typedef OpaquePtr<TemplateName> TemplateTy;
@@ -1544,6 +1547,9 @@ public:
   QualType BuildAddressSpaceAttr(QualType &T, Expr *AddrSpace,
                                  SourceLocation AttrLoc);
 
+  QualType BuildSubwordType(QualType BasicType, unsigned BitWidth,
+                            unsigned Packing, SourceLocation AttrLoc);
+
   bool CheckQualifiedFunctionForTypeId(QualType T, SourceLocation Loc);
 
   bool CheckFunctionReturnType(QualType T, SourceLocation Loc);
@@ -10681,6 +10687,9 @@ public:
   QualType CheckVectorLogicalOperands(ExprResult &LHS, ExprResult &RHS,
                                       SourceLocation Loc);
 
+  QualType CheckSubwordOperands(ExprResult &LHS, ExprResult &RHS,
+                                SourceLocation Loc, bool IsCompAssign);
+
   bool areLaxCompatibleVectorTypes(QualType srcType, QualType destType);
   bool isLaxVectorConversion(QualType srcType, QualType destType);
 
@@ -10757,6 +10766,11 @@ public:
   ExprResult CheckExtVectorCast(SourceRange R, QualType DestTy, Expr *CastExpr,
                                 CastKind &Kind);
 
+  bool areCompatibleSubwordTypes(QualType srcTy, QualType destTy);
+  bool CheckSubwordCast(SourceRange R, QualType SubwordTy, QualType Ty,
+                       CastKind &Kind);
+  ExprResult prepareSubwordSplat(QualType SubwordTy, Expr *SplattedExpr);
+
   ExprResult BuildCXXFunctionalCastExpr(TypeSourceInfo *TInfo, QualType Type,
                                         SourceLocation LParenLoc,
                                         Expr *CastExpr,
@@ -11640,6 +11654,20 @@ private:
   /// statement that produces control flow different from GCC.
   void CheckBreakContinueBinding(Expr *E);
 
+
+  // check and return type of swar operand or result - =0 no subword type, =1 subword, =2 array of subwords
+  int CheckSwarOperandType(Stmt *SubStmt, int *outBitWidth, bool *isSigned);
+public:
+  void ActOnPragmaSwarSaturate(SourceLocation PragmaLoc, Scope *curScope, bool enbl);
+  void ActOnPragmaSwarReduce(SourceLocation PragmaLoc, Scope *curScope, bool enbl);
+  void ActOnPragmaSwarNormalize(SourceLocation PragmaLoc, Scope *curScope, bool enbl);
+  void ActOnPragmaSwarManual(SourceLocation PragmaLoc, Scope *curScope, bool enbl);
+private:
+  Stmt *BuildSwarCtrlComp(Stmt *SubStmt, SourceLocation pos, int swop);
+  int CheckSwarArrayOperation(Stmt *block);
+  int CheckSwarOperation(Stmt *sop);
+
+
   /// Check whether receiver is mutable ObjC container which
   /// attempts to add itself into the container
   void CheckObjCCircularContainer(ObjCMessageExpr *Message);
diff --git a/clang/include/clang/Serialization/TypeBitCodes.def b/clang/include/clang/Serialization/TypeBitCodes.def
index 38c73ccb7daf..574a9a956692 100644
--- a/clang/include/clang/Serialization/TypeBitCodes.def
+++ b/clang/include/clang/Serialization/TypeBitCodes.def
@@ -58,5 +58,6 @@ TYPE_BIT_CODE(DependentSizedExtVector, DEPENDENT_SIZED_EXT_VECTOR, 46)
 TYPE_BIT_CODE(DependentAddressSpace, DEPENDENT_ADDRESS_SPACE, 47)
 TYPE_BIT_CODE(DependentVector, DEPENDENT_SIZED_VECTOR, 48)
 TYPE_BIT_CODE(MacroQualified, MACRO_QUALIFIED, 49)
+TYPE_BIT_CODE(Subword, SUBWORD, 50)
 
 #undef TYPE_BIT_CODE
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index d26e7f789d0a..2ef62d175cbf 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -1887,6 +1887,17 @@ TypeInfo ASTContext::getTypeInfoImpl(const Type *T) const {
     break;
   }
 
+  case Type::Subword: {
+    const auto *VT = cast<SubwordType>(T);
+    TypeInfo BasInfo = getTypeInfo(VT->getBasicType());
+    //unsigned ne = VT->getNumElements();
+    //if (!ne) ne = 1;
+    //Width = ne*VT->getBitWidth();
+    Width = VT->getPacking()*VT->getBitWidth();
+    Align = BasInfo.Align;
+    break;
+  }
+
   case Type::Builtin:
     switch (cast<BuiltinType>(T)->getKind()) {
     default: llvm_unreachable("Unknown builtin type!");
@@ -3302,6 +3313,7 @@ QualType ASTContext::getVariableArrayDecayedType(QualType type) const {
   case Type::Vector:
   case Type::DependentVector:
   case Type::ExtVector:
+  case Type::Subword:
   case Type::DependentSizedExtVector:
   case Type::DependentAddressSpace:
   case Type::ObjCObject:
@@ -3692,6 +3704,44 @@ ASTContext::getDependentSizedExtVectorType(QualType vecType,
   return QualType(New, 0);
 }
 
+/// getSubwordType - Return the unique reference to a subword type of the
+/// specified type and bit width. Basic type must be a build-in type.
+QualType
+ASTContext::getSubwordType(QualType T, unsigned BitWidth,
+                           unsigned Packing) const {
+  assert(T->isBuiltinType());
+
+  // Check if we've already instantiated a vector of this type.
+  llvm::FoldingSetNodeID ID;
+  SubwordType::Profile(ID, T, BitWidth, Packing, Type::Subword);
+
+  void *InsertPos = nullptr;
+  if (SubwordType *SWTP = SubwordTypes.FindNodeOrInsertPos(ID, InsertPos)) {
+    return QualType(SWTP, 0);
+  }
+
+  // If the basic type isn't canonical, this won't be a canonical type either,
+  // so fill in the canonical type field.
+  QualType Canonical;
+  if (!T.isCanonical()) {
+    /* TODO: ArrLen can be different if the canonical type has different size */
+    Canonical = getSubwordType(getCanonicalType(T), BitWidth, Packing);
+
+    // Get the new insert position for the node we care about.
+    SubwordType *NewIP = SubwordTypes.FindNodeOrInsertPos(ID, InsertPos);
+    assert(!NewIP && "Shouldn't be in the map!");
+    (void)NewIP;
+  }
+  auto *New = new(*this, TypeAlignment)
+                SubwordType(Type::Subword, Canonical, T, BitWidth, Packing);
+//  if (New) {
+//    New->setArrLength(ArrLen);
+//  }
+  SubwordTypes.InsertNode(New, InsertPos);
+  Types.push_back(New);
+  return QualType(New, 0);
+}
+
 QualType ASTContext::getDependentAddressSpaceType(QualType PointeeType,
                                                   Expr *AddrSpaceExpr,
                                                   SourceLocation AttrLoc) const {
@@ -7172,6 +7222,7 @@ void ASTContext::getObjCEncodingForTypeImpl(QualType T, std::string &S,
   //FIXME. We should do a better job than gcc.
   case Type::Vector:
   case Type::ExtVector:
+  case Type::Subword:
   // Until we have a coherent encoding of these three types, issue warning.
     if (NotEncodedT)
       *NotEncodedT = T;
@@ -9198,6 +9249,11 @@ QualType ASTContext::mergeTypes(QualType LHS, QualType RHS,
                              RHSCan->castAs<VectorType>()))
       return LHS;
     return {};
+
+  case Type::Subword:
+    // SubwordType MergeTypes ... eliminated above
+    return {};
+
   case Type::ObjCObject: {
     // Check if the types are assignment compatible.
     // FIXME: This should be type compatibility, e.g. whether
diff --git a/clang/lib/AST/ASTStructuralEquivalence.cpp b/clang/lib/AST/ASTStructuralEquivalence.cpp
index db48405055cd..ebe166d77e3c 100644
--- a/clang/lib/AST/ASTStructuralEquivalence.cpp
+++ b/clang/lib/AST/ASTStructuralEquivalence.cpp
@@ -623,6 +623,18 @@ static bool IsStructurallyEquivalent(StructuralEquivalenceContext &Context,
     break;
   }
 
+  case Type::Subword: {
+    const auto Sw1 = cast<SubwordType>(T1);
+    const auto Sw2 = cast<SubwordType>(T2);
+    if (!IsStructurallyEquivalent(Context, Sw1->getBasicType(), Sw2->getBasicType()))
+      return false;
+    if (Sw1->getBitWidth()!=Sw2->getBitWidth())
+      return false;
+    if (Sw1->getPacking()!=Sw2->getPacking())
+      return false;
+    break;
+  }
+
   case Type::FunctionProto: {
     const auto *Proto1 = cast<FunctionProtoType>(T1);
     const auto *Proto2 = cast<FunctionProtoType>(T2);
diff --git a/clang/lib/AST/Expr.cpp b/clang/lib/AST/Expr.cpp
index 5c9ceac854cf..0cd53930f521 100644
--- a/clang/lib/AST/Expr.cpp
+++ b/clang/lib/AST/Expr.cpp
@@ -3255,6 +3255,15 @@ bool Expr::isConstantInitializer(ASTContext &Ctx, bool IsForRef,
       return true;
     }
 
+    if (ILE->getType()->isSubwordType()) {
+      unsigned numInits = ILE->getNumInits();
+      for (unsigned i = 0; i < numInits; i++) {
+        if (!ILE->getInit(i)->isConstantInitializer(Ctx, false, Culprit))
+          return false;
+      }
+      return true;
+    }
+
     if (ILE->getType()->isRecordType()) {
       unsigned ElementNo = 0;
       RecordDecl *RD = ILE->getType()->castAs<RecordType>()->getDecl();
diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp
index 7e33b9d354b0..cce32328df5b 100644
--- a/clang/lib/AST/ExprConstant.cpp
+++ b/clang/lib/AST/ExprConstant.cpp
@@ -2072,7 +2072,7 @@ static bool CheckLValueConstantExpression(EvalInfo &Info, SourceLocation Loc,
       }
 
       APValue *V = MTE->getOrCreateValue(false);
-      assert(V && "evasluation result refers to uninitialised temporary");
+      assert(V && "evaluation result refers to uninitialised temporary");
       if (!CheckEvaluationResult(CheckEvaluationResultKind::ConstantExpression,
                                  Info, MTE->getExprLoc(), TempType, *V,
                                  Usage, SourceLocation(), CheckedTemps))
@@ -2764,7 +2764,38 @@ static bool HandleSizeof(EvalInfo &Info, SourceLocation Loc,
     return false;
   }
 
+  if (Type->isSubwordType()) {
+    auto tp = Type->castAs<SubwordType>()->getBasicType();
+    Size = Info.Ctx.getTypeSizeInChars(tp);
+    return true;
+  }
+
   Size = Info.Ctx.getTypeSizeInChars(Type);
+
+  return true;
+}
+
+
+/// Get the size of the swar type in bits. (It returns All other types
+static bool HandleSizeofSwar(EvalInfo &Info, SourceLocation Loc,
+                         QualType Type, unsigned &Size) {
+  if (!Type->isSubwordType()) {
+    Size = 0;
+    return true;
+  }
+
+  if (Type->isDependentType()) {
+    Info.FFDiag(Loc);
+    return false;
+  }
+
+  if (!Type->isConstantSizeType()) {
+    // sizeof(vla) is not a constantexpr: C99 6.5.3.4p2.
+    // FIXME: Better diagnostic.
+    Info.FFDiag(Loc);
+    return false;
+  }
+  Size = Type->castAs<SubwordType>()->getBitWidth();
   return true;
 }
 
@@ -7650,7 +7681,8 @@ bool LValueExprEvaluator::VisitMemberExpr(const MemberExpr *E) {
 
 bool LValueExprEvaluator::VisitArraySubscriptExpr(const ArraySubscriptExpr *E) {
   // FIXME: Deal with vectors as array subscript bases.
-  if (E->getBase()->getType()->isVectorType())
+  if (E->getBase()->getType()->isVectorType() ||
+      E->getBase()->getType()->isSubwordType())
     return Error(E);
 
   bool Success = true;
@@ -9461,6 +9493,172 @@ bool VectorExprEvaluator::VisitUnaryImag(const UnaryOperator *E) {
   return ZeroInitialization(E);
 }
 
+//===----------------------------------------------------------------------===//
+// Subword Evaluation
+//===----------------------------------------------------------------------===//
+
+namespace {
+  class SubwordExprEvaluator
+  : public ExprEvaluatorBase<SubwordExprEvaluator> {
+    APValue &Result;
+  public:
+
+    SubwordExprEvaluator(EvalInfo &info, APValue &Result)
+      : ExprEvaluatorBaseTy(info), Result(Result) {}
+
+/* the evaluator should interpret its value as one value of the basic type or an array of elements of the element type */
+    bool Success(APValue V, const Expr *E) {
+      assert(V.isInt());
+      // FIXME: remove this APValue copy.
+      Result = V;
+      return true;
+    }
+
+    bool ZeroInitialization(const Expr *E);
+
+    bool VisitIntegerLiteral(const IntegerLiteral *E) {
+      APValue Val = APValue(APSInt(E->getValue()));
+      return Success(Val, E);
+    }
+
+    bool VisitCastExpr(const CastExpr* E);
+    bool VisitInitListExpr(const InitListExpr *E);
+    bool VisitUnaryImag(const UnaryOperator *E);
+  };
+} // end anonymous namespace
+
+static bool EvaluateSubword(const Expr* E, APValue& Result, EvalInfo &Info) {
+  assert(E->isRValue() && E->getType()->isSubwordType() && "not a subword rvalue");
+  return SubwordExprEvaluator(Info, Result).Visit(E);
+}
+
+bool SubwordExprEvaluator::VisitCastExpr(const CastExpr *E) {
+  const SubwordType *VTy = E->getType()->castAs<SubwordType>();
+  unsigned NElts = VTy->getPacking();
+
+  const Expr *SE = E->getSubExpr();
+  QualType SETy = SE->getType();
+
+  switch (E->getCastKind()) {
+  case CK_VectorSplat: {        // as for vector; fill all elements with a value: __attribute__((ext_vector_type(4))) int v = 5;
+    APValue Val = APValue();
+    if (SETy->isIntegerType()) {
+      APSInt IntResult;
+      if (!EvaluateInteger(SE, IntResult, Info))
+        return false;
+
+      Val = APValue(std::move(IntResult));
+    } else {
+      return Error(E);
+    }
+
+    // Splat and create APValue. NElts x Val
+    APValue Elt(Val);
+    return Success(Elt, E);
+  }
+  case CK_BitCast: {
+    // Evaluate the operand into an APInt we can extract from.
+    llvm::APInt SValInt;
+    if (!EvalAndBitcastToAPInt(Info, SE, SValInt))
+      return false;
+    // Extract the elements
+    unsigned EltSize = VTy->getBitWidth();
+    bool BigEndian = Info.Ctx.getTargetInfo().isBigEndian();
+    llvm::APInt Elts = llvm::APInt(32, 0, false); /* TODO: change fixed width to bitwidth of subword basicType */
+    for (unsigned i = 0; i < NElts; i++) {
+      if (BigEndian)
+        Elts += SValInt.rotl(i*EltSize+EltSize).zextOrTrunc(EltSize);
+      else
+        Elts += SValInt.rotr(i*EltSize).zextOrTrunc(EltSize);
+    }
+    APValue Val = APValue(APSInt(Elts));
+    return Success(Val, E);
+  }
+  default:
+    return ExprEvaluatorBaseTy::VisitCastExpr(E);
+  }
+}
+
+bool SubwordExprEvaluator::VisitInitListExpr(const InitListExpr *E) {
+  const SubwordType *VT = E->getType()->castAs<SubwordType>();
+  unsigned NumInits = E->getNumInits();
+
+  unsigned NumElements = VT->getPacking();
+  QualType BasTy = VT->getBasicType();
+  unsigned ElmBW = VT->getBitWidth();
+  // SW basic type sign ???
+  bool BasTpIsSigned = false;
+  const Type *BTT = BasTy.getTypePtrOrNull();
+  if (BTT && BTT->isSignedIntegerOrEnumerationType()) BasTpIsSigned = true;
+  // element limits
+  int ernglow, ernghi;
+  bool BigEndian = Info.Ctx.getTargetInfo().isBigEndian();
+
+  if (BasTpIsSigned) {
+    ernglow = -(1<<(ElmBW-1));
+    ernghi = (1<<(ElmBW-1))-1;
+  } else {
+    ernglow = 0;
+    ernghi = (1<<ElmBW)-1;
+  }
+
+  APValue Val = APValue();
+
+  // The number of initializers can be less than the number of subword
+  // elements. Missing trailing elements should be initialized with zeroes.
+  unsigned CountInits = 0, CountElts = 0;
+  llvm::APInt sInt(32, true);
+  uint32_t swval = 0;
+  while (CountElts < NumElements) {
+    // Handle nested vector initialization.
+    //if (CountInits < NumInits
+        //&& E->getInit(CountInits)->getType()->isVectorType()) {
+      //APValue v;
+      //if (!EvaluateVector(E->getInit(CountInits), v, Info))
+        //return Error(E);
+      //unsigned vlen = v.getVectorLength();
+      //for (unsigned j = 0; j < vlen; j++)
+        //Elements.push_back(v.getVectorElt(j));
+      //CountElts += vlen;
+    //} else
+    if (BasTy->isIntegerType()) {
+      if (CountInits < NumInits) {
+        if (!EvalAndBitcastToAPInt(Info, E->getInit(CountInits), sInt))
+          return false;
+        int64_t ev = sInt.getSExtValue();
+        if (ev<ernglow || ev>ernghi)
+          return false;
+        uint32_t v = ((uint32_t)(ev & ((1<<ElmBW)-1)))<<(CountElts*ElmBW);
+/* TODO: respect BigEndian */
+        swval += v;
+      }
+      //} else // trailing integer zero.
+        //sInt = Info.Ctx.MakeIntValue(0, BasTy);
+      CountElts++;
+    }
+    CountInits++;
+  }
+  llvm::APInt swarVal(32, swval, false); /* TODO: change fixed width with size of BasicType */
+  Val = APValue(APSInt(swarVal));
+  return Success(Val, E);
+}
+
+bool SubwordExprEvaluator::ZeroInitialization(const Expr *E) {
+  const auto *VT = E->getType()->castAs<SubwordType>();
+  QualType BasTy = VT->getBasicType();
+  APValue ZeroVal;
+  if (BasTy->isIntegerType())
+    ZeroVal = APValue(Info.Ctx.MakeIntValue(0, BasTy));
+  else
+    return Error(E);
+  return Success(ZeroVal, E);
+}
+
+bool SubwordExprEvaluator::VisitUnaryImag(const UnaryOperator *E) {
+  VisitIgnoredValue(E->getSubExpr());
+  return ZeroInitialization(E);
+}
+
 //===----------------------------------------------------------------------===//
 // Array Evaluation
 //===----------------------------------------------------------------------===//
@@ -10141,6 +10339,9 @@ EvaluateBuiltinClassifyType(QualType T, const LangOptions &LangOpts) {
     // other types that don't fit into the regular classification the same way.
     return GCCTypeClass::None;
 
+  case Type::Subword:
+    return GCCTypeClass::None;
+
   case Type::LValueReference:
   case Type::RValueReference:
     llvm_unreachable("invalid type for expression");
@@ -10642,6 +10843,30 @@ bool IntExprEvaluator::VisitBuiltinCallExpr(const CallExpr *E,
     return Success(Val.countLeadingZeros(), E);
   }
 
+  case Builtin::BI__builtin_swarctrl: {
+    APSInt Val;
+    if (!EvaluateInteger(E->getArg(0), Val, Info))
+      return false;
+    if (!Val)
+      return Error(E);
+    if (Val.isNegative()) /* cannot be a negative value */
+      return Error(E);
+    return Success(Val, E);
+  }
+
+  case Builtin::BI__builtin_swaraccum: {
+    APSInt Val;
+    if (!EvaluateInteger(E->getArg(0), Val, Info)) {
+      return false;
+    }
+    if (!Val)
+      return Error(E);
+    if (Val.isNegative()) /* cannot be a negative value */
+      return Error(E);
+    return true;
+  }
+
+
   case Builtin::BI__builtin_constant_p: {
     const Expr *Arg = E->getArg(0);
     if (EvaluateBuiltinConstantP(Info, Arg))
@@ -12040,6 +12265,17 @@ bool IntExprEvaluator::VisitUnaryExprOrTypeTraitExpr(
       return false;
     return Success(Sizeof, E);
   }
+  case UETT_SizeOfSwar:
+  {
+    QualType SrcTy = E->getTypeOfArgument();
+    if (const ReferenceType *Ref = SrcTy->getAs<ReferenceType>())
+      SrcTy = Ref->getPointeeType();
+
+    unsigned SoS;
+    if (!HandleSizeofSwar(Info, E->getExprLoc(), SrcTy, SoS))
+      return false;
+    return Success(SoS, E);
+  }
   case UETT_OpenMPRequiredSimdAlign:
     assert(E->isArgumentType());
     return Success(
@@ -12587,6 +12823,7 @@ bool FloatExprEvaluator::VisitCallExpr(const CallExpr *E) {
     return true;
 
   case Builtin::BI__builtin_fabs:
+  case Builtin::BI__builtin_fabsh:
   case Builtin::BI__builtin_fabsf:
   case Builtin::BI__builtin_fabsl:
   case Builtin::BI__builtin_fabsf128:
@@ -13386,6 +13623,9 @@ static bool Evaluate(APValue &Result, EvalInfo &Info, const Expr *E) {
   } else if (T->isVectorType()) {
     if (!EvaluateVector(E, Result, Info))
       return false;
+  } else if (T->isSubwordType()) {
+    if (!EvaluateSubword(E, Result, Info))
+      return false;
   } else if (T->isIntegralOrEnumerationType()) {
     if (!IntExprEvaluator(Info, Result).Visit(E))
       return false;
@@ -13469,6 +13709,10 @@ static bool EvaluateInPlace(APValue &Result, EvalInfo &Info, const LValue &This,
     QualType T = E->getType();
     if (T->isArrayType())
       return EvaluateArray(E, This, Result, Info);
+    else if (T->isSubwordType())
+    {
+      return EvaluateSubword(E, Result, Info);
+    }
     else if (T->isRecordType())
       return EvaluateRecord(E, This, Result, Info);
     else if (T->isAtomicType()) {
diff --git a/clang/lib/AST/ItaniumMangle.cpp b/clang/lib/AST/ItaniumMangle.cpp
index 0d567edac521..aa4abfbe388b 100644
--- a/clang/lib/AST/ItaniumMangle.cpp
+++ b/clang/lib/AST/ItaniumMangle.cpp
@@ -1987,6 +1987,7 @@ bool CXXNameMangler::mangleUnresolvedTypeOrSimpleId(QualType Ty,
   case Type::DependentSizedExtVector:
   case Type::Vector:
   case Type::ExtVector:
+  case Type::Subword:
   case Type::FunctionProto:
   case Type::FunctionNoProto:
   case Type::Paren:
@@ -3249,6 +3250,15 @@ void CXXNameMangler::mangleType(const DependentSizedExtVectorType *T) {
   mangleType(T->getElementType());
 }
 
+void CXXNameMangler::mangleType(const SubwordType *T) {
+  Out << "Sw";
+  mangleNumber(T->getBitWidth());
+  Out << '_';
+  mangleNumber(T->getPacking());
+  Out << '_';
+  mangleType(T->getBasicType());
+}
+
 void CXXNameMangler::mangleType(const DependentAddressSpaceType *T) {
   SplitQualType split = T->getPointeeType().split();
   mangleQualifiers(split.Quals, T);
@@ -4020,6 +4030,13 @@ recurse:
       Diags.Report(DiagID);
       return;
     }
+    case UETT_SizeOfSwar: {
+      DiagnosticsEngine &Diags = Context.getDiags();
+      unsigned DiagID = Diags.getCustomDiagID(
+          DiagnosticsEngine::Error,
+          "cannot yet mangle sizeofswar");
+      Diags.Report(DiagID);
+    }
     }
     if (SAE->isArgumentType()) {
       Out << 't';
diff --git a/clang/lib/AST/JSONNodeDumper.cpp b/clang/lib/AST/JSONNodeDumper.cpp
index c30b07137edc..d4429b27a95e 100644
--- a/clang/lib/AST/JSONNodeDumper.cpp
+++ b/clang/lib/AST/JSONNodeDumper.cpp
@@ -1235,6 +1235,7 @@ void JSONNodeDumper::VisitCallExpr(const CallExpr *CE) {
 void JSONNodeDumper::VisitUnaryExprOrTypeTraitExpr(
     const UnaryExprOrTypeTraitExpr *TTE) {
   switch (TTE->getKind()) {
+  case UETT_SizeOfSwar: JOS.attribute("name", "sizeofswar"); break;
   case UETT_SizeOf: JOS.attribute("name", "sizeof"); break;
   case UETT_AlignOf: JOS.attribute("name", "alignof"); break;
   case UETT_VecStep:  JOS.attribute("name", "vec_step"); break;
diff --git a/clang/lib/AST/MicrosoftMangle.cpp b/clang/lib/AST/MicrosoftMangle.cpp
index 6b984955849a..4b827812c721 100644
--- a/clang/lib/AST/MicrosoftMangle.cpp
+++ b/clang/lib/AST/MicrosoftMangle.cpp
@@ -2759,6 +2759,14 @@ void MicrosoftCXXNameMangler::mangleType(const DependentSizedExtVectorType *T,
     << Range;
 }
 
+void MicrosoftCXXNameMangler::mangleType(const SubwordType *T, Qualifiers,
+                                        SourceRange Range) {
+  DiagnosticsEngine &Diags = Context.getDiags();
+  unsigned DiagID = Diags.getCustomDiagID(DiagnosticsEngine::Error,
+                              "cannot mangle this special sub-word type yes");
+  Diags.Report(Range.getBegin(), DiagID) << Range;
+}
+
 void MicrosoftCXXNameMangler::mangleType(const DependentAddressSpaceType *T,
                                          Qualifiers, SourceRange Range) {
   DiagnosticsEngine &Diags = Context.getDiags();
diff --git a/clang/lib/AST/Type.cpp b/clang/lib/AST/Type.cpp
index c5ad711d872e..ee556b7b3dfd 100644
--- a/clang/lib/AST/Type.cpp
+++ b/clang/lib/AST/Type.cpp
@@ -295,6 +295,14 @@ VectorType::VectorType(TypeClass tc, QualType vecType, unsigned nElements,
   VectorTypeBits.NumElements = nElements;
 }
 
+SubwordType::SubwordType(TypeClass tc, QualType canonType, QualType basicType,
+                          unsigned bitWidth, unsigned packing)
+    : Type(tc, canonType, false, false, false, false), BasicType(basicType), BitWidth(bitWidth), Packing(packing) {
+  unsigned maxPack =  32 / BitWidth;
+  assert(Packing<=maxPack && "number of elements in the basic type is too high");
+  if (Packing==0) Packing = maxPack;
+}
+
 /// getArrayElementTypeNoTypeQual - If this is an array type, return the
 /// element type of the array, potentially with type qualifiers missing.
 /// This method should never be used when type qualifiers are meaningful.
@@ -2440,6 +2448,10 @@ bool Type::isLiteralType(const ASTContext &Ctx) const {
   if (isa<AutoType>(BaseTy->getCanonicalTypeInternal()))
     return true;
 
+  if (isSubwordType()) { /* is it safe ? */
+    return true;
+  }
+
   return false;
 }
 
@@ -3689,6 +3701,8 @@ static CachedProperties computeCachedProperties(const Type *T) {
   case Type::Vector:
   case Type::ExtVector:
     return Cache::get(cast<VectorType>(T)->getElementType());
+  case Type::Subword:
+    return Cache::get(cast<SubwordType>(T)->getBasicType());
   case Type::FunctionNoProto:
     return Cache::get(cast<FunctionType>(T)->getReturnType());
   case Type::FunctionProto: {
@@ -3774,6 +3788,8 @@ LinkageInfo LinkageComputer::computeTypeLinkageInfo(const Type *T) {
   case Type::Vector:
   case Type::ExtVector:
     return computeTypeLinkageInfo(cast<VectorType>(T)->getElementType());
+  case Type::Subword:
+    return computeTypeLinkageInfo(cast<SubwordType>(T)->getBasicType());
   case Type::FunctionNoProto:
     return computeTypeLinkageInfo(cast<FunctionType>(T)->getReturnType());
   case Type::FunctionProto: {
@@ -3935,6 +3951,7 @@ bool Type::canHaveNullability(bool ResultIfUnknown) const {
   case Type::DependentSizedExtVector:
   case Type::Vector:
   case Type::ExtVector:
+  case Type::Subword:
   case Type::DependentAddressSpace:
   case Type::FunctionProto:
   case Type::FunctionNoProto:
diff --git a/clang/lib/AST/TypePrinter.cpp b/clang/lib/AST/TypePrinter.cpp
index c2f4baec989e..83c430cc7061 100644
--- a/clang/lib/AST/TypePrinter.cpp
+++ b/clang/lib/AST/TypePrinter.cpp
@@ -254,6 +254,7 @@ bool TypePrinter::canPrefixQualifiers(const Type *T,
     case Type::DependentSizedExtVector:
     case Type::Vector:
     case Type::ExtVector:
+    case Type::Subword:
     case Type::FunctionProto:
     case Type::FunctionNoProto:
     case Type::Paren:
@@ -718,6 +719,19 @@ void TypePrinter::printExtVectorAfter(const ExtVectorType *T, raw_ostream &OS) {
   OS << ")))";
 }
 
+void TypePrinter::printSubwordBefore(const SubwordType *T, raw_ostream &OS) {
+  unsigned pck = T->getPacking();
+  if (pck)
+    OS << "__attribute__((subword " << pck << "x" << T->getBitWidth() << "b) in ";
+  else
+    OS << "__attribute__((subword " << T->getBitWidth() << "b) in ";
+  printBefore(T->getBasicType(), OS);
+  OS <<" )";
+}
+void TypePrinter::printSubwordAfter(const SubwordType *T, raw_ostream &OS) {
+  printAfter(T->getBasicType(), OS);
+}
+
 void
 FunctionProtoType::printExceptionSpecification(raw_ostream &OS,
                                                const PrintingPolicy &Policy)
diff --git a/clang/lib/Basic/Targets/Sparc.cpp b/clang/lib/Basic/Targets/Sparc.cpp
index 13aa964d4716..53ad5f48f996 100644
--- a/clang/lib/Basic/Targets/Sparc.cpp
+++ b/clang/lib/Basic/Targets/Sparc.cpp
@@ -51,9 +51,47 @@ ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const {
   return llvm::makeArrayRef(GCCRegAliases);
 }
 
+const struct SparcTargetInfo::SoftFopsTableStruct SparcTargetInfo::SoftFopsTable[] = {
+    {FPOP_ADD,'a'},{FPOP_SUB,'s'},{FPOP_MUL,'m'},{FPOP_DIV,'d'},
+    {FPOP_MULEX,'M'},{FPOP_SQRT,'S'},{FPOP_CMP,'c'},
+    {FPOP_CI2F,'f'},{FPOP_CF2I,'i'},{FPOP_CFUP,'h'},{FPOP_CFDN,'l'},
+    {FPOP_ABS,'A'},{FPOP_PACK,'p'},{FPOP_MOV,'C'},{FPOP_NEG,'n'},
+    {0,0}
+  };
+
+std::string SparcTargetInfo::getFopsDesc(unsigned mask)
+{
+  std::string out="";
+  int i =0;
+  while (SoftFopsTable[i].mask) {
+    if (mask & SoftFopsTable[i].mask) out.push_back(SoftFopsTable[i].flag);
+    i++;
+  }
+  return out;
+}
+unsigned SparcTargetInfo::getFopsMask(const std::string &desc)
+{
+  unsigned mask = 0;
+  int i =0;
+  while (SoftFopsTable[i].mask) {
+    if (desc.find(SoftFopsTable[i].flag)!=std::string::npos)
+      mask |= SoftFopsTable[i].mask;
+    i++;
+  }
+  return mask;
+}
+
+
 bool SparcTargetInfo::hasFeature(StringRef Feature) const {
   return llvm::StringSwitch<bool>(Feature)
       .Case("softfloat", SoftFloat)
+
+      .Case("softfphalf", SoftFopsHalf)
+      .Case("softfpsingle", SoftFopsSingle)
+      .Case("softfpdouble", SoftFopsDouble)
+      .Case("enablepackedhalf", EnabledPackedHalf)
+      .Case("enablepackedsingle", EnabledPackedSingle)
+
       .Case("sparc", true)
       .Default(false);
 }
@@ -142,6 +180,18 @@ void SparcTargetInfo::getTargetDefines(const LangOptions &Opts,
 
   if (SoftFloat)
     Builder.defineMacro("SOFT_FLOAT", "1");
+
+  Builder.defineMacro("SOFT_FOPS_HALF", Twine(SoftFopsHalf));
+  Builder.defineMacro("SOFT_FOPS_SINGLE", Twine(SoftFopsSingle));
+  Builder.defineMacro("SOFT_FOPS_DOUBLE", Twine(SoftFopsDouble));
+  if (EnabledPackedHalf)
+    Builder.defineMacro("FP_PACKEDHALF_ENABLED", Twine(1));
+  else
+    Builder.defineMacro("FP_PACKEDHALF_ENABLED", Twine(0));
+  if (EnabledPackedSingle)
+    Builder.defineMacro("FP_PACKEDSINGLE_ENABLED", Twine(1));
+  else
+    Builder.defineMacro("FP_PACKEDSINGLE_ENABLED", Twine(0));
 }
 
 void SparcV8TargetInfo::getTargetDefines(const LangOptions &Opts,
diff --git a/clang/lib/Basic/Targets/Sparc.h b/clang/lib/Basic/Targets/Sparc.h
index 1f799565e99b..cb13382cf527 100644
--- a/clang/lib/Basic/Targets/Sparc.h
+++ b/clang/lib/Basic/Targets/Sparc.h
@@ -24,9 +24,45 @@ class LLVM_LIBRARY_VISIBILITY SparcTargetInfo : public TargetInfo {
   static const char *const GCCRegNames[];
   bool SoftFloat;
 
+  bool EnabledSWARdaiteq;
+
+  unsigned daiteqFPUType; // 0=none,1=dpsp,2=sphp,3=dp,4=sp,5=hp,6=php,7=psp
+
+  unsigned SoftFopsHalf;
+  unsigned SoftFopsSingle;
+  unsigned SoftFopsDouble;
+  bool EnabledPackedHalf;
+  bool EnabledPackedSingle;
+
+  enum SoftFopsMasks {
+    FPOP_ADD  = 0x00000001, // 'a'
+    FPOP_SUB  = 0x00000002, // 's'
+    FPOP_MUL  = 0x00000004, // 'm'
+    FPOP_DIV  = 0x00000008, // 'd'
+    FPOP_MULEX= 0x00000010, // 'M' expanding multiply (from the specific precision to higher precision)
+    FPOP_SQRT = 0x00000020, // 'S'
+    FPOP_CMP  = 0x00000040, // 'c'
+    FPOP_CI2F = 0x00000080, // 'f' - convert integer into float
+    FPOP_CF2I = 0x00000100, // 'i' - convert float into integer
+    FPOP_CFUP = 0x00000200, // 'h' - convert float into float with higher precision (H->S,S->D,D->Q)
+    FPOP_CFDN = 0x00000400, // 'l' - convert float into float with lower precision (D->S,S->H)
+    FPOP_ABS  = 0x00000800, // 'A'
+    FPOP_PACK = 0x00001000, // 'p'
+    FPOP_MOV  = 0x00002000, // 'C'
+    FPOP_NEG  = 0x00004000, // 'n'
+
+    FPOP_FULL_MASK = 0x00006FFF, // all known and used masks
+  };
+
+  static const struct SoftFopsTableStruct {
+    unsigned mask;
+    char     flag;
+  } SoftFopsTable[];
+
 public:
   SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
-      : TargetInfo(Triple), SoftFloat(false) {}
+      : TargetInfo(Triple), SoftFloat(false), EnabledSWARdaiteq(false), daiteqFPUType(0),
+        SoftFopsHalf(0), SoftFopsSingle(0), SoftFopsDouble(0), EnabledPackedHalf(false), EnabledPackedSingle(false)  {}
 
   int getEHDataRegisterNumber(unsigned RegNo) const override {
     if (RegNo == 0)
@@ -36,13 +72,80 @@ public:
     return -1;
   }
 
+  static std::string getFopsDesc(unsigned mask);
+  static unsigned getFopsMask(const std::string &desc);
+
   bool handleTargetFeatures(std::vector<std::string> &Features,
                             DiagnosticsEngine &Diags) override {
     // Check if software floating point is enabled
     auto Feature = llvm::find(Features, "+soft-float");
     if (Feature != Features.end()) {
       SoftFloat = true;
+      daiteqFPUType = 0;
+      SoftFopsHalf = -1;
+      SoftFopsSingle = -1;
+      SoftFopsDouble = -1;
+      EnabledPackedHalf = false;
+      EnabledPackedSingle = false;
     }
+    // Check if specific FP operations are enabled
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-half-fadd") != Features.end()) SoftFopsHalf |= FPOP_ADD;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-half-fsub") != Features.end()) SoftFopsHalf |= FPOP_SUB;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-half-fmul") != Features.end()) SoftFopsHalf |= FPOP_MUL;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-half-fdiv") != Features.end()) SoftFopsHalf |= FPOP_DIV;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-half-fmulex") != Features.end()) SoftFopsHalf |= FPOP_MULEX;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-half-fsqrt") != Features.end()) SoftFopsHalf |= FPOP_SQRT;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-half-fcmp") != Features.end()) SoftFopsHalf |= FPOP_CMP;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-half-fci2f") != Features.end()) SoftFopsHalf |= FPOP_CI2F;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-half-fcf2i") != Features.end()) SoftFopsHalf |= FPOP_CF2I;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-half-fcfup") != Features.end()) SoftFopsHalf |= FPOP_CFUP;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-half-fcfdn") != Features.end()) SoftFopsHalf |= FPOP_CFDN;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-half-fabs") != Features.end()) SoftFopsHalf |= FPOP_ABS;
+//    if (std::find(Features.begin(), Features.end(), "+soft-fops-half-fpack") != Features.end()) SoftFopsHalf |= FPOP_PACK;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-half-fmov") != Features.end()) SoftFopsHalf |= FPOP_MOV;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-half-fneg") != Features.end()) SoftFopsHalf |= FPOP_NEG;
+
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-single-fadd") != Features.end()) SoftFopsSingle |= FPOP_ADD;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-single-fsub") != Features.end()) SoftFopsSingle |= FPOP_SUB;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-single-fmul") != Features.end()) SoftFopsSingle |= FPOP_MUL;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-single-fdiv") != Features.end()) SoftFopsSingle |= FPOP_DIV;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-single-fmulex") != Features.end()) SoftFopsSingle |= FPOP_MULEX;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-single-fsqrt") != Features.end()) SoftFopsSingle |= FPOP_SQRT;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-single-fcmp") != Features.end()) SoftFopsSingle |= FPOP_CMP;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-single-fci2f") != Features.end()) SoftFopsSingle |= FPOP_CI2F;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-single-fcf2i") != Features.end()) SoftFopsSingle |= FPOP_CF2I;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-single-fcfup") != Features.end()) SoftFopsSingle |= FPOP_CFUP;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-single-fcfdn") != Features.end()) SoftFopsSingle |= FPOP_CFDN;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-single-fabs") != Features.end()) SoftFopsSingle |= FPOP_ABS;
+//    if (std::find(Features.begin(), Features.end(), "+soft-fops-single-fpack") != Features.end()) SoftFopsSingle |= FPOP_PACK;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-single-fmov") != Features.end()) SoftFopsSingle |= FPOP_MOV;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-single-fneg") != Features.end()) SoftFopsSingle |= FPOP_NEG;
+
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-double-fadd") != Features.end()) SoftFopsDouble |= FPOP_ADD;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-double-fsub") != Features.end()) SoftFopsDouble |= FPOP_SUB;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-double-fmul") != Features.end()) SoftFopsDouble |= FPOP_MUL;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-double-fdiv") != Features.end()) SoftFopsDouble |= FPOP_DIV;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-double-fmulex") != Features.end()) SoftFopsDouble |= FPOP_MULEX;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-double-fsqrt") != Features.end()) SoftFopsDouble |= FPOP_SQRT;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-double-fcmp") != Features.end()) SoftFopsDouble |= FPOP_CMP;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-double-fci2f") != Features.end()) SoftFopsDouble |= FPOP_CI2F;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-double-fcf2i") != Features.end()) SoftFopsDouble |= FPOP_CF2I;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-double-fcfup") != Features.end()) SoftFopsDouble |= FPOP_CFUP;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-double-fcfdn") != Features.end()) SoftFopsDouble |= FPOP_CFDN;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-double-fabs") != Features.end()) SoftFopsDouble |= FPOP_ABS;
+//    if (std::find(Features.begin(), Features.end(), "+soft-fops-double-fpack") != Features.end()) SoftFopsDouble |= FPOP_PACK;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-double-fmov") != Features.end()) SoftFopsDouble |= FPOP_MOV;
+    if (std::find(Features.begin(), Features.end(), "+soft-fops-double-fneg") != Features.end()) SoftFopsDouble |= FPOP_NEG;
+
+    Feature = std::find(Features.begin(), Features.end(), "+enable-packedhalf");
+    if (Feature != Features.end()) EnabledPackedHalf = true;
+    Feature = std::find(Features.begin(), Features.end(), "+enable-packedsingle");
+    if (Feature != Features.end()) EnabledPackedSingle = true;
+
+    // check if daiteq FPU/SWAR extensions are enabled
+    Feature = std::find(Features.begin(), Features.end(), "+daiteq-swar");
+    if (Feature != Features.end()) EnabledSWARdaiteq = true;
+
     return true;
   }
   void getTargetDefines(const LangOptions &Opts,
@@ -151,7 +254,10 @@ class LLVM_LIBRARY_VISIBILITY SparcV8TargetInfo : public SparcTargetInfo {
 public:
   SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
       : SparcTargetInfo(Triple, Opts) {
-    resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64");
+    if (Triple.getVendor()==llvm::Triple::Daiteq)
+      resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64-f16:16");
+    else
+      resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64");
     // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int.
     switch (getTriple().getOS()) {
     default:
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 12517709573a..927afecc602d 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -1677,9 +1677,11 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID,
                                    Intrinsic::exp2,
                                    Intrinsic::experimental_constrained_exp2));
 
+    case Builtin::BIfabsh:
     case Builtin::BIfabs:
     case Builtin::BIfabsf:
     case Builtin::BIfabsl:
+    case Builtin::BI__builtin_fabsh:
     case Builtin::BI__builtin_fabs:
     case Builtin::BI__builtin_fabsf:
     case Builtin::BI__builtin_fabsf16:
@@ -1832,9 +1834,11 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID,
                                    Intrinsic::sin,
                                    Intrinsic::experimental_constrained_sin));
 
+    case Builtin::BIsqrth:
     case Builtin::BIsqrt:
     case Builtin::BIsqrtf:
     case Builtin::BIsqrtl:
+    case Builtin::BI__builtin_sqrth:
     case Builtin::BI__builtin_sqrt:
     case Builtin::BI__builtin_sqrtf:
     case Builtin::BI__builtin_sqrtf16:
@@ -1843,6 +1847,10 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID,
                                    Intrinsic::sqrt,
                                    Intrinsic::experimental_constrained_sqrt));
 
+    case Builtin::BI__builtin_sqrtpf:
+    case Builtin::BIsqrtpf:
+      return RValue::get(emitUnaryBuiltin(*this, E, Intrinsic::sqrt));
+
     case Builtin::BItrunc:
     case Builtin::BItruncf:
     case Builtin::BItruncl:
@@ -4214,6 +4222,61 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID,
     Value *ArgPtr = Builder.CreateLoad(SrcAddr, "ap.val");
     return RValue::get(Builder.CreateStore(ArgPtr, DestAddr));
   }
+
+/* support for inserting an instruction for setting the swar control word */
+  case Builtin::BI__builtin_swarctrl: {
+    if (E->getArg(0)->isIntegerConstantExpr(getContext(), nullptr)) {
+      unsigned cfg = E->getArg(0)->EvaluateKnownConstInt(getContext()).getZExtValue();
+      llvm::InlineAsm *Emit;
+      if (cfg<0x2000) { /* can be an immediate value */
+        llvm::FunctionType *FTy = llvm::FunctionType::get(VoidTy, false);
+        Emit = InlineAsm::get(FTy, "wr %g0, 0x" + utohexstr(cfg) + ", %asr22    ! swarctrl(0x" + utohexstr(cfg) + ")", "", true);
+        return RValue::get(Builder.CreateCall(Emit));
+      } else {
+        llvm::FunctionType *FTySet = llvm::FunctionType::get(Int32Ty, false);
+        llvm::FunctionType *FTyGet = llvm::FunctionType::get(VoidTy, {Int32Ty}, false);
+
+        llvm::InlineAsm *EmitSet = InlineAsm::get(FTySet, "set 0x" + utohexstr(cfg) + ",$0", "=r", true);
+        Value *TmpVal = Builder.CreateCall(EmitSet);
+
+        llvm::InlineAsm *EmitGet = InlineAsm::get(FTyGet, "wr $0, 0, %asr22  ! swarctrl = 0x" + utohexstr(cfg), "r", true);
+        return RValue::get(Builder.CreateCall(EmitGet, {TmpVal}));
+      }
+    } else {
+      llvm::FunctionType *FTy = llvm::FunctionType::get(VoidTy, {Int32Ty}, false);
+      llvm::Value *R = EmitScalarExpr(E->getArg(0));
+      llvm::InlineAsm *Emit = InlineAsm::get(FTy, "wr $0, %asr22  ! swarctrl(var)", "r", true);
+      return RValue::get(Builder.CreateCall(Emit, {R}));
+    }
+  }
+  case Builtin::BI__builtin_swaraccum: {
+    if (E->getArg(0)->isIntegerConstantExpr(getContext(), nullptr)) {
+      llvm::FunctionType *FTy = llvm::FunctionType::get(Int32Ty, false);
+      unsigned cfg = E->getArg(0)->EvaluateKnownConstInt(getContext()).getZExtValue();
+      llvm::InlineAsm *Emit = InlineAsm::get(FTy, "wr %g0, 0x" + utohexstr(cfg) + ", %asr23; nop; rd %asr23, $0", "=r", true);
+      return RValue::get(Builder.CreateCall(Emit));
+    } else {
+      llvm::FunctionType *FTy = llvm::FunctionType::get(Int32Ty, {Int32Ty}, false);
+      llvm::Value *R = EmitScalarExpr(E->getArg(0));
+      llvm::InlineAsm *Emit = InlineAsm::get(FTy, "wr $1, %asr23; nop; rd %asr23, $0", "=r,r", true);
+      return RValue::get(Builder.CreateCall(Emit, {R}));
+    }
+  }
+  case Builtin::BI__builtin_swar: {
+    llvm::FunctionType *FTy = llvm::FunctionType::get(Int32Ty, {Int32Ty, Int32Ty}, false); // uint32 = f(uint32, uint32)
+    llvm::Value *X = EmitScalarExpr(E->getArg(0));
+    llvm::Value *Y = EmitScalarExpr(E->getArg(1));
+    llvm::InlineAsm *Emit = InlineAsm::get(FTy, "swar $1,$2,$0", "=r,r,r", true); /* hasSideEffect =false */
+    return RValue::get(Builder.CreateCall(Emit,{X,Y}));
+  }
+  case Builtin::BI__builtin_swarcc: {
+    llvm::FunctionType *FTy = llvm::FunctionType::get(Int32Ty, {Int32Ty, Int32Ty}, false); // uint32 = f(uint32, uint32)
+    llvm::Value *X = EmitScalarExpr(E->getArg(0));
+    llvm::Value *Y = EmitScalarExpr(E->getArg(1));
+    llvm::InlineAsm *Emit = InlineAsm::get(FTy, "swarcc $1,$2,$0", "=r,r,r", true); /* hasSideEffect =false */
+    return RValue::get(Builder.CreateCall(Emit,{X,Y}));
+  }
+
   }
 
   // If this is an alias for a lib function (e.g. __builtin_sin), emit
diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp
index b49b194d6112..4ac0448f6e24 100644
--- a/clang/lib/CodeGen/CGCall.cpp
+++ b/clang/lib/CodeGen/CGCall.cpp
@@ -1769,6 +1769,23 @@ void CodeGenModule::ConstructDefaultFnAttrList(StringRef Name, bool HasOptnone,
                            llvm::toStringRef(CodeGenOpts.UnsafeFPMath));
     FuncAttrs.addAttribute("use-soft-float",
                            llvm::toStringRef(CodeGenOpts.SoftFloat));
+
+    FuncAttrs.addAttribute("daiteq-fpu-type",
+                           llvm::utostr(CodeGenOpts.daiteqFPUType));
+    FuncAttrs.addAttribute("use-daiteq-swar",
+                           llvm::toStringRef(CodeGenOpts.EnabledSWARdaiteq));
+
+    FuncAttrs.addAttribute("soft-fops-half",
+                           llvm::utostr(CodeGenOpts.SoftFopsHalf));
+    FuncAttrs.addAttribute("soft-fops-single",
+                           llvm::utostr(CodeGenOpts.SoftFopsSingle));
+    FuncAttrs.addAttribute("soft-fops-double",
+                           llvm::utostr(CodeGenOpts.SoftFopsDouble));
+    FuncAttrs.addAttribute("enable-packedhalf",
+                           llvm::toStringRef(CodeGenOpts.EnabledPackedHalf));
+    FuncAttrs.addAttribute("enable-packedsingle",
+                           llvm::toStringRef(CodeGenOpts.EnabledPackedSingle));
+
     FuncAttrs.addAttribute("stack-protector-buffer-size",
                            llvm::utostr(CodeGenOpts.SSPBufferSize));
     FuncAttrs.addAttribute("no-signed-zeros-fp-math",
diff --git a/clang/lib/CodeGen/CGDebugInfo.cpp b/clang/lib/CodeGen/CGDebugInfo.cpp
index 675df309e3f0..9ffd90333412 100644
--- a/clang/lib/CodeGen/CGDebugInfo.cpp
+++ b/clang/lib/CodeGen/CGDebugInfo.cpp
@@ -2767,6 +2767,26 @@ llvm::DIType *CGDebugInfo::CreateType(const PipeType *Ty, llvm::DIFile *U) {
   return getOrCreateType(Ty->getElementType(), U);
 }
 
+llvm::DIType *CGDebugInfo::CreateType(const SubwordType *Ty, llvm::DIFile *Unit) {
+  llvm::DIType *BasicTy = getOrCreateType(Ty->getBasicType(), Unit);
+  int64_t ECount = Ty->getPacking();
+  int64_t ESize = Ty->getBitWidth();
+
+  llvm::Metadata *Subscript;
+  QualType QTy(Ty, 0);
+  auto SizeExpr = SizeExprCache.find(QTy);
+  if (SizeExpr != SizeExprCache.end())
+    Subscript = DBuilder.getOrCreateSubrange(0, SizeExpr->getSecond());
+  else
+    Subscript = DBuilder.getOrCreateSubrange(0, ECount);
+  llvm::DINodeArray SubscriptArray = DBuilder.getOrCreateArray(Subscript);
+
+  uint64_t Size = CGM.getContext().getTypeSize(Ty);
+  auto Align = getTypeAlignIfRequired(Ty, CGM.getContext());
+
+  return DBuilder.createSubwordType(ESize, ECount, BasicTy, SubscriptArray);
+}
+
 llvm::DIType *CGDebugInfo::CreateEnumType(const EnumType *Ty) {
   const EnumDecl *ED = Ty->getDecl();
 
@@ -3082,6 +3102,9 @@ llvm::DIType *CGDebugInfo::CreateTypeNode(QualType Ty, llvm::DIFile *Unit) {
   case Type::TemplateSpecialization:
     return CreateType(cast<TemplateSpecializationType>(Ty), Unit);
 
+  case Type::Subword:
+    return CreateType(cast<SubwordType>(Ty), Unit);
+
   case Type::Auto:
   case Type::Attributed:
   case Type::Adjusted:
diff --git a/clang/lib/CodeGen/CGDebugInfo.h b/clang/lib/CodeGen/CGDebugInfo.h
index 90e9a61ebe96..8c75eb48e37a 100644
--- a/clang/lib/CodeGen/CGDebugInfo.h
+++ b/clang/lib/CodeGen/CGDebugInfo.h
@@ -194,6 +194,9 @@ class CGDebugInfo {
   llvm::DIType *CreateType(const MemberPointerType *Ty, llvm::DIFile *F);
   llvm::DIType *CreateType(const AtomicType *Ty, llvm::DIFile *F);
   llvm::DIType *CreateType(const PipeType *Ty, llvm::DIFile *F);
+
+  llvm::DIType *CreateType(const SubwordType *Ty, llvm::DIFile *F);
+
   /// Get enumeration type.
   llvm::DIType *CreateEnumType(const EnumType *Ty);
   llvm::DIType *CreateTypeDefinition(const EnumType *Ty);
diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp
index e43ed5030bc2..a98a3214878b 100644
--- a/clang/lib/CodeGen/CGExpr.cpp
+++ b/clang/lib/CodeGen/CGExpr.cpp
@@ -3560,6 +3560,14 @@ LValue CodeGenFunction::EmitArraySubscriptExpr(const ArraySubscriptExpr *E,
                           CGM.getTBAAInfoForSubobject(LV, EltType));
   }
 
+  if (E->getBase()->getType()->isSubwordType()) {
+    LValue LHS = EmitLValue(E->getBase());
+    auto *Idx = EmitIdxAfterBase(false); /* ??? Promote */
+    assert(LHS.isSimple() && "Can only subscript lvalue subword here!");
+    return LValue::MakeSubwordElt(LHS.getAddress(*this), Idx, E->getBase()->getType(),
+                                 LHS.getBaseInfo(), TBAAAccessInfo());
+  }
+
   LValueBaseInfo EltBaseInfo;
   TBAAAccessInfo EltTBAAInfo;
   Address Addr = Address::invalid();
diff --git a/clang/lib/CodeGen/CGExprScalar.cpp b/clang/lib/CodeGen/CGExprScalar.cpp
index d759d3682cef..64f1f25984cc 100644
--- a/clang/lib/CodeGen/CGExprScalar.cpp
+++ b/clang/lib/CodeGen/CGExprScalar.cpp
@@ -2804,6 +2804,28 @@ ScalarExprEmitter::VisitUnaryExprOrTypeTraitExpr(
 
       return size;
     }
+  } else if (E->getKind() == UETT_SizeOfSwar) { /* TODO: change to sizeofswar */
+    if (const VariableArrayType *VAT =
+          CGF.getContext().getAsVariableArrayType(TypeToSize)) {
+      if (E->isArgumentType()) {
+        // sizeof(type) - make sure to emit the VLA size.
+        CGF.EmitVariablyModifiedType(TypeToSize);
+      } else {
+        // C99 6.5.3.4p2: If the argument is an expression of type
+        // VLA, it is evaluated.
+        CGF.EmitIgnoredExpr(E->getArgumentExpr());
+      }
+
+      auto VlaSize = CGF.getVLASize(VAT);
+      llvm::Value *size = VlaSize.NumElts;
+
+      // Scale the number of non-VLA elements by the non-VLA element size.
+      CharUnits eltSize = CGF.getContext().getTypeSizeInChars(VlaSize.Type);
+      if (!eltSize.isOne())
+        size = CGF.Builder.CreateNUWMul(CGF.CGM.getSize(eltSize), size);
+
+      return size;
+    }
   } else if (E->getKind() == UETT_OpenMPRequiredSimdAlign) {
     auto Alignment =
         CGF.getContext()
diff --git a/clang/lib/CodeGen/CGValue.h b/clang/lib/CodeGen/CGValue.h
index 9fd07bdb187d..2d1164c6d8a1 100644
--- a/clang/lib/CodeGen/CGValue.h
+++ b/clang/lib/CodeGen/CGValue.h
@@ -403,6 +403,18 @@ public:
     return R;
   }
 
+  static LValue MakeSubwordElt(Address swAddress, llvm::Value *Idx,
+                                QualType type, LValueBaseInfo BaseInfo,
+                                TBAAAccessInfo TBAAInfo) {
+    LValue R;
+    R.LVType = VectorElt;
+    R.V = swAddress.getPointer();
+    R.VectorIdx = Idx;
+    R.Initialize(type, type.getQualifiers(), swAddress.getAlignment(),
+                  BaseInfo, TBAAInfo);
+    return R;
+  }
+
   /// Create a new object to represent a bit-field access.
   ///
   /// \param Addr - The base address of the bit-field sequence this
diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp b/clang/lib/CodeGen/CodeGenFunction.cpp
index 448b70de9714..38c011405d04 100644
--- a/clang/lib/CodeGen/CodeGenFunction.cpp
+++ b/clang/lib/CodeGen/CodeGenFunction.cpp
@@ -264,6 +264,7 @@ TypeEvaluationKind CodeGenFunction::getEvaluationKind(QualType type) {
     case Type::Enum:
     case Type::ObjCObjectPointer:
     case Type::Pipe:
+    case Type::Subword:
       return TEK_Scalar;
 
     // Complexes.
@@ -1979,6 +1980,9 @@ void CodeGenFunction::EmitVariablyModifiedType(QualType type) {
     case Type::ObjCObjectPointer:
       llvm_unreachable("type class is never variably-modified!");
 
+    case Type::Subword:
+      llvm_unreachable("CodeGenFunction::EmitVariablyModifiedType - Subword type class is never variably-modified!");
+
     case Type::Adjusted:
       type = cast<AdjustedType>(ty)->getAdjustedType();
       break;
diff --git a/clang/lib/CodeGen/CodeGenTypes.cpp b/clang/lib/CodeGen/CodeGenTypes.cpp
index a458811d7a30..cbde3e391d43 100644
--- a/clang/lib/CodeGen/CodeGenTypes.cpp
+++ b/clang/lib/CodeGen/CodeGenTypes.cpp
@@ -609,6 +609,23 @@ llvm::Type *CodeGenTypes::ConvertType(QualType T) {
                                        VT->getNumElements());
     break;
   }
+
+  // convert clang Subword type to llvm::VectorType (with enabled subword flag)
+  case Type::Subword: {
+    const SubwordType *SWT = cast<SubwordType>(Ty);
+    if (!SWT->getBasicType()->isIntegerType()) {
+      llvm_unreachable("Unsupported basic type of subword type!");
+    }
+    unsigned pck = SWT->getPacking();
+    bool sign = SWT->getBasicType()->isSignedIntegerType();
+    /* TODO: bt is currently always a 32bit type -> TODO: should be according to BasicType */
+    llvm::Type *bt = llvm::IntegerType::get(getLLVMContext(), 32);
+    llvm::Type *et = llvm::IntegerType::get(getLLVMContext(),
+                      static_cast<unsigned>(SWT->getBitWidth()));
+    ResultType = llvm::VectorType::get(bt, et, pck, sign);
+    break;
+  }
+
   case Type::FunctionNoProto:
   case Type::FunctionProto:
     ResultType = ConvertFunctionTypeInternal(T);
diff --git a/clang/lib/CodeGen/ItaniumCXXABI.cpp b/clang/lib/CodeGen/ItaniumCXXABI.cpp
index 6ed172bb107e..34359274a029 100644
--- a/clang/lib/CodeGen/ItaniumCXXABI.cpp
+++ b/clang/lib/CodeGen/ItaniumCXXABI.cpp
@@ -3208,6 +3208,9 @@ void ItaniumRTTIBuilder::BuildVTablePointer(const Type *Ty) {
     VTableName = "_ZTVN10__cxxabiv123__fundamental_type_infoE";
     break;
 
+  case Type::Subword:
+    llvm_unreachable("Subword type is not supported in the ItaniumCXXABI");
+
   case Type::ConstantArray:
   case Type::IncompleteArray:
   case Type::VariableArray:
@@ -3459,6 +3462,9 @@ llvm::Constant *ItaniumRTTIBuilder::BuildTypeInfo(
     // abi::__array_type_info adds no data members to std::type_info.
     break;
 
+  case Type::Subword:
+    llvm_unreachable("Subword type shouldn't get here (ItaniumCXXABI)");
+
   case Type::FunctionNoProto:
   case Type::FunctionProto:
     // Itanium C++ ABI 2.9.5p5:
diff --git a/clang/lib/Driver/ToolChains/Arch/Sparc.cpp b/clang/lib/Driver/ToolChains/Arch/Sparc.cpp
index 043b7f257c01..76a18bbcd968 100644
--- a/clang/lib/Driver/ToolChains/Arch/Sparc.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/Sparc.cpp
@@ -7,6 +7,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "Sparc.h"
+#include "ToolChains/CommonArgs.h"
 #include "clang/Driver/Driver.h"
 #include "clang/Driver/DriverDiagnostic.h"
 #include "clang/Driver/Options.h"
@@ -106,9 +107,370 @@ sparc::FloatABI sparc::getSparcFloatABI(const Driver &D,
   return ABI;
 }
 
+/* the same table as in SparcTargetInfo ... shouldn't they be only in one place ? */
+enum SoftFopsMasks {
+  FPOP_ADD  = 0x00000001, // 'a'
+  FPOP_SUB  = 0x00000002, // 's'
+  FPOP_MUL  = 0x00000004, // 'm'
+  FPOP_DIV  = 0x00000008, // 'd'
+  FPOP_MULEX= 0x00000010, // 'M' expanding multiply (from the specific precision to higher precision)
+  FPOP_SQRT = 0x00000020, // 'S'
+  FPOP_CMP  = 0x00000040, // 'c'
+  FPOP_CI2F = 0x00000080, // 'f' - convert integer into float
+  FPOP_CF2I = 0x00000100, // 'i' - convert float into integer
+  FPOP_CFUP = 0x00000200, // 'h' - convert float into float with higher precision (H->S,S->D,D->Q)
+  FPOP_CFDN = 0x00000400, // 'l' - convert float into float with lower precision (D->S,S->H)
+  FPOP_ABS  = 0x00000800, // 'A'
+  FPOP_PACK = 0x00001000, // 'p'
+  FPOP_MOV  = 0x00002000, // 'C'
+  FPOP_NEG  = 0x00004000, // 'n'
+
+  FPOP_FULL_MASK = 0x00006FFF, // all known and used masks
+};
+
+struct SoftFopsTableStruct {
+  unsigned mask;
+  char     flag;
+};
+
+static const struct SoftFopsTableStruct SoftFopsTable[] = {
+  {FPOP_ADD,'a'},{FPOP_SUB,'s'},{FPOP_MUL,'m'},{FPOP_DIV,'d'},
+  {FPOP_MULEX,'M'},{FPOP_SQRT,'S'},{FPOP_CMP,'c'},
+  {FPOP_CI2F,'f'},{FPOP_CF2I,'i'},{FPOP_CFUP,'h'},{FPOP_CFDN,'l'},
+  {FPOP_ABS,'A'},{FPOP_PACK,'p'},{FPOP_MOV,'C'},{FPOP_NEG,'n'},
+  {0,0}
+};
+static unsigned getFopsMask(const std::string &desc)
+{
+  unsigned mask = 0;
+  int i =0;
+  while (SoftFopsTable[i].mask) {
+    if (desc.find(SoftFopsTable[i].flag)!=std::string::npos)
+      mask |= SoftFopsTable[i].mask;
+    i++;
+  }
+  return mask;
+}
+
+
 void sparc::getSparcTargetFeatures(const Driver &D, const ArgList &Args,
                                    std::vector<StringRef> &Features) {
+  handleTargetFeaturesGroup(Args, Features, options::OPT_m_sparc_Features_Group);
+
   sparc::FloatABI FloatABI = sparc::getSparcFloatABI(D, Args);
-  if (FloatABI == sparc::FloatABI::Soft)
+
+  unsigned sfhalf=0, sfsingle=0, sfdouble=0;
+  bool enphalf = false, enpsingle = false;
+  bool noalignfp = false;
+  for (const auto &A : Args) {
+    //A->dump();
+    unsigned val;
+    unsigned argid = A->getOption().getID();
+    switch (argid) {
+      case options::OPT_munaligned_packed_fp:
+        noalignfp = true;
+        break;
+      case options::OPT_msoft_float:
+        sfhalf = -1;
+        sfsingle = -1;
+        sfdouble = -1;
+        enphalf = false;
+        enpsingle = false;
+        break;
+/* half FP */
+      case options::OPT_mhard_fp_half:
+        sfhalf = 0; // all half FP ops disabled
+        break;
+      case options::OPT_msoft_fp_half:
+        sfhalf = -1; // all half FP ops enabled
+        break;
+      case options::OPT_msoft_fops_half:
+        val = getFopsMask(A->getValue());
+        sfhalf |= val;
+        break;
+      case options::OPT_mhard_fops_half:
+        val = getFopsMask(A->getValue());
+        sfhalf &= ~val;
+        break;
+/* single FP */
+      case options::OPT_mhard_fp_single:
+        sfsingle = 0; // all float FP ops disabled
+        break;
+      case options::OPT_msoft_fp_single:
+        sfsingle = -1; // all float FP ops enabled
+        break;
+      case options::OPT_msoft_fops_single:
+        val = getFopsMask(A->getValue()); // -msoft-fops-single=
+        sfsingle |= val;
+        break;
+      case options::OPT_mhard_fops_single:
+        val = getFopsMask(A->getValue()); // -mhard-fops-single=
+        sfsingle &= ~val;
+        break;
+/* double FP */
+      case options::OPT_mhard_fp_double:
+        sfdouble = 0; // all float FP ops disabled
+        break;
+      case options::OPT_msoft_fp_double:
+        sfdouble = -1; // all float FP ops enabled
+        break;
+      case options::OPT_msoft_fops_double:
+        val = getFopsMask(A->getValue()); // -msoft-fops-double=
+        sfdouble |= val;
+        break;
+      case options::OPT_mhard_fops_double:
+        val = getFopsMask(A->getValue()); // -mhard-fops-double=
+        sfdouble &= ~val;
+        break;
+/* packed half FP */
+      case options::OPT_menable_packedhalf:
+        enphalf = true;
+        break;
+/* packed single FP */
+      case options::OPT_menable_packedsingle:
+        enpsingle = true;
+        break;
+      case options::OPT_daiteq_fpu_type:
+        { // the same selection is in clang/lib/Frontend/CompilerInvocation.cpp
+          StringRef fpu = A->getValue();
+          if (fpu == "daifpu_divsqrt") {
+            FloatABI = sparc::FloatABI::Hard;
+            sfdouble = 0; // DP all in HW
+            sfsingle = 0; // SP all in HW
+            sfhalf = -1; // HP all in softfloat
+            enphalf = false;
+            enpsingle = false;
+          } else if (fpu == "daifpu_divonly") { // DP,SP - SQRT in softfloat
+            FloatABI = sparc::FloatABI::Hard;
+            sfdouble = FPOP_SQRT; // DP all in HW, except sqrt
+            sfsingle = FPOP_SQRT; // SP all in HW, except sqrt
+            sfhalf = -1; // HP all in softfloat
+            enphalf = false;
+            enpsingle = false;
+          } else if (fpu == "daifpu_none") {
+            FloatABI = sparc::FloatABI::Hard;
+            sfdouble = FPOP_DIV | FPOP_SQRT; // DP all in HW, except div/sqrt
+            sfsingle = FPOP_DIV | FPOP_SQRT; // SP all in HW, except div/sqrt
+            sfhalf = -1; // HP all in softfloat
+            enphalf = false;
+            enpsingle = false;
+          } else if (fpu == "daifpu_dual_dpsp_divsqrt") {
+            FloatABI = sparc::FloatABI::Hard;
+            sfdouble = 0; // DP all in HW
+            sfsingle = 0; // SP all in HW
+            sfhalf = -1; // HP all in softfloat
+            enphalf = false;
+            enpsingle = false;
+          } else if (fpu == "daifpu_dual_dpsp_divonly") {
+            FloatABI = sparc::FloatABI::Hard;
+            sfdouble = FPOP_SQRT; // DP all in HW, except sqrt
+            sfsingle = FPOP_SQRT; // SP all in HW, except sqrt
+            sfhalf = -1; // HP all in softfloat
+            enphalf = false;
+            enpsingle = false;
+          } else if (fpu == "daifpu_dual_dpsp_none") {
+            FloatABI = sparc::FloatABI::Hard;
+            sfdouble = FPOP_DIV | FPOP_SQRT; // DP all in HW, except div/sqrt
+            sfsingle = FPOP_DIV | FPOP_SQRT; // SP all in HW, except div/sqrt
+            sfhalf = -1; // HP all in softfloat
+            enphalf = false;
+            enpsingle = false;
+          } else if (fpu == "daifpu_dual_sphp_divsqrt") {
+            FloatABI = sparc::FloatABI::Hard;
+            sfdouble = -1; // DP all in softfloat
+            sfsingle = 0;  // SP all in HW
+            sfhalf = 0;    // HP all in HW
+            enphalf = false;
+            enpsingle = false;
+          } else if (fpu == "daifpu_dual_sphp_divonly") {
+            FloatABI = sparc::FloatABI::Hard;
+            sfdouble = -1; // DP all in softfloat
+            sfsingle = FPOP_SQRT;  // SP all in HW, except sqrt
+            sfhalf = FPOP_SQRT;    // HP all in HW, except sqrt
+            enphalf = false;
+            enpsingle = false;
+          } else if (fpu == "daifpu_dual_sphp_none") {
+            FloatABI = sparc::FloatABI::Hard;
+            sfdouble = -1; // DP all in softfloat
+            sfsingle = FPOP_DIV | FPOP_SQRT;  // SP all in HW, except div/sqrt
+            sfhalf = FPOP_DIV | FPOP_SQRT;    // HP all in HW, except div/sqrt
+            enphalf = false;
+            enpsingle = false;
+          } else if (fpu == "daifpu_dp_divsqrt") {
+            FloatABI = sparc::FloatABI::Hard;
+            sfdouble = 0; // DP all in HW
+            sfsingle = -1; // SP all in softfloat
+            sfhalf = -1; // HP all in softfloat
+            enphalf = false;
+            enpsingle = false;
+          } else if (fpu == "daifpu_dp_divonly") {
+            FloatABI = sparc::FloatABI::Hard;
+            sfdouble = FPOP_SQRT;  // DP all in HW, except sqrt
+            sfsingle = -1; // SP all in softfloat
+            sfhalf = -1; // HP all in softfloat
+            enphalf = false;
+            enpsingle = false;
+          } else if (fpu == "daifpu_dp_none") {
+            FloatABI = sparc::FloatABI::Hard;
+            sfdouble = FPOP_DIV | FPOP_SQRT;  // DP all in HW, except div/sqrt
+            sfsingle = -1; // SP all in softfloat
+            sfhalf = -1; // HP all in softfloat
+            enphalf = false;
+            enpsingle = false;
+          } else if (fpu == "daifpu_sp_divsqrt") {
+            FloatABI = sparc::FloatABI::Hard;
+            sfdouble = -1; // DP all in softfloat
+            sfsingle = 0;  // SP all in HW
+            sfhalf = -1;    // HP all in softfloat
+            enphalf = false;
+            enpsingle = false;
+          } else if (fpu == "daifpu_sp_divonly") {
+            FloatABI = sparc::FloatABI::Hard;
+            sfdouble = -1; // DP all in softfloat
+            sfsingle = FPOP_SQRT;  // SP all in HW, except sqrt
+            sfhalf = -1;    // HP all in softfloat
+            enphalf = false;
+            enpsingle = false;
+          } else if (fpu == "daifpu_sp_none") {
+            FloatABI = sparc::FloatABI::Hard;
+            sfdouble = -1; // DP all in softfloat
+            sfsingle = FPOP_DIV | FPOP_SQRT;  // SP all in HW, except div/sqrt
+            sfhalf = -1;    // HP all in softfloat
+            enphalf = false;
+            enpsingle = false;
+          } else if (fpu == "daifpu_hp_divsqrt") {
+            FloatABI = sparc::FloatABI::Hard;
+            sfdouble = -1; // DP all in softfloat
+            sfsingle = -1;  // SP all in softfloat
+            sfhalf = 0;    // HP all in HW
+            enphalf = false;
+            enpsingle = false;
+          } else if (fpu == "daifpu_hp_divonly") {
+            FloatABI = sparc::FloatABI::Hard;
+            sfdouble = -1; // DP all in softfloat
+            sfsingle = -1;  // SP all in softfloat
+            sfhalf = FPOP_SQRT;    // HP all in HW, except sqrt
+            enphalf = false;
+            enpsingle = false;
+          } else if (fpu == "daifpu_hp_none") {
+            FloatABI = sparc::FloatABI::Hard;
+            sfdouble = -1; // DP all in softfloat
+            sfsingle = -1;  // SP all in softfloat
+            sfhalf = FPOP_DIV | FPOP_SQRT;    // HP all in HW, except div/sqrt
+            enphalf = false;
+            enpsingle = false;
+          } else if (fpu == "daifpu_psp_divsqrt") {
+            FloatABI = sparc::FloatABI::Hard;
+            sfdouble = -1; // DP all in softfloat
+            sfsingle = 0;  // SP all in HW
+            sfhalf = -1;    // HP all in softfloat
+            enphalf = false;
+            enpsingle = true;
+          } else if (fpu == "daifpu_psp_divonly") {
+            FloatABI = sparc::FloatABI::Hard;
+            sfdouble = -1; // DP all in softfloat
+            sfsingle = FPOP_SQRT;  // SP all in HW, except sqrt
+            sfhalf = -1;    // HP all in softfloat
+            enphalf = false;
+            enpsingle = true;
+          } else if (fpu == "daifpu_psp_none") {
+            FloatABI = sparc::FloatABI::Hard;
+            sfdouble = -1; // DP all in softfloat
+            sfsingle = FPOP_DIV | FPOP_SQRT;  // SP all in HW, except div/sqrt
+            sfhalf = -1;    // HP all in softfloat
+            enphalf = false;
+            enpsingle = true;
+          } else if (fpu == "daifpu_php_divsqrt") {
+            FloatABI = sparc::FloatABI::Hard;
+            sfdouble = -1; // DP all in softfloat
+            sfsingle = -1;  // SP all in softfloat
+            sfhalf = 0;    // HP all in HW
+            enphalf = true;
+            enpsingle = false;
+          } else if (fpu == "daifpu_php_divonly") {
+            FloatABI = sparc::FloatABI::Hard;
+            sfdouble = -1; // DP all in softfloat
+            sfsingle = -1;  // SP all in softfloat
+            sfhalf = FPOP_SQRT;    // HP all in HW, except sqrt
+            enphalf = true;
+            enpsingle = false;
+          } else if (fpu == "daifpu_php_none") {
+            FloatABI = sparc::FloatABI::Hard;
+            sfdouble = -1; // DP all in softfloat
+            sfsingle = -1;  // SP all in softfloat
+            sfhalf = FPOP_DIV | FPOP_SQRT;    // HP all in HW, except div/sqrt
+            enphalf = true;
+            enpsingle = false;
+          } else if (fpu == "none") {
+            FloatABI = sparc::FloatABI::Soft;
+            sfdouble = -1;  // DP all in softfloat
+            sfsingle = -1;  // SP all in softfloat
+            sfhalf = -1;    // HP all in softfloat
+            enphalf = false;
+            enpsingle = false;
+          } else {
+            D.Diag(clang::diag::err_drv_invalid_value) << A->getAsString(Args) << fpu;
+          }
+        }
+        break;
+    }
+  }
+
+  if (FloatABI == sparc::FloatABI::Soft) {
     Features.push_back("+soft-float");
+  }
+
+  if (sfhalf & FPOP_ADD) Features.push_back("+soft-fops-half-fadd");
+  if (sfhalf & FPOP_SUB) Features.push_back("+soft-fops-half-fsub");
+  if (sfhalf & FPOP_MUL) Features.push_back("+soft-fops-half-fmul");
+  if (sfhalf & FPOP_DIV) Features.push_back("+soft-fops-half-fdiv");
+  if (sfhalf & FPOP_MULEX) Features.push_back("+soft-fops-half-fmulex");
+  if (sfhalf & FPOP_SQRT) Features.push_back("+soft-fops-half-fsqrt");
+  if (sfhalf & FPOP_CMP) Features.push_back("+soft-fops-half-fcmp");
+  if (sfhalf & FPOP_CI2F) Features.push_back("+soft-fops-half-fci2f");
+  if (sfhalf & FPOP_CF2I) Features.push_back("+soft-fops-half-fcf2i");
+  if (sfhalf & FPOP_CFUP) Features.push_back("+soft-fops-half-fcfup");
+  if (sfhalf & FPOP_CFDN) Features.push_back("+soft-fops-half-fcfdn");
+  if (sfhalf & FPOP_ABS) Features.push_back("+soft-fops-half-fabs");
+//  if (sfhalf & FPOP_PACK) Features.push_back("+soft-fops-half-fpack");
+  if (sfhalf & FPOP_MOV) Features.push_back("+soft-fops-half-fmov");
+  if (sfhalf & FPOP_NEG) Features.push_back("+soft-fops-half-fneg");
+
+  if (sfsingle & FPOP_ADD) Features.push_back("+soft-fops-single-fadd");
+  if (sfsingle & FPOP_SUB) Features.push_back("+soft-fops-single-fsub");
+  if (sfsingle & FPOP_MUL) Features.push_back("+soft-fops-single-fmul");
+  if (sfsingle & FPOP_DIV) Features.push_back("+soft-fops-single-fdiv");
+  if (sfsingle & FPOP_MULEX) Features.push_back("+soft-fops-single-fmulex");
+  if (sfsingle & FPOP_SQRT) Features.push_back("+soft-fops-single-fsqrt");
+  if (sfsingle & FPOP_CMP) Features.push_back("+soft-fops-single-fcmp");
+  if (sfsingle & FPOP_CI2F) Features.push_back("+soft-fops-single-fci2f");
+  if (sfsingle & FPOP_CF2I) Features.push_back("+soft-fops-single-fcf2i");
+  if (sfsingle & FPOP_CFUP) Features.push_back("+soft-fops-single-fcfup");
+  if (sfsingle & FPOP_CFDN) Features.push_back("+soft-fops-single-fcfdn");
+  if (sfsingle & FPOP_ABS) Features.push_back("+soft-fops-single-fabs");
+//  if (sfsingle & FPOP_PACK) Features.push_back("+soft-fops-single-fpack");
+  if (sfsingle & FPOP_MOV) Features.push_back("+soft-fops-single-fmov");
+  if (sfsingle & FPOP_NEG) Features.push_back("+soft-fops-single-fneg");
+
+  if (sfdouble & FPOP_ADD) Features.push_back("+soft-fops-double-fadd");
+  if (sfdouble & FPOP_SUB) Features.push_back("+soft-fops-double-fsub");
+  if (sfdouble & FPOP_MUL) Features.push_back("+soft-fops-double-fmul");
+  if (sfdouble & FPOP_DIV) Features.push_back("+soft-fops-double-fdiv");
+  if (sfdouble & FPOP_MULEX) Features.push_back("+soft-fops-double-fmulex");
+  if (sfdouble & FPOP_SQRT) Features.push_back("+soft-fops-double-fsqrt");
+  if (sfdouble & FPOP_CMP) Features.push_back("+soft-fops-double-fcmp");
+  if (sfdouble & FPOP_CI2F) Features.push_back("+soft-fops-double-fci2f");
+  if (sfdouble & FPOP_CF2I) Features.push_back("+soft-fops-double-fcf2i");
+  if (sfdouble & FPOP_CFUP) Features.push_back("+soft-fops-double-fcfup");
+  if (sfdouble & FPOP_CFDN) Features.push_back("+soft-fops-double-fcfdn");
+  if (sfdouble & FPOP_ABS) Features.push_back("+soft-fops-double-fabs");
+//  if (sfdouble & FPOP_PACK) Features.push_back("+soft-fops-double-fpack");
+  if (sfdouble & FPOP_MOV) Features.push_back("+soft-fops-double-fmov");
+  if (sfdouble & FPOP_NEG) Features.push_back("+soft-fops-double-fneg");
+
+  if (enphalf) Features.push_back("+enable-packedhalf");
+  if (enpsingle) Features.push_back("+enable-packedsingle");
+
+  if (noalignfp) Features.push_back("+unaligned-packed-fp");
+
 }
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp
index 1b8eca0ea0d7..dadee6199c59 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -1987,6 +1987,77 @@ void Clang::AddSparcTargetArgs(const ArgList &Args,
     CmdArgs.push_back("-mfloat-abi");
     CmdArgs.push_back("hard");
   }
+
+  if (Args.hasArg(options::OPT_msoft_fp_half)) {
+    CmdArgs.push_back("-msoft-fp-half");
+  }
+  if (Args.hasArg(options::OPT_msoft_fp_single)) {
+    CmdArgs.push_back("-msoft-fp-single");
+  }
+  if (Args.hasArg(options::OPT_msoft_fp_double)) {
+    CmdArgs.push_back("-msoft-fp-double");
+  }
+
+  if (Args.hasArg(options::OPT_mhard_fp_half)) {
+    CmdArgs.push_back("-mhard-fp-half");
+  }
+  if (Args.hasArg(options::OPT_mhard_fp_single)) {
+    CmdArgs.push_back("-mhard-fp-single");
+  }
+  if (Args.hasArg(options::OPT_mhard_fp_double)) {
+    CmdArgs.push_back("-mhard-fp-double");
+  }
+  // TODO: push soft-fops-half / soft-fops-single / soft-fops-double
+  if (Args.hasArg(options::OPT_msoft_fops_half)) {
+    StringRef fops = Args.getLastArgValue(options::OPT_msoft_fops_half);
+    CmdArgs.push_back(Args.MakeArgString("-msoft-fops-half=" + fops));
+  }
+  if (Args.hasArg(options::OPT_mhard_fops_half)) {
+    StringRef fops = Args.getLastArgValue(options::OPT_mhard_fops_half);
+    CmdArgs.push_back(Args.MakeArgString("-mhard-fops-half=" + fops));
+  }
+  if (Args.hasArg(options::OPT_msoft_fops_single)) {
+    StringRef fops = Args.getLastArgValue(options::OPT_msoft_fops_single);
+    CmdArgs.push_back(Args.MakeArgString("-msoft-fops-single=" + fops));
+  }
+  if (Args.hasArg(options::OPT_mhard_fops_single)) {
+    StringRef fops = Args.getLastArgValue(options::OPT_mhard_fops_single);
+    CmdArgs.push_back(Args.MakeArgString("-mhard-fops-single=" + fops));
+  }
+  if (Args.hasArg(options::OPT_msoft_fops_double)) {
+    StringRef fops = Args.getLastArgValue(options::OPT_msoft_fops_double);
+    CmdArgs.push_back(Args.MakeArgString("-msoft-fops-double=" + fops));
+  }
+  if (Args.hasArg(options::OPT_mhard_fops_double)) {
+    StringRef fops = Args.getLastArgValue(options::OPT_mhard_fops_double);
+    CmdArgs.push_back(Args.MakeArgString("-mhard-fops-double=" + fops));
+  }
+
+  if (Args.hasArg(options::OPT_menable_packedhalf)) {
+    CmdArgs.push_back("-menable-packedhalf");
+  }
+  if (Args.hasArg(options::OPT_menable_packedsingle)) {
+    CmdArgs.push_back("-menable-packedsingle");
+  }
+
+  if (Args.hasArg(options::OPT_daiteq_fpu_type)) {
+    StringRef dfpu = Args.getLastArgValue(options::OPT_daiteq_fpu_type);
+    CmdArgs.push_back(Args.MakeArgString("-daiteq-fpu-type=" + dfpu));
+  }
+
+  if (Args.hasArg(options::OPT_daiteq_swar_enable)) {
+    CmdArgs.push_back("-daiteq-swar-enable");
+  }
+
+  if (Args.hasArg(options::OPT_daiteq_swar_type)) {
+    StringRef dswar = Args.getLastArgValue(options::OPT_daiteq_swar_type);
+    CmdArgs.push_back(Args.MakeArgString("-daiteq-swar-force-config=" + dswar));
+  }
+  
+  if (Args.hasArg(options::OPT_munaligned_packed_fp)) {
+    CmdArgs.push_back("-munaligned-packed-fp");
+  }
+
 }
 
 void Clang::AddSystemZTargetArgs(const ArgList &Args,
diff --git a/clang/lib/Format/FormatToken.h b/clang/lib/Format/FormatToken.h
index 39498280fb6d..7fffb26c394b 100644
--- a/clang/lib/Format/FormatToken.h
+++ b/clang/lib/Format/FormatToken.h
@@ -419,6 +419,7 @@ struct FormatToken {
     case tok::exclaim:
     case tok::tilde:
     case tok::kw_sizeof:
+    case tok::kw_sizeofswar:
     case tok::kw_alignof:
       return true;
     default:
@@ -444,6 +445,7 @@ struct FormatToken {
     case tok::kw_typeid:
     case tok::kw_return:
     case tok::kw_sizeof:
+    case tok::kw_sizeofswar:
     case tok::kw_alignof:
     case tok::kw_alignas:
     case tok::kw_decltype:
diff --git a/clang/lib/Format/TokenAnnotator.cpp b/clang/lib/Format/TokenAnnotator.cpp
index d5d394e61926..f0bcf3ee6cfe 100644
--- a/clang/lib/Format/TokenAnnotator.cpp
+++ b/clang/lib/Format/TokenAnnotator.cpp
@@ -1692,7 +1692,7 @@ private:
     // If a (non-string) literal follows, this is likely a cast.
     if (Tok.Next->isNot(tok::string_literal) &&
         (Tok.Next->Tok.isLiteral() ||
-         Tok.Next->isOneOf(tok::kw_sizeof, tok::kw_alignof)))
+         Tok.Next->isOneOf(tok::kw_sizeof, tok::kw_sizeofswar, tok::kw_alignof)))
       return true;
 
     // Heuristically try to determine whether the parentheses contain a type.
@@ -1766,7 +1766,7 @@ private:
     if (PrevToken->isOneOf(tok::l_paren, tok::l_square, tok::l_brace,
                            tok::comma, tok::semi, tok::kw_return, tok::colon,
                            tok::equal, tok::kw_delete, tok::kw_sizeof,
-                           tok::kw_throw) ||
+                           tok::kw_sizeofswar, tok::kw_throw) ||
         PrevToken->isOneOf(TT_BinaryOperator, TT_ConditionalExpr,
                            TT_UnaryOperator, TT_CastRParen))
       return TT_UnaryOperator;
diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp
index 289c58e3eb9d..c1b6facd7f1f 100644
--- a/clang/lib/Frontend/CompilerInvocation.cpp
+++ b/clang/lib/Frontend/CompilerInvocation.cpp
@@ -664,6 +664,31 @@ static void setPGOUseInstrumentor(CodeGenOptions &Opts,
     Opts.setProfileUse(CodeGenOptions::ProfileClangInstr);
 }
 
+
+// Selection for partial soft-float
+static const struct SoftFopsTableStruct {
+  unsigned mask;
+  char     flag;
+} SoftFopsTable[] = {
+  {llvm::SoftFops::FPOP_ADD,'a'},{llvm::SoftFops::FPOP_SUB,'s'},{llvm::SoftFops::FPOP_MUL,'m'},{llvm::SoftFops::FPOP_DIV,'d'},
+  {llvm::SoftFops::FPOP_MULEX,'M'},{llvm::SoftFops::FPOP_SQRT,'S'},{llvm::SoftFops::FPOP_CMP,'c'},
+  {llvm::SoftFops::FPOP_CI2F,'f'},{llvm::SoftFops::FPOP_CF2I,'i'},{llvm::SoftFops::FPOP_CFUP,'h'},{llvm::SoftFops::FPOP_CFDN,'l'},
+  {llvm::SoftFops::FPOP_ABS,'A'},{llvm::SoftFops::FPOP_PACK,'p'},{llvm::SoftFops::FPOP_MOV,'C'},{llvm::SoftFops::FPOP_NEG,'n'},
+  {0,0}
+};
+unsigned getFopsMask(const std::string &desc)
+{
+  unsigned mask = 0;
+  int i =0;
+  while (SoftFopsTable[i].mask) {
+    if (desc.find(SoftFopsTable[i].flag)!=std::string::npos)
+      mask |= SoftFopsTable[i].mask;
+    i++;
+  }
+  return mask;
+}
+
+
 static bool ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, InputKind IK,
                              DiagnosticsEngine &Diags,
                              const TargetOptions &TargetOpts,
@@ -937,7 +962,293 @@ static bool ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, InputKind IK,
   Opts.NoPLT = Args.hasArg(OPT_fno_plt);
   Opts.SaveTempLabels = Args.hasArg(OPT_msave_temp_labels);
   Opts.NoDwarfDirectoryAsm = Args.hasArg(OPT_fno_dwarf_directory_asm);
-  Opts.SoftFloat = Args.hasArg(OPT_msoft_float);
+
+  /*
+   * For sparc architecture all options around soft-float operations will be position
+   * dependent because they will mask different operations and it si only one way to
+   * reach required combination of all possible possibilities.
+   */
+  if (Triple.getArch() != llvm::Triple::sparc) {
+    Opts.SoftFloat = Args.hasArg(OPT_msoft_float);
+
+//  if (Triple.getArch() == llvm::Triple::sparc) {
+  } else {
+
+    Opts.daiteqFPUType = Args.hasArg(OPT_daiteq_fpu_type);
+    Opts.EnabledSWARdaiteq = Args.hasArg(OPT_daiteq_swar_enable);
+
+    if (Arg *A = Args.getLastArg(OPT_daiteq_swar_type)) {
+      StringRef SKind = A->getValue();
+      if (SKind=="alu") {
+        Opts.UseSWARUnit = llvm::SwarKinds::ALU;
+      } else if (SKind=="video") {
+        Opts.UseSWARUnit = llvm::SwarKinds::Video;
+      } else if (SKind=="audio") {
+        Opts.UseSWARUnit = llvm::SwarKinds::Audio;
+      } else if (SKind=="infer") {
+        Opts.UseSWARUnit = llvm::SwarKinds::Infer;
+      } else
+        Diags.Report(diag::err_drv_invalid_value)
+            << A->getAsString(Args) << A->getValue();
+    } else
+      Opts.UseSWARUnit = llvm::SwarKinds::Infer;
+
+
+    /* all options around soft-float are position dependent */
+    for (const auto &A : Args) {
+      //A->dump();
+      unsigned val;
+      unsigned argid = A->getOption().getID();
+      switch (argid) {
+        case options::OPT_msoft_float:
+          Opts.SoftFloat = true;
+          Opts.SoftFopsHalf = -1;
+          Opts.SoftFopsSingle = -1;
+          Opts.SoftFopsDouble = -1;
+          Opts.EnabledPackedHalf = false;
+          Opts.EnabledPackedSingle = false;
+          break;
+/* half FP */
+        case options::OPT_mhard_fp_half:
+          Opts.SoftFopsHalf = 0; // all half FP ops disabled
+          break;
+        case options::OPT_msoft_fp_half:
+          Opts.SoftFopsHalf = -1; // all half FP ops enabled
+          break;
+        case options::OPT_msoft_fops_half:
+          val = getFopsMask(A->getValue());
+          Opts.SoftFopsHalf |= val;
+          break;
+        case options::OPT_mhard_fops_half:
+          val = getFopsMask(A->getValue());
+          Opts.SoftFopsHalf &= ~val;
+          break;
+/* single FP */
+        case options::OPT_mhard_fp_single:
+          Opts.SoftFopsSingle = 0; // all float FP ops disabled
+          break;
+        case options::OPT_msoft_fp_single:
+          Opts.SoftFopsSingle = -1; // all float FP ops enabled
+          break;
+        case options::OPT_msoft_fops_single:
+          val = getFopsMask(A->getValue()); // -msoft-fops-single=
+          Opts.SoftFopsSingle |= val;
+          break;
+        case options::OPT_mhard_fops_single:
+          val = getFopsMask(A->getValue()); // -mhard-fops-single=
+          Opts.SoftFopsSingle &= ~val;
+          break;
+/* double FP */
+        case options::OPT_mhard_fp_double:
+          Opts.SoftFopsDouble = 0; // all float FP ops disabled
+          break;
+        case options::OPT_msoft_fp_double:
+          Opts.SoftFopsDouble = -1; // all float FP ops enabled
+          break;
+        case options::OPT_msoft_fops_double:
+          val = getFopsMask(A->getValue()); // -msoft-fops-double=
+          Opts.SoftFopsDouble |= val;
+          break;
+        case options::OPT_mhard_fops_double:
+          val = getFopsMask(A->getValue()); // -mhard-fops-double=
+          Opts.SoftFopsDouble &= ~val;
+          break;
+/* packed half FP */
+        case options::OPT_menable_packedhalf:
+          Opts.EnabledPackedHalf = true;
+          break;
+/* packed single FP */
+        case options::OPT_menable_packedsingle:
+          Opts.EnabledPackedSingle = true;
+          break;
+
+        case options::OPT_daiteq_fpu_type:
+        { // the same selection is in clang/lib/Driver/ToolChains/Arch/Sparc.cpp
+          StringRef fpu = A->getValue();
+          if (fpu == "daifpu_divsqrt") {
+            Opts.SoftFloat = false;
+            Opts.SoftFopsDouble = 0; // DP all in HW
+            Opts.SoftFopsSingle = 0; // SP all in HW
+            Opts.SoftFopsHalf = -1; // HP all in softfloat
+            Opts.EnabledPackedHalf = false;
+            Opts.EnabledPackedSingle = false;
+          } else if (fpu == "daifpu_divonly") { // DP,SP - SQRT in softfloat
+            Opts.SoftFloat = false;
+            Opts.SoftFopsDouble = llvm::SoftFops::FPOP_SQRT; // DP all in HW, except sqrt
+            Opts.SoftFopsSingle = llvm::SoftFops::FPOP_SQRT; // SP all in HW, except sqrt
+            Opts.SoftFopsHalf = -1; // HP all in softfloat
+            Opts.EnabledPackedHalf = false;
+            Opts.EnabledPackedSingle = false;
+          } else if (fpu == "daifpu_none") {
+            Opts.SoftFloat = false;
+            Opts.SoftFopsDouble = llvm::SoftFops::FPOP_DIV | llvm::SoftFops::FPOP_SQRT; // DP all in HW, except div/sqrt
+            Opts.SoftFopsSingle = llvm::SoftFops::FPOP_DIV | llvm::SoftFops::FPOP_SQRT; // SP all in HW, except div/sqrt
+            Opts.SoftFopsHalf = -1; // HP all in softfloat
+            Opts.EnabledPackedHalf = false;
+            Opts.EnabledPackedSingle = false;
+          } else if (fpu == "daifpu_dual_dpsp_divsqrt") {
+            Opts.SoftFloat = false;
+            Opts.SoftFopsDouble = 0; // DP all in HW
+            Opts.SoftFopsSingle = 0; // SP all in HW
+            Opts.SoftFopsHalf = -1; // HP all in softfloat
+            Opts.EnabledPackedHalf = false;
+            Opts.EnabledPackedSingle = false;
+          } else if (fpu == "daifpu_dual_dpsp_divonly") {
+            Opts.SoftFloat = false;
+            Opts.SoftFopsDouble = llvm::SoftFops::FPOP_SQRT; // DP all in HW, except sqrt
+            Opts.SoftFopsSingle = llvm::SoftFops::FPOP_SQRT; // SP all in HW, except sqrt
+            Opts.SoftFopsHalf = -1; // HP all in softfloat
+            Opts.EnabledPackedHalf = false;
+            Opts.EnabledPackedSingle = false;
+          } else if (fpu == "daifpu_dual_dpsp_none") {
+            Opts.SoftFloat = false;
+            Opts.SoftFopsDouble = llvm::SoftFops::FPOP_DIV | llvm::SoftFops::FPOP_SQRT; // DP all in HW, except div/sqrt
+            Opts.SoftFopsSingle = llvm::SoftFops::FPOP_DIV | llvm::SoftFops::FPOP_SQRT; // SP all in HW, except div/sqrt
+            Opts.SoftFopsHalf = -1; // HP all in softfloat
+            Opts.EnabledPackedHalf = false;
+            Opts.EnabledPackedSingle = false;
+          } else if (fpu == "daifpu_dual_sphp_divsqrt") {
+            Opts.SoftFloat = false;
+            Opts.SoftFopsDouble = -1; // DP all in softfloat
+            Opts.SoftFopsSingle = 0;  // SP all in HW
+            Opts.SoftFopsHalf = 0;    // HP all in HW
+            Opts.EnabledPackedHalf = false;
+            Opts.EnabledPackedSingle = false;
+          } else if (fpu == "daifpu_dual_sphp_divonly") {
+            Opts.SoftFloat = false;
+            Opts.SoftFopsDouble = -1; // DP all in softfloat
+            Opts.SoftFopsSingle = llvm::SoftFops::FPOP_SQRT;  // SP all in HW, except sqrt
+            Opts.SoftFopsHalf = llvm::SoftFops::FPOP_SQRT;    // HP all in HW, except sqrt
+            Opts.EnabledPackedHalf = false;
+            Opts.EnabledPackedSingle = false;
+          } else if (fpu == "daifpu_dual_sphp_none") {
+            Opts.SoftFloat = false;
+            Opts.SoftFopsDouble = -1; // DP all in softfloat
+            Opts.SoftFopsSingle = llvm::SoftFops::FPOP_DIV | llvm::SoftFops::FPOP_SQRT;  // SP all in HW, except div/sqrt
+            Opts.SoftFopsHalf = llvm::SoftFops::FPOP_DIV | llvm::SoftFops::FPOP_SQRT;    // HP all in HW, except div/sqrt
+            Opts.EnabledPackedHalf = false;
+            Opts.EnabledPackedSingle = false;
+          } else if (fpu == "daifpu_dp_divsqrt") {
+            Opts.SoftFloat = false;
+            Opts.SoftFopsDouble = 0; // DP all in HW
+            Opts.SoftFopsSingle = -1; // SP all in softfloat
+            Opts.SoftFopsHalf = -1; // HP all in softfloat
+            Opts.EnabledPackedHalf = false;
+            Opts.EnabledPackedSingle = false;
+          } else if (fpu == "daifpu_dp_divonly") {
+            Opts.SoftFloat = false;
+            Opts.SoftFopsDouble = llvm::SoftFops::FPOP_SQRT;  // DP all in HW, except sqrt
+            Opts.SoftFopsSingle = -1; // SP all in softfloat
+            Opts.SoftFopsHalf = -1; // HP all in softfloat
+            Opts.EnabledPackedHalf = false;
+            Opts.EnabledPackedSingle = false;
+          } else if (fpu == "daifpu_dp_none") {
+            Opts.SoftFloat = false;
+            Opts.SoftFopsDouble = llvm::SoftFops::FPOP_DIV | llvm::SoftFops::FPOP_SQRT;  // DP all in HW, except div/sqrt
+            Opts.SoftFopsSingle = -1; // SP all in softfloat
+            Opts.SoftFopsHalf = -1; // HP all in softfloat
+            Opts.EnabledPackedHalf = false;
+            Opts.EnabledPackedSingle = false;
+          } else if (fpu == "daifpu_sp_divsqrt") {
+            Opts.SoftFloat = false;
+            Opts.SoftFopsDouble = -1; // DP all in softfloat
+            Opts.SoftFopsSingle = 0;  // SP all in HW
+            Opts.SoftFopsHalf = -1;    // HP all in softfloat
+            Opts.EnabledPackedHalf = false;
+            Opts.EnabledPackedSingle = false;
+          } else if (fpu == "daifpu_sp_divonly") {
+            Opts.SoftFloat = false;
+            Opts.SoftFopsDouble = -1; // DP all in softfloat
+            Opts.SoftFopsSingle = llvm::SoftFops::FPOP_SQRT;  // SP all in HW, except sqrt
+            Opts.SoftFopsHalf = -1;    // HP all in softfloat
+            Opts.EnabledPackedHalf = false;
+            Opts.EnabledPackedSingle = false;
+          } else if (fpu == "daifpu_sp_none") {
+            Opts.SoftFloat = false;
+            Opts.SoftFopsDouble = -1; // DP all in softfloat
+            Opts.SoftFopsSingle = llvm::SoftFops::FPOP_DIV | llvm::SoftFops::FPOP_SQRT;  // SP all in HW, except div/sqrt
+            Opts.SoftFopsHalf = -1;    // HP all in softfloat
+            Opts.EnabledPackedHalf = false;
+            Opts.EnabledPackedSingle = false;
+          } else if (fpu == "daifpu_hp_divsqrt") {
+            Opts.SoftFloat = false;
+            Opts.SoftFopsDouble = -1; // DP all in softfloat
+            Opts.SoftFopsSingle = -1;  // SP all in softfloat
+            Opts.SoftFopsHalf = 0;    // HP all in HW
+            Opts.EnabledPackedHalf = false;
+            Opts.EnabledPackedSingle = false;
+          } else if (fpu == "daifpu_hp_divonly") {
+            Opts.SoftFloat = false;
+            Opts.SoftFopsDouble = -1; // DP all in softfloat
+            Opts.SoftFopsSingle = -1;  // SP all in softfloat
+            Opts.SoftFopsHalf = llvm::SoftFops::FPOP_SQRT;    // HP all in HW, except sqrt
+            Opts.EnabledPackedHalf = false;
+            Opts.EnabledPackedSingle = false;
+          } else if (fpu == "daifpu_hp_none") {
+            Opts.SoftFloat = false;
+            Opts.SoftFopsDouble = -1; // DP all in softfloat
+            Opts.SoftFopsSingle = -1;  // SP all in softfloat
+            Opts.SoftFopsHalf = llvm::SoftFops::FPOP_DIV | llvm::SoftFops::FPOP_SQRT;    // HP all in HW, except div/sqrt
+            Opts.EnabledPackedHalf = false;
+            Opts.EnabledPackedSingle = false;
+          } else if (fpu == "daifpu_psp_divsqrt") {
+            Opts.SoftFloat = false;
+            Opts.SoftFopsDouble = -1; // DP all in softfloat
+            Opts.SoftFopsSingle = 0;  // SP all in HW
+            Opts.SoftFopsHalf = -1;    // HP all in softfloat
+            Opts.EnabledPackedHalf = false;
+            Opts.EnabledPackedSingle = true;
+          } else if (fpu == "daifpu_psp_divonly") {
+            Opts.SoftFloat = false;
+            Opts.SoftFopsDouble = -1; // DP all in softfloat
+            Opts.SoftFopsSingle = llvm::SoftFops::FPOP_SQRT;  // SP all in HW, except sqrt
+            Opts.SoftFopsHalf = -1;    // HP all in softfloat
+            Opts.EnabledPackedHalf = false;
+            Opts.EnabledPackedSingle = true;
+          } else if (fpu == "daifpu_psp_none") {
+            Opts.SoftFloat = false;
+            Opts.SoftFopsDouble = -1; // DP all in softfloat
+            Opts.SoftFopsSingle = llvm::SoftFops::FPOP_DIV | llvm::SoftFops::FPOP_SQRT;  // SP all in HW, except div/sqrt
+            Opts.SoftFopsHalf = -1;    // HP all in softfloat
+            Opts.EnabledPackedHalf = false;
+            Opts.EnabledPackedSingle = true;
+          } else if (fpu == "daifpu_php_divsqrt") {
+            Opts.SoftFloat = false;
+            Opts.SoftFopsDouble = -1; // DP all in softfloat
+            Opts.SoftFopsSingle = -1;  // SP all in softfloat
+            Opts.SoftFopsHalf = 0;    // HP all in HW
+            Opts.EnabledPackedHalf = true;
+            Opts.EnabledPackedSingle = false;
+          } else if (fpu == "daifpu_php_divonly") {
+            Opts.SoftFloat = false;
+            Opts.SoftFopsDouble = -1; // DP all in softfloat
+            Opts.SoftFopsSingle = -1;  // SP all in softfloat
+            Opts.SoftFopsHalf = llvm::SoftFops::FPOP_SQRT;    // HP all in HW, except sqrt
+            Opts.EnabledPackedHalf = true;
+            Opts.EnabledPackedSingle = false;
+          } else if (fpu == "daifpu_php_none") {
+            Opts.SoftFloat = false;
+            Opts.SoftFopsDouble = -1; // DP all in softfloat
+            Opts.SoftFopsSingle = -1;  // SP all in softfloat
+            Opts.SoftFopsHalf = llvm::SoftFops::FPOP_DIV | llvm::SoftFops::FPOP_SQRT;    // HP all in HW, except div/sqrt
+            Opts.EnabledPackedHalf = true;
+            Opts.EnabledPackedSingle = false;
+          } else if (fpu == "none") {
+            Opts.SoftFloat = true;
+            Opts.SoftFopsDouble = -1;  // DP all in softfloat
+            Opts.SoftFopsSingle = -1;  // SP all in softfloat
+            Opts.SoftFopsHalf = -1;    // HP all in softfloat
+            Opts.EnabledPackedHalf = false;
+            Opts.EnabledPackedSingle = false;
+          } else {
+            Diags.Report(diag::err_drv_invalid_value) << A->getAsString(Args) << fpu;
+          }
+        }
+        break;
+      }
+    }
+  }
+
   Opts.StrictEnums = Args.hasArg(OPT_fstrict_enums);
   Opts.StrictReturn = !Args.hasArg(OPT_fno_strict_return);
   Opts.StrictVTablePointers = Args.hasArg(OPT_fstrict_vtable_pointers);
@@ -2515,6 +2826,33 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK,
   llvm::Triple T(TargetOpts.Triple);
   CompilerInvocation::setLangDefaults(Opts, IK, T, PPOpts, LangStd);
 
+  // daiteq extensions for Sparc with configurable FPU
+  if (T.getArch() == llvm::Triple::sparc &&
+      T.getVendor() == llvm::Triple::Daiteq) {
+    Opts.NativeHalfType = 1;
+    Opts.NativeHalfArgsAndReturns = 1;
+    Opts.Half = 1;
+
+    Opts.EnabledSWARdaiteq = Args.hasArg(OPT_daiteq_swar_enable);
+
+    if (Arg *A = Args.getLastArg(OPT_daiteq_swar_type)) {
+      StringRef SKind = A->getValue();
+      if (SKind=="alu") {
+        Opts.UseSWARUnit = llvm::SwarKinds::ALU;
+      } else if (SKind=="video") {
+        Opts.UseSWARUnit = llvm::SwarKinds::Video;
+      } else if (SKind=="audio") {
+        Opts.UseSWARUnit = llvm::SwarKinds::Audio;
+      } else if (SKind=="infer") {
+        Opts.UseSWARUnit = llvm::SwarKinds::Infer;
+      } else
+        Diags.Report(diag::err_drv_invalid_value)
+            << A->getAsString(Args) << A->getValue();
+    } else
+      Opts.UseSWARUnit = llvm::SwarKinds::Infer;
+
+  }
+
   // -cl-strict-aliasing needs to emit diagnostic in the case where CL > 1.0.
   // This option should be deprecated for CL > 1.0 because
   // this option was added for compatibility with OpenCL 1.0.
diff --git a/clang/lib/Parse/ParseExpr.cpp b/clang/lib/Parse/ParseExpr.cpp
index b74a95a3cd4b..b5256138c276 100644
--- a/clang/lib/Parse/ParseExpr.cpp
+++ b/clang/lib/Parse/ParseExpr.cpp
@@ -1206,6 +1206,8 @@ ExprResult Parser::ParseCastExpression(bool isUnaryExpression,
                            // unary-expression: '__alignof' '(' type-name ')'
   case tok::kw_sizeof:     // unary-expression: 'sizeof' unary-expression
                            // unary-expression: 'sizeof' '(' type-name ')'
+  case tok::kw_sizeofswar: // unary-expression: 'sizeofswar' unary-expression
+                           // unary-expression: 'sizeofswar' '(' type-name ')'
   case tok::kw_vec_step:   // unary-expression: OpenCL 'vec_step' expression
   // unary-expression: '__builtin_omp_required_simd_align' '(' type-name ')'
   case tok::kw___builtin_omp_required_simd_align:
@@ -1892,7 +1894,7 @@ Parser::ParseExprAfterUnaryExprOrTypeTrait(const Token &OpTok,
                                            ParsedType &CastTy,
                                            SourceRange &CastRange) {
 
-  assert(OpTok.isOneOf(tok::kw_typeof, tok::kw_sizeof, tok::kw___alignof,
+  assert(OpTok.isOneOf(tok::kw_typeof, tok::kw_sizeof, tok::kw_sizeofswar, tok::kw___alignof,
                        tok::kw_alignof, tok::kw__Alignof, tok::kw_vec_step,
                        tok::kw___builtin_omp_required_simd_align) &&
          "Not a typeof/sizeof/alignof/vec_step expression!");
@@ -1903,7 +1905,7 @@ Parser::ParseExprAfterUnaryExprOrTypeTrait(const Token &OpTok,
   if (Tok.isNot(tok::l_paren)) {
     // If construct allows a form without parenthesis, user may forget to put
     // pathenthesis around type name.
-    if (OpTok.isOneOf(tok::kw_sizeof, tok::kw___alignof, tok::kw_alignof,
+    if (OpTok.isOneOf(tok::kw_sizeof, tok::kw_sizeofswar, tok::kw___alignof, tok::kw_alignof,
                       tok::kw__Alignof)) {
       if (isTypeIdUnambiguously()) {
         DeclSpec DS(AttrFactory);
@@ -1978,7 +1980,7 @@ Parser::ParseExprAfterUnaryExprOrTypeTrait(const Token &OpTok,
 /// [C++11] 'alignof' '(' type-id ')'
 /// \endverbatim
 ExprResult Parser::ParseUnaryExprOrTypeTraitExpression() {
-  assert(Tok.isOneOf(tok::kw_sizeof, tok::kw___alignof, tok::kw_alignof,
+  assert(Tok.isOneOf(tok::kw_sizeof, tok::kw_sizeofswar, tok::kw___alignof, tok::kw_alignof,
                      tok::kw__Alignof, tok::kw_vec_step,
                      tok::kw___builtin_omp_required_simd_align) &&
          "Not a sizeof/alignof/vec_step expression!");
@@ -1986,7 +1988,7 @@ ExprResult Parser::ParseUnaryExprOrTypeTraitExpression() {
   ConsumeToken();
 
   // [C++11] 'sizeof' '...' '(' identifier ')'
-  if (Tok.is(tok::ellipsis) && OpTok.is(tok::kw_sizeof)) {
+  if (Tok.is(tok::ellipsis) && OpTok.is(tok::kw_sizeof) && OpTok.is(tok::kw_sizeofswar)) {
     SourceLocation EllipsisLoc = ConsumeToken();
     SourceLocation LParenLoc, RParenLoc;
     IdentifierInfo *Name = nullptr;
@@ -2048,7 +2050,9 @@ ExprResult Parser::ParseUnaryExprOrTypeTraitExpression() {
                                                           CastRange);
 
   UnaryExprOrTypeTrait ExprKind = UETT_SizeOf;
-  if (OpTok.isOneOf(tok::kw_alignof, tok::kw__Alignof))
+  if (OpTok.is(tok::kw_sizeofswar))
+    ExprKind = UETT_SizeOfSwar;
+  else if (OpTok.isOneOf(tok::kw_alignof, tok::kw__Alignof))
     ExprKind = UETT_AlignOf;
   else if (OpTok.is(tok::kw___alignof))
     ExprKind = UETT_PreferredAlignOf;
diff --git a/clang/lib/Parse/ParseObjc.cpp b/clang/lib/Parse/ParseObjc.cpp
index efcef6d3b123..f9b6a6a29f11 100644
--- a/clang/lib/Parse/ParseObjc.cpp
+++ b/clang/lib/Parse/ParseObjc.cpp
@@ -1078,6 +1078,7 @@ IdentifierInfo *Parser::ParseObjCSelectorPiece(SourceLocation &SelectorLoc) {
   case tok::kw_short:
   case tok::kw_signed:
   case tok::kw_sizeof:
+  case tok::kw_sizeofswar:
   case tok::kw_static:
   case tok::kw_static_cast:
   case tok::kw_struct:
diff --git a/clang/lib/Parse/ParsePragma.cpp b/clang/lib/Parse/ParsePragma.cpp
index df411e1928d6..da2647ba2572 100644
--- a/clang/lib/Parse/ParsePragma.cpp
+++ b/clang/lib/Parse/ParsePragma.cpp
@@ -262,6 +262,44 @@ struct PragmaAttributeHandler : public PragmaHandler {
   ParsedAttributes AttributesForPragmaAttribute;
 };
 
+/// PragmaSWARSaturateHandler - "\#pragma swar saturate".
+struct PragmaSWARSaturateHandler : public PragmaHandler {
+  explicit PragmaSWARSaturateHandler(Sema &S)
+             : PragmaHandler("saturate"), Actions(S) {}
+  void HandlePragma(Preprocessor &PP, PragmaIntroducer Introducer,
+                    Token &FirstToken) override;
+private:
+  Sema &Actions;
+};
+/// PragmaSWARReductionHandler - "\#pragma swar reduction".
+struct PragmaSWARReductionHandler : public PragmaHandler {
+  explicit PragmaSWARReductionHandler(Sema &S)
+             : PragmaHandler("reduce"), Actions(S) {}
+  void HandlePragma(Preprocessor &PP, PragmaIntroducer Introducer,
+                    Token &FirstToken) override;
+private:
+  Sema &Actions;
+};
+/// PragmaSWARNormalizeHandler - "\#pragma swar normalize".
+struct PragmaSWARNormalizeHandler : public PragmaHandler {
+  explicit PragmaSWARNormalizeHandler(Sema &S)
+             : PragmaHandler("normalize"), Actions(S) {}
+  void HandlePragma(Preprocessor &PP, PragmaIntroducer Introducer,
+                    Token &FirstToken) override;
+private:
+  Sema &Actions;
+};
+
+/// PragmaSWARManualHandler - "\#pragma swar manual".
+struct PragmaSWARManualHandler : public PragmaHandler {
+  explicit PragmaSWARManualHandler(Sema &S)
+             : PragmaHandler("manual"), Actions(S) {}
+  void HandlePragma(Preprocessor &PP, PragmaIntroducer Introducer,
+                    Token &FirstToken) override;
+private:
+  Sema &Actions;
+};
+
 }  // end namespace
 
 void Parser::initializePragmaHandlers() {
@@ -382,6 +420,19 @@ void Parser::initializePragmaHandlers() {
   AttributePragmaHandler =
       std::make_unique<PragmaAttributeHandler>(AttrFactory);
   PP.AddPragmaHandler("clang", AttributePragmaHandler.get());
+
+
+  SwarSaturateHandler = std::make_unique<PragmaSWARSaturateHandler>(Actions);
+  PP.AddPragmaHandler("swar", SwarSaturateHandler.get());
+
+  SwarReductionHandler = std::make_unique<PragmaSWARReductionHandler>(Actions);
+  PP.AddPragmaHandler("swar", SwarReductionHandler.get());
+
+  SwarNormalizeHandler = std::make_unique<PragmaSWARNormalizeHandler>(Actions);
+  PP.AddPragmaHandler("swar", SwarNormalizeHandler.get());
+
+  SwarManualHandler = std::make_unique<PragmaSWARManualHandler>(Actions);
+  PP.AddPragmaHandler("swar", SwarManualHandler.get());
 }
 
 void Parser::resetPragmaHandlers() {
@@ -487,6 +538,19 @@ void Parser::resetPragmaHandlers() {
 
   PP.RemovePragmaHandler("clang", AttributePragmaHandler.get());
   AttributePragmaHandler.reset();
+
+
+  PP.RemovePragmaHandler("swar", SwarSaturateHandler.get());
+  SwarSaturateHandler.reset();
+
+  PP.RemovePragmaHandler("swar", SwarReductionHandler.get());
+  SwarReductionHandler.reset();
+
+  PP.RemovePragmaHandler("swar", SwarNormalizeHandler.get());
+  SwarNormalizeHandler.reset();
+
+  PP.RemovePragmaHandler("swar", SwarManualHandler.get());
+  SwarManualHandler.reset();
 }
 
 /// Handle the annotation token produced for #pragma unused(...)
@@ -3279,3 +3343,65 @@ void PragmaAttributeHandler::HandlePragma(Preprocessor &PP,
   PP.EnterTokenStream(std::move(TokenArray), 1,
                       /*DisableMacroExpansion=*/false, /*IsReinject=*/false);
 }
+
+
+/// Handle the SWAR saturate pragma.
+///  #pragma swar saturate
+///
+/// Set the saturation flag for the following swar instructions in the current block.
+void PragmaSWARSaturateHandler::HandlePragma(Preprocessor &PP,
+                                           PragmaIntroducer Introducer,
+                                           Token &FirstToken) {
+  Token Tok;
+  PP.Lex(Tok);
+  if (!Tok.is(tok::eod)) {
+    fprintf(stderr,"SWAR saturate pragma with argument...\n");
+  }
+  Actions.ActOnPragmaSwarSaturate(FirstToken.getLocation(), Actions.getCurScope(), true);
+}
+
+/// Handle the SWAR reduction pragma.
+///  #pragma swar reduction
+///
+/// Set the reduction flag for the following swar instructions in the current block.
+void PragmaSWARReductionHandler::HandlePragma(Preprocessor &PP,
+                                              PragmaIntroducer Introducer,
+                                              Token &FirstToken) {
+  Token Tok;
+  PP.Lex(Tok);
+  if (!Tok.is(tok::eod)) {
+    fprintf(stderr,"SWAR reduction pragma with argument...\n");
+  }
+  Actions.ActOnPragmaSwarReduce(FirstToken.getLocation(), Actions.getCurScope(), true);
+}
+
+/// Handle the SWAR normalize pragma.
+///  #pragma swar normalize
+///
+/// Set the normalize flag for the following swar instructions in the current scope block.
+void PragmaSWARNormalizeHandler::HandlePragma(Preprocessor &PP,
+                                              PragmaIntroducer Introducer,
+                                              Token &FirstToken) {
+  Token Tok;
+  PP.Lex(Tok);
+  if (!Tok.is(tok::eod)) {
+    fprintf(stderr,"SWAR normalize pragma with argument...\n");
+  }
+  Actions.ActOnPragmaSwarNormalize(FirstToken.getLocation(), Actions.getCurScope(), true);
+}
+
+/// Handle the SWAR manual pragma.
+///  #pragma swar manual
+///
+/// Set the manual flag for the following swar instructions in the current scope block.
+/// Manual flag disable automatical inserting "swarctrl" for the all following swar instructions in the current block.
+void PragmaSWARManualHandler::HandlePragma(Preprocessor &PP,
+                                           PragmaIntroducer Introducer,
+                                           Token &FirstToken) {
+  Token Tok;
+  PP.Lex(Tok);
+  if (!Tok.is(tok::eod)) {
+    fprintf(stderr,"SWAR manual pragma with argument...\n");
+  }
+  Actions.ActOnPragmaSwarManual(FirstToken.getLocation(), Actions.getCurScope(), true);
+}
diff --git a/clang/lib/Parse/ParseTentative.cpp b/clang/lib/Parse/ParseTentative.cpp
index 9cc41328c469..d2a697e1c738 100644
--- a/clang/lib/Parse/ParseTentative.cpp
+++ b/clang/lib/Parse/ParseTentative.cpp
@@ -1069,6 +1069,7 @@ Parser::isExpressionOrTypeSpecifierSimple(tok::TokenKind Kind) {
   case tok::tilde:
   case tok::exclaim:
   case tok::kw_sizeof:
+  case tok::kw_sizeofswar:
   case tok::kw___func__:
   case tok::kw_const_cast:
   case tok::kw_delete:
diff --git a/clang/lib/Sema/DeclSpec.cpp b/clang/lib/Sema/DeclSpec.cpp
index 639231c87232..d8d6d2d77133 100644
--- a/clang/lib/Sema/DeclSpec.cpp
+++ b/clang/lib/Sema/DeclSpec.cpp
@@ -1227,7 +1227,7 @@ void DeclSpec::Finish(Sema &S, const PrintingPolicy &Policy) {
       // Note that this intentionally doesn't include _Complex _Bool.
       if (!S.getLangOpts().CPlusPlus)
         S.Diag(TSTLoc, diag::ext_integer_complex);
-    } else if (TypeSpecType != TST_float && TypeSpecType != TST_double) {
+    } else if (TypeSpecType != TST_float && TypeSpecType != TST_double && TypeSpecType != TST_half) {
       S.Diag(TSCLoc, diag::err_invalid_complex_spec)
         << getSpecifierName((TST)TypeSpecType, Policy);
       TypeSpecComplex = TSC_unspecified;
diff --git a/clang/lib/Sema/SemaAttr.cpp b/clang/lib/Sema/SemaAttr.cpp
index cd2a65276b09..98e698235eb3 100644
--- a/clang/lib/Sema/SemaAttr.cpp
+++ b/clang/lib/Sema/SemaAttr.cpp
@@ -993,3 +993,42 @@ void Sema::PopPragmaVisibility(bool IsNamespaceEnd, SourceLocation EndLoc) {
   if (Stack->empty())
     FreeVisContext();
 }
+
+/* update swarflags specific for each scope block */
+void Sema::ActOnPragmaSwarSaturate(SourceLocation PragmaLoc, Scope *curScope, bool enbl) {
+  if (curScope->getFnParent()->getEntity()) {
+    DeclContext *dc = curScope->getFnParent()->getEntity();
+    if (!dc->swarPragmaLoc[DeclContext::SwarIndices::saturateIdx].isValid())
+      dc->swarPragmaLoc[DeclContext::SwarIndices::saturateIdx] = PragmaLoc;
+  } else {
+    Diag(PragmaLoc, diag::err_swar_pragma_outside_declctx);
+  }
+}
+void Sema::ActOnPragmaSwarReduce(SourceLocation PragmaLoc, Scope *curScope, bool enbl) {
+  if (curScope->getFnParent()->getEntity()) {
+    DeclContext *dc = curScope->getFnParent()->getEntity();
+    if (!dc->swarPragmaLoc[DeclContext::SwarIndices::reduceIdx].isValid())
+      dc->swarPragmaLoc[DeclContext::SwarIndices::reduceIdx] = PragmaLoc;
+  } else {
+    Diag(PragmaLoc, diag::err_swar_pragma_outside_declctx);
+  }
+}
+void Sema::ActOnPragmaSwarNormalize(SourceLocation PragmaLoc, Scope *curScope, bool enbl) {
+  if (curScope->getFnParent()->getEntity()) {
+    DeclContext *dc = curScope->getFnParent()->getEntity();
+    if (!dc->swarPragmaLoc[DeclContext::SwarIndices::normalizeIdx].isValid())
+      dc->swarPragmaLoc[DeclContext::SwarIndices::normalizeIdx] = PragmaLoc;
+  } else {
+    Diag(PragmaLoc, diag::err_swar_pragma_outside_declctx);
+  }
+}
+void Sema::ActOnPragmaSwarManual(SourceLocation PragmaLoc, Scope *curScope, bool enbl) {
+
+  if (curScope->getFnParent()->getEntity()) {
+    DeclContext *dc = curScope->getFnParent()->getEntity();
+    if (!dc->swarPragmaLoc[DeclContext::SwarIndices::manualIdx].isValid())
+      dc->swarPragmaLoc[DeclContext::SwarIndices::manualIdx] = PragmaLoc;
+  } else {
+    Diag(PragmaLoc, diag::err_swar_pragma_outside_declctx);
+  }
+}
diff --git a/clang/lib/Sema/SemaCast.cpp b/clang/lib/Sema/SemaCast.cpp
index 6216206690b0..5d7ba1890c82 100644
--- a/clang/lib/Sema/SemaCast.cpp
+++ b/clang/lib/Sema/SemaCast.cpp
@@ -2629,7 +2629,8 @@ void CastOperation::CheckCStyleCast() {
     return;
   }
 
-  if (!DestType->isScalarType() && !DestType->isVectorType()) {
+  if (!DestType->isScalarType() &&
+      !(DestType->isVectorType() || DestType->isSubwordType())) {
     const RecordType *DestRecordTy = DestType->getAs<RecordType>();
 
     if (DestRecordTy && Self.Context.hasSameUnqualifiedType(DestType, SrcType)){
@@ -2680,6 +2681,12 @@ void CastOperation::CheckCStyleCast() {
     return;
   }
 
+  if (const SubwordType *DestSWTy = DestType->getAs<SubwordType>()) {
+      Kind = CK_IntegralCast;
+      return;
+    return;
+  }
+
   // The type we're casting to is known to be a scalar or vector.
 
   // Require the operand to be a scalar or vector.
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index d8711fb6bcab..3e430ac9f461 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -8900,6 +8900,8 @@ static unsigned getLargerAbsoluteValueFunction(unsigned AbsFunction) {
   case Builtin::BI__builtin_llabs:
     return 0;
 
+  case Builtin::BI__builtin_fabsh:
+    return Builtin::BI__builtin_fabsf;
   case Builtin::BI__builtin_fabsf:
     return Builtin::BI__builtin_fabs;
   case Builtin::BI__builtin_fabs:
@@ -8921,6 +8923,8 @@ static unsigned getLargerAbsoluteValueFunction(unsigned AbsFunction) {
   case Builtin::BIllabs:
     return 0;
 
+  case Builtin::BIfabsh:
+    return Builtin::BIfabsf;
   case Builtin::BIfabsf:
     return Builtin::BIfabs;
   case Builtin::BIfabs:
@@ -9005,6 +9009,7 @@ static unsigned changeAbsFunction(unsigned AbsKind,
     switch (AbsKind) {
     default:
       return 0;
+    case Builtin::BI__builtin_fabsh:
     case Builtin::BI__builtin_fabsf:
     case Builtin::BI__builtin_fabs:
     case Builtin::BI__builtin_fabsl:
@@ -9012,6 +9017,7 @@ static unsigned changeAbsFunction(unsigned AbsKind,
     case Builtin::BI__builtin_cabs:
     case Builtin::BI__builtin_cabsl:
       return Builtin::BI__builtin_abs;
+    case Builtin::BIfabsh:
     case Builtin::BIfabsf:
     case Builtin::BIfabs:
     case Builtin::BIfabsl:
@@ -9046,6 +9052,7 @@ static unsigned changeAbsFunction(unsigned AbsKind,
     case Builtin::BI__builtin_abs:
     case Builtin::BI__builtin_labs:
     case Builtin::BI__builtin_llabs:
+    case Builtin::BI__builtin_fabsh:
     case Builtin::BI__builtin_fabsf:
     case Builtin::BI__builtin_fabs:
     case Builtin::BI__builtin_fabsl:
@@ -9053,6 +9060,7 @@ static unsigned changeAbsFunction(unsigned AbsKind,
     case Builtin::BIabs:
     case Builtin::BIlabs:
     case Builtin::BIllabs:
+    case Builtin::BIfabsh:
     case Builtin::BIfabsf:
     case Builtin::BIfabs:
     case Builtin::BIfabsl:
@@ -9071,6 +9079,7 @@ static unsigned getAbsoluteValueFunctionKind(const FunctionDecl *FDecl) {
   default:
     return 0;
   case Builtin::BI__builtin_abs:
+  case Builtin::BI__builtin_fabsh:
   case Builtin::BI__builtin_fabs:
   case Builtin::BI__builtin_fabsf:
   case Builtin::BI__builtin_fabsl:
@@ -9082,6 +9091,7 @@ static unsigned getAbsoluteValueFunctionKind(const FunctionDecl *FDecl) {
   case Builtin::BIabs:
   case Builtin::BIlabs:
   case Builtin::BIllabs:
+  case Builtin::BIfabsh:
   case Builtin::BIfabs:
   case Builtin::BIfabsf:
   case Builtin::BIfabsl:
diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp
index 15e86ba8e8d5..a1c30ec9cb68 100644
--- a/clang/lib/Sema/SemaExpr.cpp
+++ b/clang/lib/Sema/SemaExpr.cpp
@@ -3642,7 +3642,8 @@ ExprResult Sema::ActOnNumericConstant(const Token &Tok, Scope *UDLScope) {
   } else if (Literal.isFloatingLiteral()) {
     QualType Ty;
     if (Literal.isHalf){
-      if (getOpenCLOptions().isEnabled("cl_khr_fp16"))
+      if (getOpenCLOptions().isEnabled("cl_khr_fp16") ||
+          (getLangOpts().Half && getLangOpts().NativeHalfType))
         Ty = Context.HalfTy;
       else {
         Diag(Tok.getLocation(), diag::err_half_const_requires_fp16);
@@ -4144,6 +4145,7 @@ static void captureVariablyModifiedType(ASTContext &Context, QualType T,
     case Type::Complex:
     case Type::Vector:
     case Type::ExtVector:
+    case Type::Subword:
     case Type::Record:
     case Type::Enum:
     case Type::Elaborated:
@@ -4714,7 +4716,7 @@ Sema::CreateBuiltinArraySubscriptExpr(Expr *Base, SourceLocation LLoc,
   }
 
   // Perform default conversions.
-  if (!LHSExp->getType()->getAs<VectorType>()) {
+  if (!LHSExp->getType()->getAs<VectorType>() && !LHSExp->getType()->getAs<SubwordType>()) {
     ExprResult Result = DefaultFunctionArrayLvalueConversion(LHSExp);
     if (Result.isInvalid())
       return ExprError();
@@ -4816,6 +4818,29 @@ Sema::CreateBuiltinArraySubscriptExpr(Expr *Base, SourceLocation LLoc,
     BaseExpr = RHSExp;
     IndexExpr = LHSExp;
     ResultType = RHSTy->getAs<PointerType>()->getPointeeType();
+
+  } else if (const SubwordType *SWTy = LHSTy->getAs<SubwordType>()) {
+    BaseExpr = LHSExp;    // Subword: V[123]
+    IndexExpr = RHSExp;
+    // We apply C++ DR1213 to vector subscripting too.
+    if (getLangOpts().CPlusPlus11 && LHSExp->getValueKind() == VK_RValue) {
+      ExprResult Materialized = TemporaryMaterializationConversion(LHSExp);
+      if (Materialized.isInvalid())
+        return ExprError();
+      LHSExp = Materialized.get();
+    }
+    VK = LHSExp->getValueKind();
+    if (VK != VK_RValue)
+      OK = OK_VectorComponent;
+
+    ResultType = SWTy->getBasicType();
+    QualType BaseType = BaseExpr->getType();
+    Qualifiers BaseQuals = BaseType.getQualifiers();
+    Qualifiers MemberQuals = ResultType.getQualifiers();
+    Qualifiers Combined = BaseQuals + MemberQuals;
+    if (Combined != MemberQuals)
+      ResultType = Context.getQualifiedType(ResultType, Combined);
+
   } else {
     return ExprError(Diag(LLoc, diag::err_typecheck_subscript_value)
        << LHSExp->getSourceRange() << RHSExp->getSourceRange());
@@ -5803,6 +5828,43 @@ ExprResult Sema::BuildCallExpr(Scope *Scope, Expr *Fn, SourceLocation LParenLoc,
 
     FunctionDecl *FDecl = dyn_cast<FunctionDecl>(NDecl);
     if (FDecl && FDecl->getBuiltinID()) {
+
+    /* hack for updating the first argument of swarctrl builtin function (ORing input constant with flags defined by swar pragmas in the currect scope block) */
+      if (FDecl->getBuiltinID()==Builtin::BI__builtin_swarctrl) do {
+        unsigned swfl = 0;
+        if (Scope) {
+          DeclContext *dc = Scope->getFnParent()->getEntity();
+          if (dc && dc->swarPragmaLoc[DeclContext::SwarIndices::manualIdx].isValid() &&
+              dc->swarPragmaLoc[DeclContext::SwarIndices::manualIdx]<LParenLoc) {
+            dc->swarPragmaLoc[DeclContext::SwarIndices::manualIdx] = SourceLocation();
+            break;  /* skip automatic swarctrl */
+          }
+          if (dc && dc->swarPragmaLoc[DeclContext::SwarIndices::reduceIdx].isValid() &&
+              dc->swarPragmaLoc[DeclContext::SwarIndices::reduceIdx]<LParenLoc) {
+            dc->swarPragmaLoc[DeclContext::SwarIndices::reduceIdx] = SourceLocation();
+            swfl |= DeclContext::SwarFlags::reduceFlg;
+          }
+          if (dc && dc->swarPragmaLoc[DeclContext::SwarIndices::saturateIdx].isValid() &&
+              dc->swarPragmaLoc[DeclContext::SwarIndices::saturateIdx]<LParenLoc) {
+            dc->swarPragmaLoc[DeclContext::SwarIndices::saturateIdx] = SourceLocation();
+            swfl |= DeclContext::SwarFlags::saturateFlg;
+          }
+          if (dc && dc->swarPragmaLoc[DeclContext::SwarIndices::normalizeIdx].isValid() &&
+              dc->swarPragmaLoc[DeclContext::SwarIndices::normalizeIdx]<LParenLoc) {
+            dc->swarPragmaLoc[DeclContext::SwarIndices::normalizeIdx] = SourceLocation();
+            swfl |= DeclContext::SwarFlags::normalizeFlg;
+          }
+        }
+        llvm::APSInt argval;
+        if (ArgExprs[0]->isIntegerConstantExpr(argval, Context, nullptr, false)) {
+          ConstantExpr *CE = (ConstantExpr *)ArgExprs[0];
+          argval |= llvm::APSInt::get(swfl).extOrTrunc(argval.getBitWidth());
+          // set updated argval value to the first argument - probably there is a better way how to do it
+          CE = ConstantExpr::Create(Context, CE, APValue(argval));
+          ArgExprs[0] = CE;
+        }
+      } while(0);
+
       // Rewrite the function decl for this builtin by replacing parameters
       // with no explicit address space with the address space of the arguments
       // in ArgExprs.
@@ -6734,6 +6796,84 @@ ExprResult Sema::CheckExtVectorCast(SourceRange R, QualType DestTy,
   return prepareVectorSplat(DestTy, CastExpr);
 }
 
+/* Subword */
+static bool breakDownSubwordType(QualType type, unsigned &bwd, unsigned &pck, QualType &btp) {
+  if (const SubwordType *swType = type->getAs<SubwordType>()) {
+    bwd = swType->getBitWidth();
+    pck = swType->getPacking();
+    btp = swType->getBasicType();
+    assert(btp->isScalarType());
+    return true;
+  }
+  // We allow conversion to and from non-vector types, but only if they're integer types (i.e. non-complex, non-pointer scalar types).
+  if (!type->isIntegerType()) return false;
+  bwd = 0;
+  pck = 1;
+  btp = type;
+  return true;
+}
+
+// both subword types have to contain the same number of elements in the basic type (packing) and the same width of elements
+// ... or the destination type has to the same or greater width and the same number of elements
+// ... or the size of
+bool Sema::areCompatibleSubwordTypes(QualType srcTy, QualType destTy) {
+  assert(destTy->isSubwordType() || srcTy->isSubwordType());
+  unsigned srcbitsz, destbitsz;
+  unsigned srcpack, destpack;
+  QualType srcbastp, destbastp;
+  if (!breakDownSubwordType(srcTy, srcbitsz, srcpack, srcbastp)) return false;
+  if (srcbitsz==0) srcbitsz = static_cast<unsigned>(Context.getTypeSize(srcTy));
+  if (!breakDownSubwordType(destTy, destbitsz, destpack, destbastp)) return false;
+  if (destbitsz==0) destbitsz = static_cast<unsigned>(Context.getTypeSize(destTy));
+
+  if (srcpack!=destpack) return false;
+  if (srcbitsz>destbitsz) return false;
+  return true;
+}
+
+bool Sema::CheckSubwordCast(SourceRange R, QualType SubwordTy, QualType Ty,
+                       CastKind &Kind)
+{
+  assert(SubwordTy->isSubwordType() && "Not a subword type!");
+
+  if (Ty->isSubwordType() || Ty->isIntegralType(Context)) {
+    if (!areCompatibleSubwordTypes(Ty, SubwordTy))
+      return Diag(R.getBegin(),
+                  Ty->isSubwordType() ?
+                  diag::err_invalid_conversion_between_subwords :
+                  diag::err_invalid_conversion_between_subword_and_integer)
+        << SubwordTy << Ty << R;
+  } else {
+    return Diag(R.getBegin(),
+                diag::err_invalid_conversion_between_subword_and_scalar)
+      << SubwordTy << Ty << R;
+  }
+
+  Kind = CK_BitCast;
+  return false;
+}
+
+ExprResult Sema::prepareSubwordSplat(QualType SubwordTy, Expr *SplattedExpr)
+{
+  QualType DestBasicTy = SubwordTy->castAs<SubwordType>()->getBasicType();
+  unsigned DestBitWidth = SubwordTy->castAs<SubwordType>()->getBitWidth();
+  QualType SWcanTy = SubwordTy.getCanonicalType();
+
+  if (DestBasicTy == SplattedExpr->getType())
+    return SplattedExpr;
+
+  assert(DestBasicTy->isIntegralOrEnumerationType());
+
+  CastKind CK;
+  ExprResult CastExprRes = SplattedExpr;
+  CK = PrepareScalarCast(CastExprRes, DestBasicTy);
+  if (CastExprRes.isInvalid())
+    return ExprError();
+  SplattedExpr = CastExprRes.get();
+  return ImpCastExprToType(SplattedExpr, DestBasicTy, CK);
+}
+/* Subword - end */
+
 ExprResult
 Sema::ActOnCastExpr(Scope *S, SourceLocation LParenLoc,
                     Declarator &D, ParsedType &Ty,
@@ -6966,6 +7106,15 @@ static bool checkCondition(Sema &S, Expr *Cond, SourceLocation QuestionLoc) {
     return true;
   }
 
+  // daiteq packed half/single
+  if (S.Context.getTargetInfo().getTriple().getArch() == llvm::Triple::sparc &&
+      S.Context.getTargetInfo().getTriple().getVendor() == llvm::Triple::Daiteq) {
+    if (CondTy->isVectorType()) {
+      QualType ElmTy = CondTy->castAs<VectorType>()->getElementType();
+      if (ElmTy->isFloatingType()) return true;
+    }
+  }
+
   // C99 6.5.15p2
   if (CondTy->isScalarType()) return false;
 
@@ -8553,6 +8702,15 @@ Sema::CheckAssignmentConstraints(QualType LHSType, ExprResult &RHS,
     return Compatible;
   }
 
+  if (LHSType->isSubwordType() && RHSType->isIntegerType()) {
+    Kind = CK_IntegralCast;
+    return Compatible;
+  }
+  if (LHSType->isIntegerType() && RHSType->isSubwordType()) { // convert subword to integer ... is used in 'sw_16b2[3] = (sw_b2)2
+    Kind = CK_UserDefinedConversion;
+    return Compatible;
+  }
+
   return Incompatible;
 }
 
@@ -9261,6 +9419,51 @@ QualType Sema::CheckVectorOperands(ExprResult &LHS, ExprResult &RHS,
   return QualType();
 }
 
+// Check operands for operations with subword types
+QualType Sema::CheckSubwordOperands(ExprResult &LHS, ExprResult &RHS,
+                                    SourceLocation Loc, bool IsCompAssign) {
+
+  QualType LHSType = LHS.get()->getType().getUnqualifiedType();
+  QualType RHSType = RHS.get()->getType().getUnqualifiedType();
+
+
+  const SubwordType *LHSSWType;
+  const SubwordType *RHSSWType;
+
+  if (LHSType->isArrayType()) {
+    LHSSWType = Context.getAsArrayType(LHSType)->getElementType()->getAs<SubwordType>();
+  } else {
+    LHSSWType = LHSType->getAs<SubwordType>();
+  }
+
+  if (RHSType->isArrayType()) {
+    RHSSWType = Context.getAsArrayType(RHSType)->getElementType()->getAs<SubwordType>();
+  } else {
+    RHSSWType = RHSType->getAs<SubwordType>();
+  }
+
+  assert(LHSSWType || RHSSWType);
+
+  // If the subword types are identical, return.
+  if (Context.hasSameType(LHSType, RHSType))
+    return LHSType;
+
+  // Combinations of subword types are not allowed now
+  if (LHSSWType->getPacking() == RHSSWType->getPacking()) {
+    if (RHSSWType->getBitWidth()>LHSSWType->getBitWidth())
+      return RHSType;
+    else
+      return LHSType;
+  }
+
+  // Otherwise, use generic diagnostic.
+  Diag(Loc, diag::err_typecheck_subword_length_not_equal)
+        << LHSSWType->getPacking() << RHSSWType->getPacking();
+  return QualType();
+}
+
+
+
 // checkArithmeticNull - Detect when a NULL constant is used improperly in an
 // expression.  These are mainly cases where the null pointer is used as an
 // integer instead of a pointer.
@@ -9366,6 +9569,11 @@ QualType Sema::CheckMultiplyDivideOperands(ExprResult &LHS, ExprResult &RHS,
                                            bool IsCompAssign, bool IsDiv) {
   checkArithmeticNull(*this, LHS, RHS, Loc, /*IsCompare=*/false);
 
+  if (LHS.get()->getType()->isSubwordType() &&
+      RHS.get()->getType()->isSubwordType()) {
+    return CheckSubwordOperands(LHS, RHS, Loc, IsCompAssign);
+  }
+
   if (LHS.get()->getType()->isVectorType() ||
       RHS.get()->getType()->isVectorType())
     return CheckVectorOperands(LHS, RHS, Loc, IsCompAssign,
@@ -9691,6 +9899,24 @@ QualType Sema::CheckAdditionOperands(ExprResult &LHS, ExprResult &RHS,
     return compType;
   }
 
+  if (LHS.get()->getType()->isSubwordType() &&
+      RHS.get()->getType()->isSubwordType()) {
+    QualType compType = CheckSubwordOperands(LHS, RHS, Loc, CompLHSTy);
+    if (CompLHSTy) *CompLHSTy = compType;
+    return compType;
+  }
+
+  if (LHS.get()->getType()->isArrayType() && RHS.get()->getType()->isArrayType()) {
+    const ArrayType *LHSArrTy = Context.getAsArrayType(LHS.get()->getType());
+    const ArrayType *RHSArrTy = Context.getAsArrayType(RHS.get()->getType());
+    if (LHSArrTy->getElementType()->isSubwordType() &&
+        RHSArrTy->getElementType()->isSubwordType()) {
+      QualType compType = CheckSubwordOperands(LHS, RHS, Loc, CompLHSTy);
+      if (CompLHSTy) *CompLHSTy = compType;
+      return compType;
+    }
+  }
+
   QualType compType = UsualArithmeticConversions(
       LHS, RHS, Loc, CompLHSTy ? ACK_CompAssign : ACK_Arithmetic);
   if (LHS.isInvalid() || RHS.isInvalid())
@@ -9786,6 +10012,28 @@ QualType Sema::CheckSubtractionOperands(ExprResult &LHS, ExprResult &RHS,
     return compType;
   }
 
+  // direct subword types
+  if (LHS.get()->getType()->isSubwordType() &&
+      RHS.get()->getType()->isSubwordType()) {
+    theLastSubwordOperation = 2; // subtraction
+    QualType compType = CheckSubwordOperands(LHS, RHS, Loc, CompLHSTy);
+    if (CompLHSTy) *CompLHSTy = compType;
+    return compType;
+  }
+
+  // array of subwords types
+  if (LHS.get()->getType()->isArrayType() && RHS.get()->getType()->isArrayType()) {
+    const ArrayType *LHSArrTy = Context.getAsArrayType(LHS.get()->getType());
+    const ArrayType *RHSArrTy = Context.getAsArrayType(RHS.get()->getType());
+    if (LHSArrTy->getElementType()->isSubwordType() &&
+        RHSArrTy->getElementType()->isSubwordType()) {
+      theLastSubwordOperation = 2; // sub (array)
+      QualType compType = CheckSubwordOperands(LHS, RHS, Loc, CompLHSTy);
+      if (CompLHSTy) *CompLHSTy = compType;
+      return compType;
+    }
+  }
+
   QualType compType = UsualArithmeticConversions(
       LHS, RHS, Loc, CompLHSTy ? ACK_CompAssign : ACK_Arithmetic);
   if (LHS.isInvalid() || RHS.isInvalid())
diff --git a/clang/lib/Sema/SemaInit.cpp b/clang/lib/Sema/SemaInit.cpp
index 94d524a63f5a..20fff1502cb1 100644
--- a/clang/lib/Sema/SemaInit.cpp
+++ b/clang/lib/Sema/SemaInit.cpp
@@ -330,6 +330,13 @@ class InitListChecker {
                        InitListExpr *IList, QualType DeclType, unsigned &Index,
                        InitListExpr *StructuredList,
                        unsigned &StructuredIndex);
+
+  void CheckSubwordType(const InitializedEntity &Entity,
+                        InitListExpr *IList, QualType DeclType,
+                        unsigned &Index,
+                        InitListExpr *StructuredList,
+                        unsigned &StructuredIndex);
+
   void CheckStructUnionTypes(const InitializedEntity &Entity,
                              InitListExpr *IList, QualType DeclType,
                              CXXRecordDecl::base_class_range Bases,
@@ -1111,6 +1118,7 @@ static void warnBracedScalarInit(Sema &S, const InitializedEntity &Entity,
   unsigned DiagID = 0;
 
   switch (Entity.getKind()) {
+  case InitializedEntity::EK_SubWordElement:
   case InitializedEntity::EK_VectorElement:
   case InitializedEntity::EK_ComplexElement:
   case InitializedEntity::EK_ArrayElement:
@@ -1298,7 +1306,11 @@ void InitListChecker::CheckListElementTypes(const InitializedEntity &Entity,
     // Checks for scalar type are sufficient for these types too.
     CheckScalarType(Entity, IList, DeclType, Index, StructuredList,
                     StructuredIndex);
+  } else if (DeclType->isSubwordType()) {
+    CheckSubwordType(Entity, IList, DeclType, Index,
+                    StructuredList, StructuredIndex);
   } else {
+
     if (!VerifyOnly)
       SemaRef.Diag(IList->getBeginLoc(), diag::err_illegal_initializer_type)
           << DeclType;
@@ -1786,6 +1798,48 @@ void InitListChecker::CheckVectorType(const InitializedEntity &Entity,
   }
 }
 
+void InitListChecker::CheckSubwordType(const InitializedEntity &Entity,
+                                      InitListExpr *IList, QualType DeclType,
+                                      unsigned &Index,
+                                      InitListExpr *StructuredList,
+                                      unsigned &StructuredIndex) {
+  const SubwordType *SubT = DeclType->castAs<SubwordType>();
+  unsigned maxElements = SubT->getPacking();
+  unsigned elmBitSize = SubT->getBitWidth();
+  unsigned numEltsInit = 0;
+  QualType basicType = SubT->getBasicType();
+
+  if (maxElements==0) { /* compute number of elements from sizeof(basicType) and elmBits */
+    unsigned basTpSz = SemaRef.Context.getTypeSize(basicType);
+    maxElements = basTpSz/elmBitSize;
+  }
+  if (Index >= IList->getNumInits()) {
+    // Make sure the element type can be value-initialized.
+    CheckEmptyInitializable(
+        InitializedEntity::InitializeElement(SemaRef.Context, 0, Entity),
+        IList->getEndLoc());
+    return;
+  }
+
+  InitializedEntity ElementEntity =
+    InitializedEntity::InitializeElement(SemaRef.Context, 0, Entity);
+
+  // OpenCL initializers allows vectors to be constructed from vectors.
+  for (unsigned i = 0; i < maxElements; ++i) {
+    // Don't attempt to go past the end of the init list
+    if (Index >= IList->getNumInits())
+      break;
+
+    ElementEntity.setElementIndex(Index);
+
+    QualType IType = IList->getInit(Index)->getType();
+    CheckSubElementType(ElementEntity, IList, basicType, Index,  /* basicType should be elementType */
+                        StructuredList, StructuredIndex);
+    ++numEltsInit;
+  }
+}
+
+
 /// Check if the type of a class element has an accessible destructor, and marks
 /// it referenced. Returns true if we shouldn't form a reference to the
 /// destructor.
@@ -3228,6 +3282,9 @@ InitializedEntity::InitializedEntity(ASTContext &Context, unsigned Index,
   } else if (const VectorType *VT = Parent.getType()->getAs<VectorType>()) {
     Kind = EK_VectorElement;
     Type = VT->getElementType();
+  } else if (const SubwordType *SWT = Parent.getType()->getAs<SubwordType>()) {
+    Kind = EK_SubWordElement;
+    Type = SWT->getBasicType();
   } else {
     const ComplexType *CT = Parent.getType()->getAs<ComplexType>();
     assert(CT && "Unexpected type");
@@ -3277,6 +3334,7 @@ DeclarationName InitializedEntity::getName() const {
   case EK_Delegating:
   case EK_ArrayElement:
   case EK_VectorElement:
+  case EK_SubWordElement:
   case EK_ComplexElement:
   case EK_BlockElement:
   case EK_LambdaToBlockConversionBlockElement:
@@ -3308,6 +3366,7 @@ ValueDecl *InitializedEntity::getDecl() const {
   case EK_Delegating:
   case EK_ArrayElement:
   case EK_VectorElement:
+  case EK_SubWordElement:
   case EK_ComplexElement:
   case EK_BlockElement:
   case EK_LambdaToBlockConversionBlockElement:
@@ -3339,6 +3398,7 @@ bool InitializedEntity::allowsNRVO() const {
   case EK_Delegating:
   case EK_ArrayElement:
   case EK_VectorElement:
+  case EK_SubWordElement:
   case EK_ComplexElement:
   case EK_BlockElement:
   case EK_LambdaToBlockConversionBlockElement:
@@ -3374,6 +3434,7 @@ unsigned InitializedEntity::dumpImpl(raw_ostream &OS) const {
   case EK_Delegating: OS << "Delegating"; break;
   case EK_ArrayElement: OS << "ArrayElement " << Index; break;
   case EK_VectorElement: OS << "VectorElement " << Index; break;
+  case EK_SubWordElement: OS << "SubWordElement " << Index; break;
   case EK_ComplexElement: OS << "ComplexElement " << Index; break;
   case EK_BlockElement: OS << "Block"; break;
   case EK_LambdaToBlockConversionBlockElement:
@@ -5963,6 +6024,7 @@ getAssignmentAction(const InitializedEntity &Entity, bool Diagnose = false) {
   case InitializedEntity::EK_Binding:
   case InitializedEntity::EK_ArrayElement:
   case InitializedEntity::EK_VectorElement:
+  case InitializedEntity::EK_SubWordElement:
   case InitializedEntity::EK_ComplexElement:
   case InitializedEntity::EK_BlockElement:
   case InitializedEntity::EK_LambdaToBlockConversionBlockElement:
@@ -5987,6 +6049,7 @@ static bool shouldBindAsTemporary(const InitializedEntity &Entity) {
   case InitializedEntity::EK_Base:
   case InitializedEntity::EK_Delegating:
   case InitializedEntity::EK_VectorElement:
+  case InitializedEntity::EK_SubWordElement:
   case InitializedEntity::EK_ComplexElement:
   case InitializedEntity::EK_Exception:
   case InitializedEntity::EK_BlockElement:
@@ -6016,6 +6079,7 @@ static bool shouldDestroyEntity(const InitializedEntity &Entity) {
     case InitializedEntity::EK_Base:
     case InitializedEntity::EK_Delegating:
     case InitializedEntity::EK_VectorElement:
+    case InitializedEntity::EK_SubWordElement:
     case InitializedEntity::EK_ComplexElement:
     case InitializedEntity::EK_BlockElement:
     case InitializedEntity::EK_LambdaToBlockConversionBlockElement:
@@ -6065,6 +6129,7 @@ static SourceLocation getInitializationLoc(const InitializedEntity &Entity,
   case InitializedEntity::EK_Base:
   case InitializedEntity::EK_Delegating:
   case InitializedEntity::EK_VectorElement:
+  case InitializedEntity::EK_SubWordElement:
   case InitializedEntity::EK_ComplexElement:
   case InitializedEntity::EK_BlockElement:
   case InitializedEntity::EK_LambdaToBlockConversionBlockElement:
@@ -6613,6 +6678,7 @@ static LifetimeResult getEntityLifetime(
   case InitializedEntity::EK_LambdaToBlockConversionBlockElement:
   case InitializedEntity::EK_LambdaCapture:
   case InitializedEntity::EK_VectorElement:
+  case InitializedEntity::EK_SubWordElement:
   case InitializedEntity::EK_ComplexElement:
     return {nullptr, LK_FullExpression};
 
diff --git a/clang/lib/Sema/SemaLookup.cpp b/clang/lib/Sema/SemaLookup.cpp
index 0ed51de0cc13..7782bb3e6444 100644
--- a/clang/lib/Sema/SemaLookup.cpp
+++ b/clang/lib/Sema/SemaLookup.cpp
@@ -2960,6 +2960,7 @@ addAssociatedClassesAndNamespaces(AssociatedLookup &Result, QualType Ty) {
     case Type::Vector:
     case Type::ExtVector:
     case Type::Complex:
+    case Type::Subword:
       break;
 
     // Non-deduced auto types only get here for error cases.
diff --git a/clang/lib/Sema/SemaStmt.cpp b/clang/lib/Sema/SemaStmt.cpp
index 1e7cc503d8c2..2481e2fb1c1e 100644
--- a/clang/lib/Sema/SemaStmt.cpp
+++ b/clang/lib/Sema/SemaStmt.cpp
@@ -42,6 +42,109 @@
 using namespace clang;
 using namespace sema;
 
+
+/* check if @SubStmt is a subword variable or array of subwords (one element or the whole array)
+ * SubStmt is a
+ * - DeclRefExpr - direct reference to variable (return 1)
+ * - ArraySubscriptExpr - indexed element in an array (return 2)
+ * - ArrayType ... - TODO (return 3)
+ * - others (return 0)
+ * outBitWidth - buffer for bitwidth of subword type (or NULL)
+ * isSigned - buffer for flag if subword is signed (or NULL)
+ */
+int Sema::CheckSwarOperandType(Stmt *SubStmt, int *outBitWidth, bool *isSigned)
+{
+  if (!getLangOpts().EnabledSWARdaiteq) return 0; /* skip checking if swar is not required */
+  /* check direct reference to variable */
+  if (const auto *BchDEC = dyn_cast<DeclRefExpr>(SubStmt)) {
+    if (BchDEC->getDecl()->getType().getTypePtr()->isSubwordType()) {
+      const SubwordType *SWTy = BchDEC->getDecl()->getType().getTypePtr()->castAs<SubwordType>();
+      if (outBitWidth) *outBitWidth = SWTy->getBitWidth();
+      if (isSigned) {
+        QualType qtp = SWTy->getBasicType();
+        const Type *btp = qtp.getTypePtrOrNull();
+        if (btp && btp->isSignedIntegerType())
+          *isSigned = true;
+        else
+          *isSigned = false;
+      }
+      return 1;
+    }
+  }
+  /* check array */
+  if (const auto *BchARR = dyn_cast<ArraySubscriptExpr>(SubStmt)) {
+    const Type *PTp = BchARR->getBase()->getType().getTypePtr();
+    if (PTp->isPointerType()) {
+      PTp = PTp->getPointeeType().getTypePtr();
+    }
+    if (PTp->isSubwordType()) {
+      const SubwordType *SWTy = PTp->castAs<SubwordType>();
+      if (outBitWidth) *outBitWidth = SWTy->getBitWidth();
+      if (isSigned) {
+        QualType qtp = SWTy->getBasicType();
+        const Type *btp = qtp.getTypePtrOrNull();
+        if (btp && btp->isSignedIntegerType())
+          *isSigned = true;
+        else
+          *isSigned = false;
+      }
+      return 2;
+    }
+  }
+  return 0;
+}
+
+/* insert automatically generated instruction for SWAR configuration */
+Stmt *Sema::BuildSwarCtrlComp(Stmt *SubStmt, SourceLocation pos, int swop) {
+  StringRef swarctrlName = "__builtin_swarctrl";
+  LookupResult R(*this, &Context.Idents.get(swarctrlName), SubStmt->getBeginLoc(), Sema::LookupOrdinaryName);
+  LookupName(R, TUScope, true);
+  FunctionDecl *SwarCtrl = R.getAsSingle<FunctionDecl>();
+  ExprResult SwarCtrlRef = BuildDeclRefExpr(SwarCtrl, Context.BuiltinFnTy, VK_RValue, SubStmt->getBeginLoc(), nullptr);
+
+  Scope *curscope = getCurScope();
+  if (curscope) {
+    DeclContext *dc = curscope->getFnParent()->getEntity();
+    if (dc && dc->swarPragmaLoc[DeclContext::SwarIndices::manualIdx].isValid() &&
+        dc->swarPragmaLoc[DeclContext::SwarIndices::manualIdx]<SubStmt->getBeginLoc()) {
+      dc->swarPragmaLoc[DeclContext::SwarIndices::manualIdx] = SourceLocation();
+      return SubStmt; /* skip automatic swarctrl */
+    }
+
+    unsigned swfl = 0;
+    if (dc && dc->swarPragmaLoc[DeclContext::SwarIndices::reduceIdx].isValid() &&
+        dc->swarPragmaLoc[DeclContext::SwarIndices::reduceIdx]<SubStmt->getBeginLoc()) {
+      dc->swarPragmaLoc[DeclContext::SwarIndices::reduceIdx] = SourceLocation();
+      swfl |= DeclContext::SwarFlags::reduceFlg;
+    }
+    if (dc && dc->swarPragmaLoc[DeclContext::SwarIndices::saturateIdx].isValid() &&
+        dc->swarPragmaLoc[DeclContext::SwarIndices::saturateIdx]<SubStmt->getBeginLoc()) {
+      dc->swarPragmaLoc[DeclContext::SwarIndices::saturateIdx] = SourceLocation();
+      swfl |= DeclContext::SwarFlags::saturateFlg;
+    }
+    if (dc && dc->swarPragmaLoc[DeclContext::SwarIndices::normalizeIdx].isValid() &&
+        dc->swarPragmaLoc[DeclContext::SwarIndices::normalizeIdx]<SubStmt->getBeginLoc()) {
+      dc->swarPragmaLoc[DeclContext::SwarIndices::normalizeIdx] = SourceLocation();
+      swfl |= DeclContext::SwarFlags::normalizeFlg;
+    }
+    swop |= swfl;
+  } else {
+    //fprintf(stderr, "no scope for swarflags\n");
+  }
+
+
+  llvm::APInt swcval(Context.getTypeSize(Context.IntTy), swop);
+  Expr *CallArgs[] = {
+    IntegerLiteral::Create(Context, swcval, Context.IntTy, SubStmt->getBeginLoc())
+  };
+  ExprResult Call = BuildCallExpr(/*Scope=*/nullptr, SwarCtrlRef.get(),
+                                    SubStmt->getBeginLoc(), CallArgs, SubStmt->getBeginLoc());
+  llvm::SmallVector<Stmt*, 16> nwcpmstmt;
+  nwcpmstmt.push_back(Call.getAs<Stmt>());
+  nwcpmstmt.push_back(SubStmt);
+  return CompoundStmt::Create(Context, nwcpmstmt, SubStmt->getBeginLoc(), SubStmt->getEndLoc());
+}
+
 StmtResult Sema::ActOnExprStmt(ExprResult FE, bool DiscardedValue) {
   if (FE.isInvalid())
     return StmtError();
@@ -417,7 +520,28 @@ StmtResult Sema::ActOnCompoundStmt(SourceLocation L, SourceLocation R,
       DiagnoseEmptyLoopBody(Elts[i], Elts[i + 1]);
   }
 
-  return CompoundStmt::Create(Context, Elts, L, R);
+  StmtResult sr = CompoundStmt::Create(Context, Elts, L, R);
+
+  if (getLangOpts().EnabledSWARdaiteq) {
+/* search SWAR operations and add swarctrl cmd */
+/* skip compound stmt in for loop */
+    Scope *psc = getCurScope()->getParent();
+    if (!((psc->getFlags() & Scope::ScopeFlags::ContinueScope) &&
+        (getCurScope()->getFlags() & Scope::ScopeFlags::CompoundStmtScope)) ) {
+      Stmt::child_iterator schi = sr.get()->child_begin();
+      while (schi!=sr.get()->child_end()) {
+        Stmt *SubStmt = *schi;
+        int swop = CheckSwarOperation(SubStmt);
+
+        if (swop>=0) {
+          *schi = BuildSwarCtrlComp(SubStmt, L, swop);
+        }
+        schi++;
+      }
+    }
+  }
+
+  return sr;
 }
 
 ExprResult
@@ -1760,6 +1884,227 @@ void Sema::CheckBreakContinueBinding(Expr *E) {
   }
 }
 
+// The function tries to find a binary operation with subword arguments in the FOR stmt
+// block - only on the first level of hierarchy.
+int Sema::CheckSwarArrayOperation(Stmt *block) {
+  int swop = -1;
+  bool locswop = false; /* local swarctrl in a loop */
+
+  Stmt::child_iterator chi = block->child_begin();
+  while (chi!=block->child_end()) {
+    Stmt *SubStmt = *chi;
+    if (const auto *BO = dyn_cast<BinaryOperator>(SubStmt)) {
+      if (BO->getOpcode()==BO_Assign ||
+          BO->getOpcode()==BO_MulAssign ||
+          BO->getOpcode()==BO_AddAssign ||
+          BO->getOpcode()==BO_SubAssign) { /* R = XXX , R += XXX , R-= XXX , R *= XXX */
+        int boidx = 0; /* 0 is result, 1 is a part of computation for operator '=' */
+        int swoparrtype = -1;
+        int swoptype = -1;
+        int subwordop = 0;
+        bool subsign = false;
+/* TODO: check if sign/unsign is used correctly */
+        for (Stmt *bchild: SubStmt->children()) {
+          if (boidx==0) {
+            int subtp;
+            bool issign = false;
+            int swt = CheckSwarOperandType(bchild, &subtp, &issign);
+            subsign = issign;
+            if (swt==1) {         // direct var
+              swoptype = subtp;
+            } else if (swt==2) {  // array element
+              swoparrtype = subtp;
+            }
+          }
+          if (boidx==1) {
+            // test for binary operation
+            if (const auto *BchBO = dyn_cast<BinaryOperator>(bchild)) {
+              int lsubtp, rsubtp;
+              int lswt, rswt;
+              bool lsubsig, rsubsig;
+              lswt = CheckSwarOperandType(BchBO->getLHS(), &lsubtp, &lsubsig);
+              rswt = CheckSwarOperandType(BchBO->getRHS(), &rsubtp, &rsubsig);
+              if (lswt>0 && rswt==lswt && lsubsig==rsubsig) {
+                switch (BchBO->getOpcode()) {
+                  case BO_Add: subwordop=1; break;
+                  case BO_Sub: subwordop=2; break;
+                  case BO_Mul: subwordop=3; break;
+                  default:
+                    break;
+                }
+              }
+            }
+          }
+
+          /* block is a swar operation on an array x[i] = a[i] <+/-/*> b[i] */
+          if (swoparrtype>=0 && subwordop) {
+            if (swop>=0) {  /* another swar operation on an array (swarctrl is already before loop) */
+              Diag(SubStmt->getBeginLoc(), diag::warn_subword_crossover);
+              return swop;
+            }
+            if (locswop) {  /* a local swar operation in the loop (swarctrl is already in the loop) */
+              Diag(SubStmt->getBeginLoc(), diag::warn_subword_crossover);
+              return swop;
+            }
+            switch (subwordop) {
+              case 1: swop = SWAR_CTRL_OP_ADD; break; // SWADD
+              case 2: swop = SWAR_CTRL_OP_SUB; break; // SWSUB
+              case 3: swop = SWAR_CTRL_OP_MUL; break; // SWMUL
+            }
+            if (subsign) swop |= SWAR_CTRL_SIGNED;
+            switch ((unsigned)getLangOpts().UseSWARUnit) {
+              default: /* SwarKind::SWAR_Unit_ByType = by variable type */
+                if (swoparrtype==16)
+                  swop |= SWAR_CTRL_AUDIO;
+                else if (swoparrtype==8)
+                  swop |= SWAR_CTRL_VIDEO;
+                else
+                  swop |= SWAR_CTRL_ALU;
+                break;
+              case llvm::SwarKinds::Audio:
+                swop |= SWAR_CTRL_AUDIO;
+                break;
+              case llvm::SwarKinds::Video:
+                swop |= SWAR_CTRL_VIDEO;
+                break;
+              case llvm::SwarKinds::ALU:
+                swop |= SWAR_CTRL_ALU;
+                break;
+            }
+          }
+
+          /* block is a local swar operation on direct subword var x = a <+/-/*> b  */
+          if (swoptype>=0 && subwordop) {
+            if (swop>=0) {  /* swar operation on an array is already in the loop */
+              Diag(SubStmt->getBeginLoc(), diag::warn_subword_crossover);
+              return swop;
+            }
+            locswop = true;
+            /* insert swarctrl builtin function before this SubStmt block */
+            /* create CompoundStmt from calling swarctrl and the original BinaryOperation(subword) */
+            /* exchange the original stmt with the created compound stmt */
+            if (swoptype>0 && subwordop) {
+              int swctrl = 0;
+              switch (subwordop) {
+                case 1: swctrl = SWAR_CTRL_OP_ADD; break; // SWADD
+                case 2: swctrl = SWAR_CTRL_OP_SUB; break; // SWSUB
+                case 3: swctrl = SWAR_CTRL_OP_MUL; break; // SWMUL
+              }
+              if (subsign) swctrl |= SWAR_CTRL_SIGNED;
+              switch ((unsigned)getLangOpts().UseSWARUnit) {
+                default: /* SwarKind::SWAR_Unit_ByType = by variable type */
+                  if (swoptype==16)
+                    swctrl |= SWAR_CTRL_AUDIO;
+                  else if (swoptype==8)
+                    swctrl |= SWAR_CTRL_VIDEO;
+                  else
+                    swctrl |= SWAR_CTRL_ALU;
+                  break;
+                case llvm::SwarKinds::Audio:
+                  swctrl |= SWAR_CTRL_AUDIO;
+                  break;
+                case llvm::SwarKinds::Video:
+                  swctrl |= SWAR_CTRL_VIDEO;
+                  break;
+                case llvm::SwarKinds::ALU:
+                  swctrl |= SWAR_CTRL_ALU;
+                  break;
+              }
+
+              *chi = BuildSwarCtrlComp(SubStmt, SubStmt->getBeginLoc(), swctrl);
+              break;
+            }
+          }
+
+          boidx++;
+        }
+      }
+    }
+    chi++;
+  }
+
+  return swop;
+}
+
+//  The function finds swar operations (without for loops)
+int Sema::CheckSwarOperation(Stmt *sop) {
+  int swop = -1;
+
+  if (const auto *BO = dyn_cast<BinaryOperator>(sop)) {
+    if (BO->getOpcode()==BO_Assign ||
+        BO->getOpcode()==BO_MulAssign ||
+        BO->getOpcode()==BO_AddAssign ||
+        BO->getOpcode()==BO_SubAssign) { /* R = XXX , R += XXX , R-= XXX , R *= XXX */
+      int boidx = 0; /* 0 is result, 1 is part of computation for operator '=' */
+      int swoptype = -1;
+      int subwordop = 0;
+      bool subsign = false;
+
+      for (Stmt *bchild: sop->children()) {
+        if (boidx==0) { // result - is it a subword type ?
+          int swbit;
+          int swtp = CheckSwarOperandType(bchild, &swbit, &subsign);
+          if (swtp==1) // direct variable
+            swoptype = swbit;
+          else if (swtp==2) // array type
+            swoptype = swbit;
+        }
+        if (boidx==1) { // operation + arguments
+          // test for binary operation
+          if (const auto *BchBO = dyn_cast<BinaryOperator>(bchild)) {
+            int lsubtp, rsubtp;
+            int lswt, rswt;
+            bool lsubsig, rsubsig;
+            lswt = CheckSwarOperandType(BchBO->getLHS(), &lsubtp, &lsubsig);
+            rswt = CheckSwarOperandType(BchBO->getRHS(), &rsubtp, &rsubsig);
+            if (lswt>0 && rswt==lswt && lsubsig==rsubsig) {
+              switch (BchBO->getOpcode()) {
+                case BO_Add: subwordop=1; break;
+                case BO_Sub: subwordop=2; break;
+                case BO_Mul: subwordop=3; break;
+                default:
+                  break;
+              }
+            }
+          }
+        }
+
+        /* block is a local swar operation on direct subword var x = a <+/-/*> b  */
+        if (swoptype>0 && subwordop) {
+          switch (subwordop) {
+            case 1: swop = SWAR_CTRL_OP_ADD; break; // SWADD
+            case 2: swop = SWAR_CTRL_OP_SUB; break; // SWSUB
+            case 3: swop = SWAR_CTRL_OP_MUL; break; // SWMUL
+          }
+          if (subsign) swop |= SWAR_CTRL_SIGNED;
+          switch ((unsigned)getLangOpts().UseSWARUnit) {
+            default: /* SwarKind::SWAR_Unit_ByType = by variable type */
+              if (swoptype==16)
+                swop |= SWAR_CTRL_AUDIO;
+              else if (swoptype==8)
+                swop |= SWAR_CTRL_VIDEO;
+              else
+                swop |= SWAR_CTRL_ALU;
+              break;
+            case llvm::SwarKinds::Audio:
+              swop |= SWAR_CTRL_AUDIO;
+              break;
+            case llvm::SwarKinds::Video:
+              swop |= SWAR_CTRL_VIDEO;
+              break;
+            case llvm::SwarKinds::ALU:
+              swop |= SWAR_CTRL_ALU;
+              break;
+          }
+          break;
+        }
+        boidx++;
+      }
+    }
+  }
+  return swop;
+}
+
 StmtResult Sema::ActOnForStmt(SourceLocation ForLoc, SourceLocation LParenLoc,
                               Stmt *First, ConditionResult Second,
                               FullExprArg third, SourceLocation RParenLoc,
@@ -1767,6 +2112,8 @@ StmtResult Sema::ActOnForStmt(SourceLocation ForLoc, SourceLocation LParenLoc,
   if (Second.isInvalid())
     return StmtError();
 
+  theLastSubwordOperation = 0;
+
   if (!getLangOpts().CPlusPlus) {
     if (DeclStmt *DS = dyn_cast_or_null<DeclStmt>(First)) {
       // C99 6.8.5p3: The declaration part of a 'for' statement shall only
@@ -1801,9 +2148,20 @@ StmtResult Sema::ActOnForStmt(SourceLocation ForLoc, SourceLocation LParenLoc,
   if (isa<NullStmt>(Body))
     getCurCompoundScope().setHasEmptyLoopBodies();
 
-  return new (Context)
+  if (!getLangOpts().EnabledSWARdaiteq)
+    return new (Context) ForStmt(Context, First, Second.get().second, Second.get().first, Third,
+                    Body, ForLoc, LParenLoc, RParenLoc);
+
+  int swarop = CheckSwarArrayOperation(Body);
+  inForLoopSubwordChecking = true;
+  Stmt *forres = new (Context)
       ForStmt(Context, First, Second.get().second, Second.get().first, Third,
               Body, ForLoc, LParenLoc, RParenLoc);
+  inForLoopSubwordChecking = false;
+  if (swarop>=0) {
+    forres = BuildSwarCtrlComp(forres, ForLoc, swarop);
+  }
+  return forres;
 }
 
 /// In an Objective C collection iteration statement:
diff --git a/clang/lib/Sema/SemaTemplate.cpp b/clang/lib/Sema/SemaTemplate.cpp
index ade8a5a6ac14..e8c06adf4d07 100755
--- a/clang/lib/Sema/SemaTemplate.cpp
+++ b/clang/lib/Sema/SemaTemplate.cpp
@@ -5586,6 +5586,10 @@ bool UnnamedLocalNoLinkageFinder::VisitExtVectorType(const ExtVectorType* T) {
   return Visit(T->getElementType());
 }
 
+bool UnnamedLocalNoLinkageFinder::VisitSubwordType(const SubwordType* T) {
+  return Visit(T->getBasicType());
+}
+
 bool UnnamedLocalNoLinkageFinder::VisitFunctionProtoType(
                                                   const FunctionProtoType* T) {
   for (const auto &A : T->param_types()) {
diff --git a/clang/lib/Sema/SemaTemplateDeduction.cpp b/clang/lib/Sema/SemaTemplateDeduction.cpp
index 822ea12246a9..f77eac918fbe 100644
--- a/clang/lib/Sema/SemaTemplateDeduction.cpp
+++ b/clang/lib/Sema/SemaTemplateDeduction.cpp
@@ -1498,6 +1498,7 @@ DeduceTemplateArgumentsByTypeMatch(Sema &S,
     case Type::Builtin:
     case Type::VariableArray:
     case Type::Vector:
+    case Type::Subword:
     case Type::FunctionNoProto:
     case Type::Record:
     case Type::Enum:
@@ -5596,6 +5597,12 @@ MarkUsedTemplateParameters(ASTContext &Ctx, QualType T,
     break;
   }
 
+  case Type::Subword:
+    MarkUsedTemplateParameters(Ctx,
+                               cast<SubwordType>(T)->getBasicType(),
+                               OnlyDeduced, Depth, Used);
+    break;
+
   case Type::DependentAddressSpace: {
     const DependentAddressSpaceType *DependentASType =
         cast<DependentAddressSpaceType>(T);
diff --git a/clang/lib/Sema/SemaType.cpp b/clang/lib/Sema/SemaType.cpp
index d77542be53fb..2385ab5fb034 100644
--- a/clang/lib/Sema/SemaType.cpp
+++ b/clang/lib/Sema/SemaType.cpp
@@ -2467,6 +2467,33 @@ QualType Sema::BuildExtVectorType(QualType T, Expr *ArraySize,
   return Context.getDependentSizedExtVectorType(T, ArraySize, AttrLoc);
 }
 
+QualType Sema::BuildSubwordType(QualType BasicType, unsigned BitWidth,
+                                unsigned Packing, SourceLocation AttrLoc) {
+  // The base type must be integer (not Boolean or enumeration) or float, and
+  // can't already be a vector.
+  if (!BasicType->isDependentType() &&
+      (!BasicType->isBuiltinType() || BasicType->isBooleanType() ||
+       (!BasicType->isIntegerType() && !BasicType->isRealFloatingType()))) {
+    Diag(AttrLoc, diag::err_attribute_invalid_vector_type) << BasicType;
+    return QualType();
+  }
+
+  // Bitsize of the basic type
+  unsigned TypeSize = static_cast<unsigned>(Context.getTypeSize(BasicType));
+
+  // !!! PackSize = currently Number of elements in basic type word
+  unsigned maxpack = TypeSize/BitWidth;
+  // length of array of basic type words to cover all subword elements
+  //unsigned arrlen = (ne+(neiow-1))/neiow;
+  if (Packing>maxpack) {
+    Diag(AttrLoc, diag::err_attribute_subword_oversized) << Packing << BitWidth << TypeSize;
+    return QualType();
+  }
+  if (Packing==0) Packing = maxpack;
+
+  return Context.getSubwordType(BasicType, BitWidth, Packing);
+}
+
 bool Sema::CheckFunctionReturnType(QualType T, SourceLocation Loc) {
   if (T->isArrayType() || T->isFunctionType()) {
     Diag(Loc, diag::err_func_returning_array_function)
@@ -7359,6 +7386,77 @@ static void HandleNeonVectorTypeAttr(QualType &CurType, const ParsedAttr &Attr,
   CurType = S.Context.getVectorType(CurType, numElts, VecKind);
 }
 
+static void HandleSubwordAttr(QualType &CurType, const ParsedAttr &Attr,
+                              Sema &S) {
+  if (!S.getLangOpts().EnabledSWARdaiteq) {
+    S.Diag(Attr.getLoc(), diag::err_attribute_subword_disabled);
+    return;
+  }
+// check the attribute arguments.
+  if (Attr.getNumArgs() < 1 || Attr.getNumArgs() > 2) {
+    S.Diag(Attr.getLoc(), diag::err_attribute_wrong_number_arguments)
+      << Attr.getAttrName()->getName() << 1;
+    return;
+  }
+
+// BitWidth - the first mandatory argument
+  Expr *BitSizeExpr;
+  // Special case where the argument is a template id.
+  if (Attr.isArgIdent(0)) {
+    CXXScopeSpec SS;
+    SourceLocation TemplateKWLoc;
+    UnqualifiedId Id;
+    Id.setIdentifier(Attr.getArgAsIdent(0)->Ident, Attr.getLoc());
+    ExprResult Size = S.ActOnIdExpression(S.getCurScope(), SS, TemplateKWLoc,
+                                          Id, false, false);
+    if (Size.isInvalid())
+      return;
+    BitSizeExpr = Size.get();
+  } else {
+    BitSizeExpr = Attr.getArgAsExpr(0);
+  }
+  llvm::APSInt BitWidth(8);
+  if (!BitSizeExpr->isIntegerConstantExpr(BitWidth, S.Context)) {
+    S.Diag(Attr.getLoc(), diag::err_attribute_argument_type)
+        << "subword BS " << Attr.getAttrName()->getName() << BitSizeExpr->getSourceRange();
+    return;
+  }
+  unsigned BWidth = static_cast<unsigned>(BitWidth.getZExtValue());
+
+// Packing - the second optional argument
+  unsigned packing = 0; /* if the attribute has only one argument (bitwidth), packing is 0 by default for automatically filling the whole basic type */
+  if (Attr.getNumArgs()==2) {
+    Expr *PackingExpr;
+    // Special case where the argument is a template id.
+    if (Attr.isArgIdent(1)) {
+      CXXScopeSpec SS;
+      SourceLocation TemplateKWLoc;
+      UnqualifiedId Id;
+      Id.setIdentifier(Attr.getArgAsIdent(1)->Ident, Attr.getLoc());
+      ExprResult PckSz = S.ActOnIdExpression(S.getCurScope(), SS, TemplateKWLoc,
+                                              Id, false, false);
+      if (PckSz.isInvalid()) return;
+      PackingExpr = PckSz.get();
+    } else {
+      PackingExpr = Attr.getArgAsExpr(1);
+    }
+    llvm::APSInt Packing(32);
+    if (!PackingExpr->isIntegerConstantExpr(Packing, S.Context)) {
+      S.Diag(Attr.getLoc(), diag::err_attribute_argument_type)
+          << "subword Pack " << Attr.getAttrName()->getName() << PackingExpr->getSourceRange();
+      return;
+    }
+    packing = static_cast<unsigned>(Packing.getZExtValue());
+  }
+
+  QualType T = S.BuildSubwordType(CurType, BWidth, packing, Attr.getLoc());
+  if (!T.isNull())
+    CurType = T;
+  else
+    Attr.setInvalid();
+//  S.Diag(Attr.getLoc(), diag::err_attribute_unsupported) << Attr.getName();
+}
+
 /// Handle OpenCL Access Qualifier Attribute.
 static void HandleOpenCLAccessAttr(QualType &CurType, const ParsedAttr &Attr,
                                    Sema &S) {
@@ -7533,6 +7631,12 @@ static void processTypeAttrs(TypeProcessingState &state, QualType &type,
       HandleExtVectorTypeAttr(type, attr, state.getSema());
       attr.setUsedAsTypeAttr();
       break;
+
+    case ParsedAttr::AT_Subword:
+      HandleSubwordAttr(type, attr, state.getSema());
+      attr.setUsedAsTypeAttr();
+      break;
+
     case ParsedAttr::AT_NeonVectorType:
       HandleNeonVectorTypeAttr(type, attr, state.getSema(),
                                VectorType::NeonVector);
diff --git a/clang/lib/Sema/TreeTransform.h b/clang/lib/Sema/TreeTransform.h
index eb5646729899..64d9343dd56f 100644
--- a/clang/lib/Sema/TreeTransform.h
+++ b/clang/lib/Sema/TreeTransform.h
@@ -868,6 +868,14 @@ public:
                                               Expr *SizeExpr,
                                               SourceLocation AttributeLoc);
 
+  /// Build a new subword type given the element type, element bitwidth and
+  /// packed number of elements.
+  ///
+  /// By default, performs semantic analysis when building the vector type.
+  /// Subclasses may override this routine to provide different behavior.
+  QualType RebuildSubwordType(QualType ElementType, unsigned BitWidth,
+                              unsigned Packing, SourceLocation AttributeLoc);
+
   /// Build a new DependentAddressSpaceType or return the pointee
   /// type variable with the correct address space (retrieved from
   /// AddrSpaceExpr) applied to it. The former will be returned in cases
@@ -5108,6 +5116,31 @@ QualType TreeTransform<Derived>::TransformExtVectorType(TypeLocBuilder &TLB,
   return Result;
 }
 
+template<typename Derived>
+QualType TreeTransform<Derived>::TransformSubwordType(TypeLocBuilder &TLB,
+                                                      SubwordTypeLoc TL) {
+  const SubwordType *T = TL.getTypePtr();
+  QualType BasicType = getDerived().TransformType(T->getBasicType());
+  if (BasicType.isNull())
+    return QualType();
+
+  QualType Result = TL.getType();
+  if (getDerived().AlwaysRebuild() ||
+      BasicType != T->getBasicType()) {
+    Result = getDerived().RebuildSubwordType(BasicType,
+                                              T->getBitWidth(),
+                                              T->getPacking(),
+                                               /*FIXME*/ SourceLocation());
+    if (Result.isNull())
+      return QualType();
+  }
+
+  SubwordTypeLoc NewTL = TLB.push<SubwordTypeLoc>(Result);
+  NewTL.setNameLoc(TL.getNameLoc());
+
+  return Result;
+}
+
 template <typename Derived>
 ParmVarDecl *TreeTransform<Derived>::TransformFunctionTypeParam(
     ParmVarDecl *OldParm, int indexAdjustment, Optional<unsigned> NumExpansions,
@@ -13084,6 +13117,12 @@ TreeTransform<Derived>::RebuildDependentSizedExtVectorType(QualType ElementType,
   return SemaRef.BuildExtVectorType(ElementType, SizeExpr, AttributeLoc);
 }
 
+template<typename Derived>
+QualType TreeTransform<Derived>::RebuildSubwordType(QualType BasicType,
+        unsigned BitWidth, unsigned Packing, SourceLocation AttributeLoc) {
+  return SemaRef.BuildSubwordType(BasicType, BitWidth, Packing, AttributeLoc);
+}
+
 template<typename Derived>
 QualType TreeTransform<Derived>::RebuildFunctionProtoType(
     QualType T,
diff --git a/clang/lib/Serialization/ASTReader.cpp b/clang/lib/Serialization/ASTReader.cpp
index a9f433b50074..3d1dbcb08fe7 100644
--- a/clang/lib/Serialization/ASTReader.cpp
+++ b/clang/lib/Serialization/ASTReader.cpp
@@ -6522,6 +6522,10 @@ void TypeLocReader::VisitExtVectorTypeLoc(ExtVectorTypeLoc TL) {
   TL.setNameLoc(readSourceLocation());
 }
 
+void TypeLocReader::VisitSubwordTypeLoc(SubwordTypeLoc TL) {
+  TL.setNameLoc(readSourceLocation());
+}
+
 void TypeLocReader::VisitFunctionTypeLoc(FunctionTypeLoc TL) {
   TL.setLocalRangeBegin(readSourceLocation());
   TL.setLParenLoc(readSourceLocation());
diff --git a/clang/lib/Serialization/ASTWriter.cpp b/clang/lib/Serialization/ASTWriter.cpp
index aebdfa907066..3468ccc3d109 100644
--- a/clang/lib/Serialization/ASTWriter.cpp
+++ b/clang/lib/Serialization/ASTWriter.cpp
@@ -288,6 +288,10 @@ void TypeLocWriter::VisitExtVectorTypeLoc(ExtVectorTypeLoc TL) {
   Record.AddSourceLocation(TL.getNameLoc());
 }
 
+void TypeLocWriter::VisitSubwordTypeLoc(SubwordTypeLoc TL) {
+  Record.AddSourceLocation(TL.getNameLoc());
+}
+
 void TypeLocWriter::VisitFunctionTypeLoc(FunctionTypeLoc TL) {
   Record.AddSourceLocation(TL.getLocalRangeBegin());
   Record.AddSourceLocation(TL.getLParenLoc());
@@ -800,6 +804,9 @@ void ASTWriter::WriteBlockInfoBlock() {
   RECORD(TYPE_VARIABLE_ARRAY);
   RECORD(TYPE_VECTOR);
   RECORD(TYPE_EXT_VECTOR);
+
+  RECORD(TYPE_SUBWORD);
+
   RECORD(TYPE_FUNCTION_NO_PROTO);
   RECORD(TYPE_FUNCTION_PROTO);
   RECORD(TYPE_TYPEDEF);
diff --git a/clang/tools/libclang/CIndex.cpp b/clang/tools/libclang/CIndex.cpp
index 94084e169faf..c2264f43b0bc 100644
--- a/clang/tools/libclang/CIndex.cpp
+++ b/clang/tools/libclang/CIndex.cpp
@@ -1800,6 +1800,8 @@ DEFAULT_TYPELOC_IMPL(SubstTemplateTypeParm, Type)
 DEFAULT_TYPELOC_IMPL(SubstTemplateTypeParmPack, Type)
 DEFAULT_TYPELOC_IMPL(Auto, Type)
 
+DEFAULT_TYPELOC_IMPL(Subword, Type)
+
 bool CursorVisitor::VisitCXXRecordDecl(CXXRecordDecl *D) {
   // Visit the nested-name-specifier, if present.
   if (NestedNameSpecifierLoc QualifierLoc = D->getQualifierLoc())
diff --git a/llvm/include/llvm/ADT/Triple.h b/llvm/include/llvm/ADT/Triple.h
index b9485e81feb7..d8f09e1e76d6 100644
--- a/llvm/include/llvm/ADT/Triple.h
+++ b/llvm/include/llvm/ADT/Triple.h
@@ -149,7 +149,8 @@ public:
     Mesa,
     SUSE,
     OpenEmbedded,
-    LastVendorType = OpenEmbedded
+    Daiteq,
+    LastVendorType = Daiteq
   };
   enum OSType {
     UnknownOS,
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
index d81a4a8fd43f..2668acc0b914 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -180,7 +180,10 @@ public:
   }
 
   TypeSize getScalarValueSizeInBits() const {
-    return getValueType().getScalarType().getSizeInBits();
+    if (getValueType().isSubwordVector())
+      return getValueType().getSizeInBits();
+    else
+      return getValueType().getScalarType().getSizeInBits();
   }
 
   // Forwarding methods - These forward to the corresponding methods in SDNode.
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 6c8895e4f9df..01399b506754 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -1230,6 +1230,11 @@ public:
 
     if (auto *VTy = dyn_cast<VectorType>(Ty)) {
       Type *EltTy = VTy->getElementType();
+
+      if (VTy->isSubword()) {
+        return EVT::getEVT(Ty, false);
+      }
+
       // Lower vectors of pointers to native pointer types.
       if (auto *PTy = dyn_cast<PointerType>(EltTy)) {
         EVT PointerTy(getPointerTy(DL, PTy->getAddressSpace()));
@@ -1248,6 +1253,9 @@ public:
     if (PointerType *PTy = dyn_cast<PointerType>(Ty))
       return getPointerMemTy(DL, PTy->getAddressSpace());
     else if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
+      if (VTy->isSubword()) {
+        return EVT::getEVT(VTy->getBasicType(), false);
+      }
       Type *Elm = VTy->getElementType();
       if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
         EVT PointerTy(getPointerMemTy(DL, PT->getAddressSpace()));
diff --git a/llvm/include/llvm/CodeGen/ValueTypes.h b/llvm/include/llvm/CodeGen/ValueTypes.h
index bcf417762920..8b7c87150df2 100644
--- a/llvm/include/llvm/CodeGen/ValueTypes.h
+++ b/llvm/include/llvm/CodeGen/ValueTypes.h
@@ -36,10 +36,13 @@ namespace llvm {
     MVT V = MVT::INVALID_SIMPLE_VALUE_TYPE;
     Type *LLVMTy = nullptr;
 
+    unsigned packing = 0; /* number of all elements in the vector, num.of words<basic_type> = roundup(subNumElements/(elem_per_basic_type)) */
+
   public:
     constexpr EVT() = default;
     constexpr EVT(MVT::SimpleValueType SVT) : V(SVT) {}
     constexpr EVT(MVT S) : V(S) {}
+//    constexpr EVT(MVT S, unsigned subElms, bool ) : V(S), subwordElements(subElms) {}
 
     bool operator==(EVT VT) const {
       return !(*this != VT);
@@ -49,6 +52,8 @@ namespace llvm {
         return true;
       if (V.SimpleTy == MVT::INVALID_SIMPLE_VALUE_TYPE)
         return LLVMTy != VT.LLVMTy;
+      if (V.isSubwordVector())
+        return packing != VT.packing;
       return false;
     }
 
@@ -90,6 +95,15 @@ namespace llvm {
       return getExtendedVectorVT(Context, VT, EC.Min);
     }
 
+/* returns EVT Type which represents LLVM::Type (Subword vector). The output type is a vector type of vsXp32 */
+/* ElementSize is one from 1/2/3/4/8/16, Packing is a number of elements packed in each basic types */
+    static EVT getSubwordVT(LLVMContext &Context, MVT subwordType, unsigned Packing) {
+      assert ((subwordType.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE) && "getSubwordVT for unsupported basic type");
+      EVT extVT = EVT(subwordType);
+      extVT.packing = Packing;
+      return extVT;
+    }
+
     /// Return a vector with the same number of elements as this vector, but
     /// with the element type converted to an integer type with the same
     /// bitwidth.
@@ -102,8 +116,20 @@ namespace llvm {
       MVT EltTy = getSimpleVT().getVectorElementType();
       unsigned BitWidth = EltTy.getSizeInBits();
       MVT IntTy = MVT::getIntegerVT(BitWidth);
-      MVT VecTy = MVT::getVectorVT(IntTy, getVectorNumElements(),
-                                   isScalableVector());
+      MVT VecTy;
+      if (getSimpleVT().isSubwordVector()) {
+        /* subword vector has <packedElements> in one element of the integer <basictype>, but we
+           can have an integer vector with the same size in the memory or with the same number of elements !!!
+           This function creates an integer vector with the same size in the memory (not the same number of elements).
+        */
+//        unsigned npack = getSimpleVT().getVectorNumElements(); // number of elements (1/2/3/4/8/16) packed in the basic type (i32)
+//        npack = (subwordElements+npack-1)/npack;  // number of words<basic type> for saving all subword elements in the vector
+//        VecTy = MVT::getVectorVT(IntTy,npack, false);
+        VecTy = MVT::getIntegerVT(getSimpleVT().getSizeInBits()); /* now only i32 is a basic type */
+      } else
+        VecTy = MVT::getVectorVT(IntTy, getVectorNumElements(),
+                                 isScalableVector());
+
       assert(VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE &&
              "Simple vector VT not representable by simple integer vector VT!");
       return VecTy;
@@ -152,6 +178,10 @@ namespace llvm {
       return isSimple() ? V.isVector() : isExtendedVector();
     }
 
+    bool isSubwordVector() const {
+      return isSimple() ? V.isSubwordVector() : isExtendedSubword();
+    }
+
     /// Return true if this is a vector type where the runtime
     /// length is machine dependent
     bool isScalableVector() const {
@@ -260,6 +290,7 @@ namespace llvm {
     /// If this is a vector type, return the element type, otherwise return
     /// this.
     EVT getScalarType() const {
+      if (isSubwordVector()) return EVT(MVT::i32); //getBasicType(); /* basic type is only i32 now */
       return isVector() ? getVectorElementType() : *this;
     }
 
@@ -273,7 +304,7 @@ namespace llvm {
 
     /// Given a vector type, return the number of elements it contains.
     unsigned getVectorNumElements() const {
-      assert(isVector() && "Invalid vector type!");
+      assert((isVector() || isSubwordVector()) && "Invalid vector type!");
       if (isSimple())
         return V.getVectorNumElements();
       return getExtendedVectorNumElements();
@@ -434,6 +465,7 @@ namespace llvm {
     bool isExtendedInteger() const LLVM_READONLY;
     bool isExtendedScalarInteger() const LLVM_READONLY;
     bool isExtendedVector() const LLVM_READONLY;
+    bool isExtendedSubword() const LLVM_READONLY;
     bool isExtended16BitVector() const LLVM_READONLY;
     bool isExtended32BitVector() const LLVM_READONLY;
     bool isExtended64BitVector() const LLVM_READONLY;
diff --git a/llvm/include/llvm/CodeGen/ValueTypes.td b/llvm/include/llvm/CodeGen/ValueTypes.td
index 16df565bc8b8..029872520350 100644
--- a/llvm/include/llvm/CodeGen/ValueTypes.td
+++ b/llvm/include/llvm/CodeGen/ValueTypes.td
@@ -161,11 +161,18 @@ def nxv2f64  : ValueType<128, 127>; // n x  2 x f64 vector value
 def nxv4f64  : ValueType<256, 128>; // n x  4 x f64 vector value
 def nxv8f64  : ValueType<512, 129>; // n x  8 x f64 vector value
 
-def x86mmx : ValueType<64 , 130>;   // X86 MMX value
-def FlagVT : ValueType<0  , 131>;   // Pre-RA sched glue
-def isVoid : ValueType<0  , 132>;   // Produces no value
-def untyped: ValueType<8  , 133>;   // Produces an untyped value
-def exnref: ValueType<0, 134>;      // WebAssembly's exnref type
+def vs1p32   : ValueType<32 , 130>; // p x 32 x i1 vector value
+def vs2p32   : ValueType<32 , 131>; // p x 16 x i2 vector value
+def vs3p32   : ValueType<32 , 132>; // p x 10 x i3 vector value
+def vs4p32   : ValueType<32 , 133>; // p x  8 x i4 vector value
+def vs8p32   : ValueType<32 , 134>; // p x  4 x i8 vector value
+def vs16p32  : ValueType<32 , 135>; // p x  2 x i16 vector value
+
+def x86mmx : ValueType<64 , 136>;   // X86 MMX value
+def FlagVT : ValueType<0  , 137>;   // Pre-RA sched glue
+def isVoid : ValueType<0  , 138>;   // Produces no value
+def untyped: ValueType<8  , 139>;   // Produces an untyped value
+def exnref: ValueType<0, 140>;      // WebAssembly's exnref type
 def token  : ValueType<0  , 248>;   // TokenTy
 def MetadataVT: ValueType<0, 249>;  // Metadata
 
diff --git a/llvm/include/llvm/IR/DIBuilder.h b/llvm/include/llvm/IR/DIBuilder.h
index f7c242554f6a..4ba08af2ae50 100644
--- a/llvm/include/llvm/IR/DIBuilder.h
+++ b/llvm/include/llvm/IR/DIBuilder.h
@@ -492,6 +492,14 @@ namespace llvm {
     DICompositeType *createVectorType(uint64_t Size, uint32_t AlignInBits,
                                       DIType *Ty, DINodeArray Subscripts);
 
+    /// Create debugging information entry for a subword type.
+    /// \param ESize        Element size.
+    /// \param ECount       Number of elements.
+    /// \param Ty           Basic type.
+    /// \param Subscripts   Subscripts.
+    DICompositeType *createSubwordType(uint64_t ESize, uint64_t ECount,
+                                      DIType *Ty, DINodeArray Subscripts);
+
     /// Create debugging information entry for an
     /// enumeration.
     /// \param Scope          Scope in which this enumeration is defined.
diff --git a/llvm/include/llvm/IR/DebugInfoFlags.def b/llvm/include/llvm/IR/DebugInfoFlags.def
index df375b6c68e8..3d0b3fcfad25 100644
--- a/llvm/include/llvm/IR/DebugInfoFlags.def
+++ b/llvm/include/llvm/IR/DebugInfoFlags.def
@@ -58,7 +58,7 @@ HANDLE_DI_FLAG((1 << 26), NonTrivial)
 HANDLE_DI_FLAG((1 << 27), BigEndian)
 HANDLE_DI_FLAG((1 << 28), LittleEndian)
 HANDLE_DI_FLAG((1 << 29), AllCallsDescribed)
-
+HANDLE_DI_FLAG((1 << 30), Subword)
 // To avoid needing a dedicated value for IndirectVirtualBase, we use
 // the bitwise or of Virtual and FwdDecl, which does not otherwise
 // make sense for inheritance.
@@ -67,7 +67,7 @@ HANDLE_DI_FLAG((1 << 2) | (1 << 5), IndirectVirtualBase)
 #ifdef DI_FLAG_LARGEST_NEEDED
 // intended to be used with ADT/BitmaskEnum.h
 // NOTE: always must be equal to largest flag, check this when adding new flag
-HANDLE_DI_FLAG((1 << 29), Largest)
+HANDLE_DI_FLAG((1 << 30), Largest)
 #undef DI_FLAG_LARGEST_NEEDED
 #endif
 
diff --git a/llvm/include/llvm/IR/DebugInfoMetadata.h b/llvm/include/llvm/IR/DebugInfoMetadata.h
index d6bfe504dd94..356bca8c51f9 100644
--- a/llvm/include/llvm/IR/DebugInfoMetadata.h
+++ b/llvm/include/llvm/IR/DebugInfoMetadata.h
@@ -657,6 +657,7 @@ public:
     return getFlags() & FlagObjcClassComplete;
   }
   bool isVector() const { return getFlags() & FlagVector; }
+  bool isSubword() const { return getFlags() & FlagSubword; }
   bool isBitField() const { return getFlags() & FlagBitField; }
   bool isStaticMember() const { return getFlags() & FlagStaticMember; }
   bool isLValueReference() const { return getFlags() & FlagLValueReference; }
diff --git a/llvm/include/llvm/IR/DerivedTypes.h b/llvm/include/llvm/IR/DerivedTypes.h
index 20097ef3f31a..ebb34418bb12 100644
--- a/llvm/include/llvm/IR/DerivedTypes.h
+++ b/llvm/include/llvm/IR/DerivedTypes.h
@@ -442,15 +442,30 @@ class VectorType : public SequentialType {
   /// <4 x i32>          - a vector containing 4 i32s
   /// <vscale x 4 x i32> - a vector containing an unknown integer multiple
   ///                      of 4 i32s
+  ///
+  /// <subword 'PckSz' x 'eltTy' in 'BasTp' > - a vector of subword elements
 
   VectorType(Type *ElType, unsigned NumEl, bool Scalable = false);
   VectorType(Type *ElType, ElementCount EC);
 
+  // This special constructor is only for subword type
+  VectorType(Type *BasType, Type *ElType, unsigned Packing, bool IsSigned);
+
   // If true, the total number of elements is an unknown multiple of the
   // minimum 'NumElements' from SequentialType. Otherwise the total number
   // of elements is exactly equal to 'NumElements'.
   bool Scalable;
 
+  // Subword is true, if the vector contains a subword type. The subword type
+  // is described by Type of element, Basic Type and number of elements packed
+  // in the basic type (if Packing is 0, the maximum elements is used, i.e.
+  // packing = size(basicType)/size(elementType). Packing is saved in NumElements.
+  bool Subword;
+  Type *BasicType; /* place for Basic type, Element Type is in nested SequentialType::ContainedType (use getElementType() ) */
+  Type *SubwordSubTys[2]; /* 0: elementType, 1: basicType */
+  bool signedBasicType; /* hold if the Basic Type is signed */
+
+
 public:
   VectorType(const VectorType &) = delete;
   VectorType &operator=(const VectorType &) = delete;
@@ -462,6 +477,13 @@ public:
     return VectorType::get(ElementType, {NumElements, Scalable});
   }
 
+  // For Subword type
+  static VectorType *get(Type *BasicType, Type *ElementType, unsigned Packing, bool IsSigned);
+  uint64_t getPackSize() const { return getNumElements(); }
+  Type *getBasicType() const { return BasicType; }
+  bool getBasicSign() const { return signedBasicType; }
+
+
   /// This static method gets a VectorType with the same number of elements as
   /// the input type, and the element type is an integer type of the same width
   /// as the input element type.
@@ -551,6 +573,11 @@ public:
     return Scalable;
   }
 
+  bool isSubword() const {
+    if (getBasicType()==NULL || getElementType()==NULL) return false;
+    return Subword;
+  }
+
   /// Return the minimum number of bits in the Vector type.
   /// Returns zero when the vector is a vector of pointers.
   unsigned getBitWidth() const {
@@ -571,6 +598,11 @@ bool Type::getVectorIsScalable() const {
   return cast<VectorType>(this)->isScalable();
 }
 
+bool Type::getVectorIsSubword() const {
+  if (!this->isVectorTy()) return false;
+  return cast<VectorType>(this)->isSubword();
+}
+
 ElementCount Type::getVectorElementCount() const {
   return cast<VectorType>(this)->getElementCount();
 }
diff --git a/llvm/include/llvm/IR/InstrTypes.h b/llvm/include/llvm/IR/InstrTypes.h
index 49f8ffddcabf..fc6d78477917 100644
--- a/llvm/include/llvm/IR/InstrTypes.h
+++ b/llvm/include/llvm/IR/InstrTypes.h
@@ -188,6 +188,8 @@ public:
 class BinaryOperator : public Instruction {
   void AssertOK();
 
+  bool SubwordOp;
+
 protected:
   BinaryOperator(BinaryOps iType, Value *S1, Value *S2, Type *Ty,
                  const Twine &Name, Instruction *InsertBefore);
@@ -205,6 +207,8 @@ public:
     return User::operator new(s, 2);
   }
 
+  bool isSubwordOp(void) const { return SubwordOp; }
+
   /// Transparently provide more efficient getOperand methods.
   DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
 
diff --git a/llvm/include/llvm/IR/Instructions.h b/llvm/include/llvm/IR/Instructions.h
index b73d5274238c..09a6aaca787e 100644
--- a/llvm/include/llvm/IR/Instructions.h
+++ b/llvm/include/llvm/IR/Instructions.h
@@ -1159,12 +1159,16 @@ class ICmpInst: public CmpInst {
   void AssertOK() {
     assert(isIntPredicate() &&
            "Invalid ICmp predicate value");
-    assert(getOperand(0)->getType() == getOperand(1)->getType() &&
-          "Both operands to ICmp instruction are not of the same type!");
+//    assert(getOperand(0)->getType() == getOperand(1)->getType() &&
+//          "Both operands to ICmp instruction are not of the same type!");
     // Check that the operands are the right type
     assert((getOperand(0)->getType()->isIntOrIntVectorTy() ||
             getOperand(0)->getType()->isPtrOrPtrVectorTy()) &&
            "Invalid operand types for ICmp instruction");
+
+    assert((getOperand(1)->getType()->isIntOrIntVectorTy() ||
+            getOperand(1)->getType()->isPtrOrPtrVectorTy()) &&
+           "Invalid second operand types for ICmp instruction");
   }
 
 protected:
diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td
index 90cac9759c76..54dff08b2ed1 100644
--- a/llvm/include/llvm/IR/Intrinsics.td
+++ b/llvm/include/llvm/IR/Intrinsics.td
@@ -287,6 +287,15 @@ def llvm_v8f64_ty      : LLVMType<v8f64>;    //  8 x double
 
 def llvm_vararg_ty     : LLVMType<isVoid>;   // this means vararg here
 
+
+def llvm_vs1p32_ty         : LLVMType<vs1p32>;
+def llvm_vs2p32_ty         : LLVMType<vs2p32>;
+def llvm_vs3p32_ty         : LLVMType<vs3p32>;
+def llvm_vs4p32_ty         : LLVMType<vs4p32>;
+def llvm_vs8p32_ty         : LLVMType<vs8p32>;
+def llvm_vs16p32_ty        : LLVMType<vs16p32>;
+
+
 //===----------------------------------------------------------------------===//
 // Intrinsic Definitions.
 //===----------------------------------------------------------------------===//
diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.def b/llvm/include/llvm/IR/RuntimeLibcalls.def
index 5e17ed641846..6f57a49649a2 100644
--- a/llvm/include/llvm/IR/RuntimeLibcalls.def
+++ b/llvm/include/llvm/IR/RuntimeLibcalls.def
@@ -87,111 +87,152 @@ HANDLE_LIBCALL(CTLZ_I64, "__clzdi2")
 HANDLE_LIBCALL(CTLZ_I128, "__clzti2")
 
 // Floating-point
+HANDLE_LIBCALL(NEG_F16, "__neghf2")
+HANDLE_LIBCALL(NEG_F32, "__negsf2")
+HANDLE_LIBCALL(NEG_F64, "__negdf2")
+HANDLE_LIBCALL(ABS_F16, "fabsh")
+HANDLE_LIBCALL(ABS_F32, "fabsf")
+HANDLE_LIBCALL(ABS_F64, "fabs")
+
+
+HANDLE_LIBCALL(ADD_V2F16, "__addphf3")
+HANDLE_LIBCALL(ADD_V2F32, "__addpsf3")
+HANDLE_LIBCALL(SUB_V2F16, "__subphf3")
+HANDLE_LIBCALL(SUB_V2F32, "__subpsf3")
+HANDLE_LIBCALL(MUL_V2F16, "__mulphf3")
+HANDLE_LIBCALL(MUL_V2F32, "__mulpsf3")
+HANDLE_LIBCALL(DIV_V2F16, "__divphf3")
+HANDLE_LIBCALL(DIV_V2F32, "__divpsf3")
+HANDLE_LIBCALL(SQRT_V2F16, "sqrtph")
+HANDLE_LIBCALL(SQRT_V2F32, "sqrtps")
+
+HANDLE_LIBCALL(ADD_F16, "__addhf3")
 HANDLE_LIBCALL(ADD_F32, "__addsf3")
 HANDLE_LIBCALL(ADD_F64, "__adddf3")
 HANDLE_LIBCALL(ADD_F80, "__addxf3")
 HANDLE_LIBCALL(ADD_F128, "__addtf3")
 HANDLE_LIBCALL(ADD_PPCF128, "__gcc_qadd")
+HANDLE_LIBCALL(SUB_F16, "__subhf3")
 HANDLE_LIBCALL(SUB_F32, "__subsf3")
 HANDLE_LIBCALL(SUB_F64, "__subdf3")
 HANDLE_LIBCALL(SUB_F80, "__subxf3")
 HANDLE_LIBCALL(SUB_F128, "__subtf3")
 HANDLE_LIBCALL(SUB_PPCF128, "__gcc_qsub")
+HANDLE_LIBCALL(MUL_F16, "__mulhf3")
 HANDLE_LIBCALL(MUL_F32, "__mulsf3")
 HANDLE_LIBCALL(MUL_F64, "__muldf3")
 HANDLE_LIBCALL(MUL_F80, "__mulxf3")
 HANDLE_LIBCALL(MUL_F128, "__multf3")
 HANDLE_LIBCALL(MUL_PPCF128, "__gcc_qmul")
+HANDLE_LIBCALL(DIV_F16, "__divhf3")
 HANDLE_LIBCALL(DIV_F32, "__divsf3")
 HANDLE_LIBCALL(DIV_F64, "__divdf3")
 HANDLE_LIBCALL(DIV_F80, "__divxf3")
 HANDLE_LIBCALL(DIV_F128, "__divtf3")
 HANDLE_LIBCALL(DIV_PPCF128, "__gcc_qdiv")
+HANDLE_LIBCALL(REM_F16, "fmodh")
 HANDLE_LIBCALL(REM_F32, "fmodf")
 HANDLE_LIBCALL(REM_F64, "fmod")
 HANDLE_LIBCALL(REM_F80, "fmodl")
 HANDLE_LIBCALL(REM_F128, "fmodl")
 HANDLE_LIBCALL(REM_PPCF128, "fmodl")
+HANDLE_LIBCALL(FMA_F16, "fmah")
 HANDLE_LIBCALL(FMA_F32, "fmaf")
 HANDLE_LIBCALL(FMA_F64, "fma")
 HANDLE_LIBCALL(FMA_F80, "fmal")
 HANDLE_LIBCALL(FMA_F128, "fmal")
 HANDLE_LIBCALL(FMA_PPCF128, "fmal")
+HANDLE_LIBCALL(POWI_F16, "__powihf2")
 HANDLE_LIBCALL(POWI_F32, "__powisf2")
 HANDLE_LIBCALL(POWI_F64, "__powidf2")
 HANDLE_LIBCALL(POWI_F80, "__powixf2")
 HANDLE_LIBCALL(POWI_F128, "__powitf2")
 HANDLE_LIBCALL(POWI_PPCF128, "__powitf2")
+HANDLE_LIBCALL(SQRT_F16, "sqrth")
 HANDLE_LIBCALL(SQRT_F32, "sqrtf")
 HANDLE_LIBCALL(SQRT_F64, "sqrt")
 HANDLE_LIBCALL(SQRT_F80, "sqrtl")
 HANDLE_LIBCALL(SQRT_F128, "sqrtl")
 HANDLE_LIBCALL(SQRT_PPCF128, "sqrtl")
+HANDLE_LIBCALL(CBRT_F16, "cbrth")
 HANDLE_LIBCALL(CBRT_F32, "cbrtf")
 HANDLE_LIBCALL(CBRT_F64, "cbrt")
 HANDLE_LIBCALL(CBRT_F80, "cbrtl")
 HANDLE_LIBCALL(CBRT_F128, "cbrtl")
 HANDLE_LIBCALL(CBRT_PPCF128, "cbrtl")
+HANDLE_LIBCALL(LOG_F16, "logh")
 HANDLE_LIBCALL(LOG_F32, "logf")
 HANDLE_LIBCALL(LOG_F64, "log")
 HANDLE_LIBCALL(LOG_F80, "logl")
 HANDLE_LIBCALL(LOG_F128, "logl")
 HANDLE_LIBCALL(LOG_PPCF128, "logl")
+HANDLE_LIBCALL(LOG_FINITE_F16, "__logh_finite")
 HANDLE_LIBCALL(LOG_FINITE_F32, "__logf_finite")
 HANDLE_LIBCALL(LOG_FINITE_F64, "__log_finite")
 HANDLE_LIBCALL(LOG_FINITE_F80, "__logl_finite")
 HANDLE_LIBCALL(LOG_FINITE_F128, "__logl_finite")
 HANDLE_LIBCALL(LOG_FINITE_PPCF128, "__logl_finite")
+HANDLE_LIBCALL(LOG2_F16, "log2h")
 HANDLE_LIBCALL(LOG2_F32, "log2f")
 HANDLE_LIBCALL(LOG2_F64, "log2")
 HANDLE_LIBCALL(LOG2_F80, "log2l")
 HANDLE_LIBCALL(LOG2_F128, "log2l")
 HANDLE_LIBCALL(LOG2_PPCF128, "log2l")
+HANDLE_LIBCALL(LOG2_FINITE_F16, "__log2h_finite")
 HANDLE_LIBCALL(LOG2_FINITE_F32, "__log2f_finite")
 HANDLE_LIBCALL(LOG2_FINITE_F64, "__log2_finite")
 HANDLE_LIBCALL(LOG2_FINITE_F80, "__log2l_finite")
 HANDLE_LIBCALL(LOG2_FINITE_F128, "__log2l_finite")
 HANDLE_LIBCALL(LOG2_FINITE_PPCF128, "__log2l_finite")
+HANDLE_LIBCALL(LOG10_F16, "log10h")
 HANDLE_LIBCALL(LOG10_F32, "log10f")
 HANDLE_LIBCALL(LOG10_F64, "log10")
 HANDLE_LIBCALL(LOG10_F80, "log10l")
 HANDLE_LIBCALL(LOG10_F128, "log10l")
 HANDLE_LIBCALL(LOG10_PPCF128, "log10l")
+HANDLE_LIBCALL(LOG10_FINITE_F16, "__log10h_finite")
 HANDLE_LIBCALL(LOG10_FINITE_F32, "__log10f_finite")
 HANDLE_LIBCALL(LOG10_FINITE_F64, "__log10_finite")
 HANDLE_LIBCALL(LOG10_FINITE_F80, "__log10l_finite")
 HANDLE_LIBCALL(LOG10_FINITE_F128, "__log10l_finite")
 HANDLE_LIBCALL(LOG10_FINITE_PPCF128, "__log10l_finite")
+HANDLE_LIBCALL(EXP_F16, "exph")
 HANDLE_LIBCALL(EXP_F32, "expf")
 HANDLE_LIBCALL(EXP_F64, "exp")
 HANDLE_LIBCALL(EXP_F80, "expl")
 HANDLE_LIBCALL(EXP_F128, "expl")
 HANDLE_LIBCALL(EXP_PPCF128, "expl")
+HANDLE_LIBCALL(EXP_FINITE_F16, "__exph_finite")
 HANDLE_LIBCALL(EXP_FINITE_F32, "__expf_finite")
 HANDLE_LIBCALL(EXP_FINITE_F64, "__exp_finite")
 HANDLE_LIBCALL(EXP_FINITE_F80, "__expl_finite")
 HANDLE_LIBCALL(EXP_FINITE_F128, "__expl_finite")
 HANDLE_LIBCALL(EXP_FINITE_PPCF128, "__expl_finite")
+HANDLE_LIBCALL(EXP2_F16, "exp2h")
 HANDLE_LIBCALL(EXP2_F32, "exp2f")
 HANDLE_LIBCALL(EXP2_F64, "exp2")
 HANDLE_LIBCALL(EXP2_F80, "exp2l")
 HANDLE_LIBCALL(EXP2_F128, "exp2l")
 HANDLE_LIBCALL(EXP2_PPCF128, "exp2l")
+HANDLE_LIBCALL(EXP2_FINITE_F16, "__exp2h_finite")
 HANDLE_LIBCALL(EXP2_FINITE_F32, "__exp2f_finite")
 HANDLE_LIBCALL(EXP2_FINITE_F64, "__exp2_finite")
 HANDLE_LIBCALL(EXP2_FINITE_F80, "__exp2l_finite")
 HANDLE_LIBCALL(EXP2_FINITE_F128, "__exp2l_finite")
 HANDLE_LIBCALL(EXP2_FINITE_PPCF128, "__exp2l_finite")
+HANDLE_LIBCALL(SIN_F16, "sinf16")
 HANDLE_LIBCALL(SIN_F32, "sinf")
 HANDLE_LIBCALL(SIN_F64, "sin")
 HANDLE_LIBCALL(SIN_F80, "sinl")
 HANDLE_LIBCALL(SIN_F128, "sinl")
 HANDLE_LIBCALL(SIN_PPCF128, "sinl")
+HANDLE_LIBCALL(COS_F16, "cosf16")
 HANDLE_LIBCALL(COS_F32, "cosf")
 HANDLE_LIBCALL(COS_F64, "cos")
 HANDLE_LIBCALL(COS_F80, "cosl")
 HANDLE_LIBCALL(COS_F128, "cosl")
 HANDLE_LIBCALL(COS_PPCF128, "cosl")
+HANDLE_LIBCALL(SINCOS_F16, nullptr)
 HANDLE_LIBCALL(SINCOS_F32, nullptr)
 HANDLE_LIBCALL(SINCOS_F64, nullptr)
 HANDLE_LIBCALL(SINCOS_F80, nullptr)
@@ -199,76 +240,91 @@ HANDLE_LIBCALL(SINCOS_F128, nullptr)
 HANDLE_LIBCALL(SINCOS_PPCF128, nullptr)
 HANDLE_LIBCALL(SINCOS_STRET_F32, nullptr)
 HANDLE_LIBCALL(SINCOS_STRET_F64, nullptr)
+HANDLE_LIBCALL(POW_F16, "powh")
 HANDLE_LIBCALL(POW_F32, "powf")
 HANDLE_LIBCALL(POW_F64, "pow")
 HANDLE_LIBCALL(POW_F80, "powl")
 HANDLE_LIBCALL(POW_F128, "powl")
 HANDLE_LIBCALL(POW_PPCF128, "powl")
+HANDLE_LIBCALL(POW_FINITE_F16, "__powh_finite")
 HANDLE_LIBCALL(POW_FINITE_F32, "__powf_finite")
 HANDLE_LIBCALL(POW_FINITE_F64, "__pow_finite")
 HANDLE_LIBCALL(POW_FINITE_F80, "__powl_finite")
 HANDLE_LIBCALL(POW_FINITE_F128, "__powl_finite")
 HANDLE_LIBCALL(POW_FINITE_PPCF128, "__powl_finite")
+HANDLE_LIBCALL(CEIL_F16, "ceilh")
 HANDLE_LIBCALL(CEIL_F32, "ceilf")
 HANDLE_LIBCALL(CEIL_F64, "ceil")
 HANDLE_LIBCALL(CEIL_F80, "ceill")
 HANDLE_LIBCALL(CEIL_F128, "ceill")
 HANDLE_LIBCALL(CEIL_PPCF128, "ceill")
+HANDLE_LIBCALL(TRUNC_F16, "trunch")
 HANDLE_LIBCALL(TRUNC_F32, "truncf")
 HANDLE_LIBCALL(TRUNC_F64, "trunc")
 HANDLE_LIBCALL(TRUNC_F80, "truncl")
 HANDLE_LIBCALL(TRUNC_F128, "truncl")
 HANDLE_LIBCALL(TRUNC_PPCF128, "truncl")
+HANDLE_LIBCALL(RINT_F16, "rinth")
 HANDLE_LIBCALL(RINT_F32, "rintf")
 HANDLE_LIBCALL(RINT_F64, "rint")
 HANDLE_LIBCALL(RINT_F80, "rintl")
 HANDLE_LIBCALL(RINT_F128, "rintl")
 HANDLE_LIBCALL(RINT_PPCF128, "rintl")
+HANDLE_LIBCALL(NEARBYINT_F16, "nearbyinth")
 HANDLE_LIBCALL(NEARBYINT_F32, "nearbyintf")
 HANDLE_LIBCALL(NEARBYINT_F64, "nearbyint")
 HANDLE_LIBCALL(NEARBYINT_F80, "nearbyintl")
 HANDLE_LIBCALL(NEARBYINT_F128, "nearbyintl")
 HANDLE_LIBCALL(NEARBYINT_PPCF128, "nearbyintl")
+HANDLE_LIBCALL(ROUND_F16, "roundh")
 HANDLE_LIBCALL(ROUND_F32, "roundf")
 HANDLE_LIBCALL(ROUND_F64, "round")
 HANDLE_LIBCALL(ROUND_F80, "roundl")
 HANDLE_LIBCALL(ROUND_F128, "roundl")
 HANDLE_LIBCALL(ROUND_PPCF128, "roundl")
+HANDLE_LIBCALL(FLOOR_F16, "floorh")
 HANDLE_LIBCALL(FLOOR_F32, "floorf")
 HANDLE_LIBCALL(FLOOR_F64, "floor")
 HANDLE_LIBCALL(FLOOR_F80, "floorl")
 HANDLE_LIBCALL(FLOOR_F128, "floorl")
 HANDLE_LIBCALL(FLOOR_PPCF128, "floorl")
+HANDLE_LIBCALL(COPYSIGN_F16, "copysignh")
 HANDLE_LIBCALL(COPYSIGN_F32, "copysignf")
 HANDLE_LIBCALL(COPYSIGN_F64, "copysign")
 HANDLE_LIBCALL(COPYSIGN_F80, "copysignl")
 HANDLE_LIBCALL(COPYSIGN_F128, "copysignl")
 HANDLE_LIBCALL(COPYSIGN_PPCF128, "copysignl")
+HANDLE_LIBCALL(FMIN_F16, "fminh")
 HANDLE_LIBCALL(FMIN_F32, "fminf")
 HANDLE_LIBCALL(FMIN_F64, "fmin")
 HANDLE_LIBCALL(FMIN_F80, "fminl")
 HANDLE_LIBCALL(FMIN_F128, "fminl")
 HANDLE_LIBCALL(FMIN_PPCF128, "fminl")
+HANDLE_LIBCALL(FMAX_F16, "fmaxh")
 HANDLE_LIBCALL(FMAX_F32, "fmaxf")
 HANDLE_LIBCALL(FMAX_F64, "fmax")
 HANDLE_LIBCALL(FMAX_F80, "fmaxl")
 HANDLE_LIBCALL(FMAX_F128, "fmaxl")
 HANDLE_LIBCALL(FMAX_PPCF128, "fmaxl")
+HANDLE_LIBCALL(LROUND_F16, "lroundh")
 HANDLE_LIBCALL(LROUND_F32, "lroundf")
 HANDLE_LIBCALL(LROUND_F64, "lround")
 HANDLE_LIBCALL(LROUND_F80, "lroundl")
 HANDLE_LIBCALL(LROUND_F128, "lroundl")
 HANDLE_LIBCALL(LROUND_PPCF128, "lroundl")
+HANDLE_LIBCALL(LLROUND_F16, "llroundh")
 HANDLE_LIBCALL(LLROUND_F32, "llroundf")
 HANDLE_LIBCALL(LLROUND_F64, "llround")
 HANDLE_LIBCALL(LLROUND_F80, "llroundl")
 HANDLE_LIBCALL(LLROUND_F128, "llroundl")
 HANDLE_LIBCALL(LLROUND_PPCF128, "llroundl")
+HANDLE_LIBCALL(LRINT_F16, "lrinth")
 HANDLE_LIBCALL(LRINT_F32, "lrintf")
 HANDLE_LIBCALL(LRINT_F64, "lrint")
 HANDLE_LIBCALL(LRINT_F80, "lrintl")
 HANDLE_LIBCALL(LRINT_F128, "lrintl")
 HANDLE_LIBCALL(LRINT_PPCF128, "lrintl")
+HANDLE_LIBCALL(LLRINT_F16, "llrinth")
 HANDLE_LIBCALL(LLRINT_F32, "llrintf")
 HANDLE_LIBCALL(LLRINT_F64, "llrint")
 HANDLE_LIBCALL(LLRINT_F80, "llrintl")
@@ -283,6 +339,7 @@ HANDLE_LIBCALL(FPEXT_F64_F128, "__extenddftf2")
 HANDLE_LIBCALL(FPEXT_F32_F128, "__extendsftf2")
 HANDLE_LIBCALL(FPEXT_F32_F64, "__extendsfdf2")
 HANDLE_LIBCALL(FPEXT_F16_F32, "__gnu_h2f_ieee")
+HANDLE_LIBCALL(FPEXT_F16_F64, "__extendhfdf2")
 HANDLE_LIBCALL(FPROUND_F32_F16, "__gnu_f2h_ieee")
 HANDLE_LIBCALL(FPROUND_F64_F16, "__truncdfhf2")
 HANDLE_LIBCALL(FPROUND_F80_F16, "__truncxfhf2")
@@ -296,6 +353,7 @@ HANDLE_LIBCALL(FPROUND_F80_F64, "__truncxfdf2")
 HANDLE_LIBCALL(FPROUND_F128_F64, "__trunctfdf2")
 HANDLE_LIBCALL(FPROUND_PPCF128_F64, "__gcc_qtod")
 HANDLE_LIBCALL(FPROUND_F128_F80, "__trunctfxf2")
+HANDLE_LIBCALL(FPTOSINT_F16_I32, "__fixhfsi")
 HANDLE_LIBCALL(FPTOSINT_F32_I32, "__fixsfsi")
 HANDLE_LIBCALL(FPTOSINT_F32_I64, "__fixsfdi")
 HANDLE_LIBCALL(FPTOSINT_F32_I128, "__fixsfti")
@@ -311,6 +369,7 @@ HANDLE_LIBCALL(FPTOSINT_F128_I128, "__fixtfti")
 HANDLE_LIBCALL(FPTOSINT_PPCF128_I32, "__gcc_qtou")
 HANDLE_LIBCALL(FPTOSINT_PPCF128_I64, "__fixtfdi")
 HANDLE_LIBCALL(FPTOSINT_PPCF128_I128, "__fixtfti")
+HANDLE_LIBCALL(FPTOUINT_F16_I32, "__fixunshfsi")
 HANDLE_LIBCALL(FPTOUINT_F32_I32, "__fixunssfsi")
 HANDLE_LIBCALL(FPTOUINT_F32_I64, "__fixunssfdi")
 HANDLE_LIBCALL(FPTOUINT_F32_I128, "__fixunssfti")
@@ -326,6 +385,7 @@ HANDLE_LIBCALL(FPTOUINT_F128_I128, "__fixunstfti")
 HANDLE_LIBCALL(FPTOUINT_PPCF128_I32, "__fixunstfsi")
 HANDLE_LIBCALL(FPTOUINT_PPCF128_I64, "__fixunstfdi")
 HANDLE_LIBCALL(FPTOUINT_PPCF128_I128, "__fixunstfti")
+HANDLE_LIBCALL(SINTTOFP_I32_F16, "__floatsihf")
 HANDLE_LIBCALL(SINTTOFP_I32_F32, "__floatsisf")
 HANDLE_LIBCALL(SINTTOFP_I32_F64, "__floatsidf")
 HANDLE_LIBCALL(SINTTOFP_I32_F80, "__floatsixf")
@@ -341,6 +401,7 @@ HANDLE_LIBCALL(SINTTOFP_I128_F64, "__floattidf")
 HANDLE_LIBCALL(SINTTOFP_I128_F80, "__floattixf")
 HANDLE_LIBCALL(SINTTOFP_I128_F128, "__floattitf")
 HANDLE_LIBCALL(SINTTOFP_I128_PPCF128, "__floattitf")
+HANDLE_LIBCALL(UINTTOFP_I32_F16, "__floatunsihf")
 HANDLE_LIBCALL(UINTTOFP_I32_F32, "__floatunsisf")
 HANDLE_LIBCALL(UINTTOFP_I32_F64, "__floatunsidf")
 HANDLE_LIBCALL(UINTTOFP_I32_F80, "__floatunsixf")
@@ -358,34 +419,42 @@ HANDLE_LIBCALL(UINTTOFP_I128_F128, "__floatuntitf")
 HANDLE_LIBCALL(UINTTOFP_I128_PPCF128, "__floatuntitf")
 
 // Comparison
+HANDLE_LIBCALL(OEQ_F16, "__eqhf2")
 HANDLE_LIBCALL(OEQ_F32, "__eqsf2")
 HANDLE_LIBCALL(OEQ_F64, "__eqdf2")
 HANDLE_LIBCALL(OEQ_F128, "__eqtf2")
 HANDLE_LIBCALL(OEQ_PPCF128, "__gcc_qeq")
+HANDLE_LIBCALL(UNE_F16, "__nehf2")
 HANDLE_LIBCALL(UNE_F32, "__nesf2")
 HANDLE_LIBCALL(UNE_F64, "__nedf2")
 HANDLE_LIBCALL(UNE_F128, "__netf2")
 HANDLE_LIBCALL(UNE_PPCF128, "__gcc_qne")
+HANDLE_LIBCALL(OGE_F16, "__gehf2")
 HANDLE_LIBCALL(OGE_F32, "__gesf2")
 HANDLE_LIBCALL(OGE_F64, "__gedf2")
 HANDLE_LIBCALL(OGE_F128, "__getf2")
 HANDLE_LIBCALL(OGE_PPCF128, "__gcc_qge")
+HANDLE_LIBCALL(OLT_F16, "__lthf2")
 HANDLE_LIBCALL(OLT_F32, "__ltsf2")
 HANDLE_LIBCALL(OLT_F64, "__ltdf2")
 HANDLE_LIBCALL(OLT_F128, "__lttf2")
 HANDLE_LIBCALL(OLT_PPCF128, "__gcc_qlt")
+HANDLE_LIBCALL(OLE_F16, "__lehf2")
 HANDLE_LIBCALL(OLE_F32, "__lesf2")
 HANDLE_LIBCALL(OLE_F64, "__ledf2")
 HANDLE_LIBCALL(OLE_F128, "__letf2")
 HANDLE_LIBCALL(OLE_PPCF128, "__gcc_qle")
+HANDLE_LIBCALL(OGT_F16, "__gthf2")
 HANDLE_LIBCALL(OGT_F32, "__gtsf2")
 HANDLE_LIBCALL(OGT_F64, "__gtdf2")
 HANDLE_LIBCALL(OGT_F128, "__gttf2")
 HANDLE_LIBCALL(OGT_PPCF128, "__gcc_qgt")
+HANDLE_LIBCALL(UO_F16, "__unordhf2")
 HANDLE_LIBCALL(UO_F32, "__unordsf2")
 HANDLE_LIBCALL(UO_F64, "__unorddf2")
 HANDLE_LIBCALL(UO_F128, "__unordtf2")
 HANDLE_LIBCALL(UO_PPCF128, "__gcc_qunord")
+HANDLE_LIBCALL(O_F16, "__unordhf2")
 HANDLE_LIBCALL(O_F32, "__unordsf2")
 HANDLE_LIBCALL(O_F64, "__unorddf2")
 HANDLE_LIBCALL(O_F128, "__unordtf2")
diff --git a/llvm/include/llvm/IR/Type.h b/llvm/include/llvm/IR/Type.h
index d0961dac833d..7ef02515930d 100644
--- a/llvm/include/llvm/IR/Type.h
+++ b/llvm/include/llvm/IR/Type.h
@@ -383,6 +383,8 @@ public:
     return ContainedTys[0];
   }
 
+  inline bool getVectorIsSubword() const;
+
   /// Given an integer or vector type, change the lane bitwidth to NewBitwidth,
   /// whilst keeping the old number of lanes.
   inline Type *getWithNewBitWidth(unsigned NewBitWidth) const;
diff --git a/llvm/include/llvm/Support/MachineValueType.h b/llvm/include/llvm/Support/MachineValueType.h
index 26b45a602763..da87dfb12187 100644
--- a/llvm/include/llvm/Support/MachineValueType.h
+++ b/llvm/include/llvm/Support/MachineValueType.h
@@ -204,23 +204,40 @@ namespace llvm {
       FIRST_SCALABLE_VECTOR_VALUETYPE = nxv1i1,
       LAST_SCALABLE_VECTOR_VALUETYPE = nxv8f64,
 
+      vs1p32        =  130,   // subword 1bit packed in i32 (normally 32 x  1b in i32)
+      vs2p32        =  131,   // subword 2bit packed in i32 (normally 16 x  2b in i32)
+      vs3p32        =  132,   // subword 3bit packed in i32 (normally 10 x  3b in i32)
+      vs4p32        =  133,   // subword 4bit packed in i32 (normally  8 x  4b in i32)
+      vs8p32        =  134,   // subword 8bit packed in i32 (normally  4 x  8b in i32)
+      vs16p32       =  135,   // subword 16bit packed in i32 (normally 2 x 16b in i32)
+
+      FIRST_SUBWORD_VECTOR_VALUETYPE = vs1p32,
+      LAST_SUBWORD_VECTOR_VALUETYPE = vs16p32,
+
       FIRST_VECTOR_VALUETYPE = v1i1,
-      LAST_VECTOR_VALUETYPE  = nxv8f64,
+      LAST_VECTOR_VALUETYPE  = vs16p32, //nxv8f64,
+
+//      i2             =  136,
+//      i3             =  137,
+//      i4             =  138,
+
+//      FIRST_ADD_INTEGER_VALUETYPE = i2,
+//      LAST_ADD_INTEGER_VALUETYPE = i4,
 
-      x86mmx         =  130,   // This is an X86 MMX value
+      x86mmx         =  136,   // This is an X86 MMX value
 
-      Glue           =  131,   // This glues nodes together during pre-RA sched
+      Glue           =  137,   // This glues nodes together during pre-RA sched
 
-      isVoid         =  132,   // This has no value
+      isVoid         =  138,   // This has no value
 
-      Untyped        =  133,   // This value takes a register, but has
+      Untyped        =  139,   // This value takes a register, but has
                                // unspecified type.  The register class
                                // will be determined by the opcode.
 
-      exnref         =  134,   // WebAssembly's exnref type
+      exnref         =  140,   // WebAssembly's exnref type
 
       FIRST_VALUETYPE = 1,     // This is always the beginning of the list.
-      LAST_VALUETYPE =  135,   // This always remains at the end of the list.
+      LAST_VALUETYPE =  141,   // This always remains at the end of the list.
 
       // This is the current maximum for LAST_VALUETYPE.
       // MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors
@@ -297,7 +314,12 @@ namespace llvm {
               (SimpleTy >= MVT::FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE &&
                SimpleTy <= MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE) ||
               (SimpleTy >= MVT::FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE &&
-               SimpleTy <= MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE));
+               SimpleTy <= MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE) ||
+              (SimpleTy >= MVT::FIRST_SUBWORD_VECTOR_VALUETYPE &&
+               SimpleTy <= MVT::LAST_SUBWORD_VECTOR_VALUETYPE) // ||
+//              (SimpleTy >= MVT::FIRST_ADD_INTEGER_VALUETYPE &&
+//               SimpleTy <= MVT::LAST_ADD_INTEGER_VALUETYPE)
+               );
     }
 
     /// Return true if this is an integer, not including vectors.
@@ -319,9 +341,16 @@ namespace llvm {
               SimpleTy <= MVT::LAST_SCALABLE_VECTOR_VALUETYPE);
     }
 
+    bool isSubwordVector() const {
+      return (SimpleTy >= MVT::FIRST_SUBWORD_VECTOR_VALUETYPE &&
+              SimpleTy <= MVT::LAST_SUBWORD_VECTOR_VALUETYPE);
+    }
+
     bool isFixedLengthVector() const {
-      return (SimpleTy >= MVT::FIRST_FIXEDLEN_VECTOR_VALUETYPE &&
-              SimpleTy <= MVT::LAST_FIXEDLEN_VECTOR_VALUETYPE);
+      return ((SimpleTy >= MVT::FIRST_FIXEDLEN_VECTOR_VALUETYPE &&
+              SimpleTy <= MVT::LAST_FIXEDLEN_VECTOR_VALUETYPE) ||
+              (SimpleTy >= MVT::FIRST_SUBWORD_VECTOR_VALUETYPE &&
+              SimpleTy <= MVT::LAST_SUBWORD_VECTOR_VALUETYPE));
     }
 
     /// Return true if this is a 16-bit vector type.
@@ -334,7 +363,9 @@ namespace llvm {
     bool is32BitVector() const {
       return (SimpleTy == MVT::v32i1 || SimpleTy == MVT::v4i8  ||
               SimpleTy == MVT::v2i16 || SimpleTy == MVT::v1i32 ||
-              SimpleTy == MVT::v2f16 || SimpleTy == MVT::v1f32);
+              SimpleTy == MVT::v2f16 || SimpleTy == MVT::v1f32 ||
+              (SimpleTy >= MVT::FIRST_SUBWORD_VECTOR_VALUETYPE &&   /* all subword types are i32 vectors in this version */
+               SimpleTy <= MVT::LAST_SUBWORD_VECTOR_VALUETYPE));
     }
 
     /// Return true if this is a 64-bit vector type.
@@ -541,6 +572,15 @@ namespace llvm {
       case nxv2f64:
       case nxv4f64:
       case nxv8f64: return f64;
+
+      /* subword types returns element type as normal integer i32 */
+      case vs1p32:
+      case vs2p32:
+      case vs3p32:
+      case vs4p32:
+      case vs8p32:
+      case vs16p32: return i32;
+
       }
     }
 
@@ -581,7 +621,8 @@ namespace llvm {
       case nxv32i8:
       case nxv32i16:
       case nxv32i32:
-      case nxv32i64: return 32;
+      case nxv32i64:
+        return 32;
       case v16i1:
       case v16i8:
       case v16i16:
@@ -594,7 +635,8 @@ namespace llvm {
       case nxv16i16:
       case nxv16i32:
       case nxv16i64:
-      case nxv16f32: return 16;
+      case nxv16f32:
+        return 16;
       case v8i1:
       case v8i8:
       case v8i16:
@@ -610,7 +652,8 @@ namespace llvm {
       case nxv8i64:
       case nxv8f16:
       case nxv8f32:
-      case nxv8f64: return 8;
+      case nxv8f64:
+        return 8;
       case v5i32:
       case v5f32: return 5;
       case v4i1:
@@ -628,7 +671,8 @@ namespace llvm {
       case nxv4i64:
       case nxv4f16:
       case nxv4f32:
-      case nxv4f64: return 4;
+      case nxv4f64:
+        return 4;
       case v3i16:
       case v3i32:
       case v3f16:
@@ -648,7 +692,8 @@ namespace llvm {
       case nxv2i64:
       case nxv2f16:
       case nxv2f32:
-      case nxv2f64: return 2;
+      case nxv2f64:
+        return 2;
       case v1i1:
       case v1i8:
       case v1i16:
@@ -664,10 +709,22 @@ namespace llvm {
       case nxv1i64:
       case nxv1f32:
       case nxv1f64: return 1;
+
+      case vs1p32:  return 32;
+      case vs2p32:  return 16;
+      case vs3p32:  return 10;
+      case vs4p32:  return 8;
+      case vs8p32:  return 4;
+      case vs16p32: return 2;
+
       }
     }
 
     ElementCount getVectorElementCount() const {
+      // TODO ? check if the function always returns required value for subword types (maybe in some cases it should return 32 instead of number of elements in the basic type
+      if (isSubwordVector()) {
+        return { getVectorNumElements(), false };  /* it depends on all elements are required or elements packed in the basic type */
+      }
       return { getVectorNumElements(), isScalableVector() };
     }
 
@@ -729,6 +786,14 @@ namespace llvm {
       case nxv1i32:
       case nxv2f16:
       case nxv1f32: return TypeSize::Scalable(32);
+
+      case vs1p32:
+      case vs2p32:
+      case vs3p32:
+      case vs4p32:
+      case vs8p32:
+      case vs16p32:  return TypeSize::Fixed(32);
+
       case v3i16:
       case v3f16: return TypeSize::Fixed(48);
       case x86mmx:
@@ -828,6 +893,18 @@ namespace llvm {
       }
     }
 
+    TypeSize getSubwordSizeInBits() const {
+      switch (SimpleTy) {
+      default:      return TypeSize::Fixed(0);
+      case vs1p32:  return TypeSize::Fixed(1);
+      case vs2p32:  return TypeSize::Fixed(2);
+      case vs3p32:  return TypeSize::Fixed(3);
+      case vs4p32:  return TypeSize::Fixed(4);
+      case vs8p32:  return TypeSize::Fixed(8);
+      case vs16p32: return TypeSize::Fixed(16);
+      }
+    }
+
     TypeSize getScalarSizeInBits() const {
       return getScalarType().getSizeInBits();
     }
@@ -1081,6 +1158,19 @@ namespace llvm {
       return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE);
     }
 
+    /* subword vector specified by basic type (i32), ElementSize = 1/2/3/4/8/16 */
+    static MVT getSubwordVT(MVT baseVT, unsigned ElemSize) {
+      if ((baseVT.SimpleTy) && baseVT==MVT::i32) {  /* we have only subword type with basicType = i32 */
+        if (ElemSize==1) return MVT::vs1p32;
+        if (ElemSize==2) return MVT::vs2p32;
+        if (ElemSize==3) return MVT::vs3p32;
+        if (ElemSize==4) return MVT::vs4p32;
+        if (ElemSize==8) return MVT::vs8p32;
+        if (ElemSize==16) return MVT::vs16p32;
+      }
+      return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE);
+    }
+
     static MVT getVectorVT(MVT VT, unsigned NumElements, bool IsScalable) {
       if (IsScalable)
         return getScalableVectorVT(VT, NumElements);
@@ -1176,6 +1266,13 @@ namespace llvm {
             MVT::FIRST_FP_SCALABLE_VECTOR_VALUETYPE,
             (MVT::SimpleValueType)(MVT::LAST_FP_SCALABLE_VECTOR_VALUETYPE + 1));
     }
+
+    static mvt_range subword_vector_valuetypes() {
+      return mvt_range(
+               MVT::FIRST_SUBWORD_VECTOR_VALUETYPE,
+               (MVT::SimpleValueType)(MVT::LAST_SUBWORD_VECTOR_VALUETYPE + 1));
+    }
+
     /// @}
   };
 
diff --git a/llvm/include/llvm/Target/TargetOptions.h b/llvm/include/llvm/Target/TargetOptions.h
index d1db4eceabb8..52793481fe70 100644
--- a/llvm/include/llvm/Target/TargetOptions.h
+++ b/llvm/include/llvm/Target/TargetOptions.h
@@ -20,6 +20,57 @@ namespace llvm {
   class MachineFunction;
   class Module;
 
+  namespace SoftFops {
+    enum SoftFPoperations {
+      SOFTFP_ADD  =  0,
+      SOFTFP_SUB  =  1,
+      SOFTFP_MUL  =  2,
+      SOFTFP_DIV  =  3,
+      SOFTFP_MULEX=  4,
+      SOFTFP_SQRT =  5,
+      SOFTFP_CMP  =  6,
+      SOFTFP_CI2F =  7,
+      SOFTFP_CF2I =  8,
+      SOFTFP_CFUP =  9,
+      SOFTFP_CFDN = 10,
+      SOFTFP_ABS  = 11,
+      SOFTFP_PACK = 12, // extract/pack for packed/complex registers
+      SOFTFP_MOV  = 13,
+      SOFTFP_NEG  = 14,
+    };
+    enum SoftFopsMasks {
+      FPOP_ADD  = (1<<SOFTFP_ADD), // 'a'
+      FPOP_SUB  = (1<<SOFTFP_SUB), // 's'
+      FPOP_MUL  = (1<<SOFTFP_MUL), // 'm'
+      FPOP_DIV  = (1<<SOFTFP_DIV), // 'd'
+      FPOP_MULEX= (1<<SOFTFP_MULEX), // 'M' expanding multiply (from the specific precision to higher precision)
+      FPOP_SQRT = (1<<SOFTFP_SQRT), // 'S'
+      FPOP_CMP  = (1<<SOFTFP_CMP),  // 'c'
+      FPOP_CI2F = (1<<SOFTFP_CI2F), // 'f' - convert integer into float
+      FPOP_CF2I = (1<<SOFTFP_CF2I), // 'i' - convert float into integer
+      FPOP_CFUP = (1<<SOFTFP_CFUP), // 'h' - convert float into float with higher precision (H->S,S->D,D->Q)
+      FPOP_CFDN = (1<<SOFTFP_CFDN), // 'l' - convert float into float with lower precision (D->S,S->H)
+// newly added - TODO: check the whole LLVM
+      FPOP_ABS  = (1<<SOFTFP_ABS),  // 'A'
+      FPOP_PACK = (1<<SOFTFP_PACK), // 'p' - all pack/unpack operation
+      FPOP_MOV  = (1<<SOFTFP_MOV),  // 'C' - copy register to another register
+      FPOP_NEG  = (1<<SOFTFP_NEG),  // 'n' - neg
+
+      FPOP_KNOWN_MASK = FPOP_ADD | FPOP_SUB | FPOP_MUL | FPOP_DIV |
+                        FPOP_MULEX | FPOP_SQRT | FPOP_CMP | FPOP_CI2F |
+                        FPOP_CF2I | FPOP_CFUP | FPOP_CFDN | FPOP_ABS |
+                        FPOP_PACK | FPOP_MOV | FPOP_NEG
+    };
+  }
+  namespace SwarKinds {
+    enum SWARKind {
+      Infer,
+      Audio,
+      Video,
+      ALU
+    };
+  }
+
   namespace FloatABI {
     enum ABIType {
       Default, // Target-specific (either soft or hard depending on triple, etc).
diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp
index ad6765e2514b..8b16b3101b35 100644
--- a/llvm/lib/Analysis/ValueTracking.cpp
+++ b/llvm/lib/Analysis/ValueTracking.cpp
@@ -192,8 +192,18 @@ bool llvm::haveNoCommonBitsSet(const Value *LHS, const Value *RHS,
                                const DataLayout &DL, AssumptionCache *AC,
                                const Instruction *CxtI, const DominatorTree *DT,
                                bool UseInstrInfo) {
-  assert(LHS->getType() == RHS->getType() &&
-         "LHS and RHS should have the same type");
+  if (LHS->getType()->isVectorTy() && RHS->getType()->isVectorTy() &&
+      (LHS->getType()->getVectorIsSubword() || RHS->getType()->getVectorIsSubword())
+     ) {
+    assert( LHS->getType()->getVectorNumElements() ==
+            RHS->getType()->getVectorNumElements() &&
+            LHS->getType()->getVectorElementType() ==
+            RHS->getType()->getVectorElementType() &&
+            "Vector LHS and RHS should be the same");
+  } else {
+    assert(LHS->getType() == RHS->getType() &&
+           "LHS and RHS should have the same type");
+  }
   assert(LHS->getType()->isIntOrIntVectorTy() &&
          "LHS and RHS should be integers");
   // Look for an inverted mask: (X & ~M) op (Y & M).
diff --git a/llvm/lib/AsmParser/LLLexer.cpp b/llvm/lib/AsmParser/LLLexer.cpp
index d96b5e0bff5a..7b7c7e38ca26 100644
--- a/llvm/lib/AsmParser/LLLexer.cpp
+++ b/llvm/lib/AsmParser/LLLexer.cpp
@@ -714,6 +714,8 @@ lltok::Kind LLLexer::LexIdentifier() {
   KEYWORD(xchg); KEYWORD(nand); KEYWORD(max); KEYWORD(min); KEYWORD(umax);
   KEYWORD(umin);
 
+  KEYWORD(subword);
+  KEYWORD(in);
   KEYWORD(vscale);
   KEYWORD(x);
   KEYWORD(blockaddress);
diff --git a/llvm/lib/AsmParser/LLParser.cpp b/llvm/lib/AsmParser/LLParser.cpp
index 1a17f633ae16..cf6070ccb0e7 100644
--- a/llvm/lib/AsmParser/LLParser.cpp
+++ b/llvm/lib/AsmParser/LLParser.cpp
@@ -1375,6 +1375,21 @@ static inline GlobalValue *createGlobalFwdRef(Module *M, PointerType *PTy,
 
 Value *LLParser::checkValidVariableType(LocTy Loc, const Twine &Name, Type *Ty,
                                         Value *Val, bool IsCall) {
+
+  if (Val->getType()->isVectorTy() && Ty->isVectorTy()) do {
+    VectorType *VTyVal = cast<VectorType>(Val->getType());
+    VectorType *VTy = cast<VectorType>(Ty);
+    if (!VTyVal->isSubword()) break;
+    if (!VTy->isSubword()) break;
+    if (VTyVal->getBasicType()!=VTy->getBasicType()) break;
+    if (VTyVal->getElementType()!=VTy->getElementType()) break;
+    if (VTyVal->getNumElements()!=VTy->getNumElements()) break;
+    if (VTyVal->getPackSize()!=VTy->getPackSize()) break;
+    /* all is the same ... */
+    return Val;
+  } while (0);
+
+
   if (Val->getType() == Ty)
     return Val;
   // For calls we also accept variables in the program address space.
@@ -2346,8 +2361,9 @@ bool LLParser::ParseType(Type *&Result, const Twine &Msg, bool AllowVoid) {
       if (ParseAnonStructType(Result, true) ||
           ParseToken(lltok::greater, "expected '>' at end of packed struct"))
         return true;
-    } else if (ParseArrayVectorType(Result, true))
+    } else if (ParseArrayVectorType(Result, true)) {
       return true;
+    }
     break;
   case lltok::LocalVar: {
     // Type ::= %foo
@@ -2781,8 +2797,11 @@ bool LLParser::ParseStructBody(SmallVectorImpl<Type*> &Body) {
 ///     ::= '[' APSINTVAL 'x' Types ']'
 ///     ::= '<' APSINTVAL 'x' Types '>'
 ///     ::= '<' 'vscale' 'x' APSINTVAL 'x' Types '>'
+///     ::= '<' 'subword' APSINTVAL 'x' IntTypes 'in' IntTypes {*}'>' - if '*' is used, the subword has signed basic type
 bool LLParser::ParseArrayVectorType(Type *&Result, bool isVector) {
   bool Scalable = false;
+  bool Subword = false;
+  bool Signed = false;
 
   if (isVector && Lex.getKind() == lltok::kw_vscale) {
     Lex.Lex(); // consume the 'vscale'
@@ -2792,6 +2811,12 @@ bool LLParser::ParseArrayVectorType(Type *&Result, bool isVector) {
     Scalable = true;
   }
 
+  // subword vector
+  if (isVector && Lex.getKind() == lltok::kw_subword) {
+    Lex.Lex(); // consume the 'subword'
+    Subword = true;
+  }
+
   if (Lex.getKind() != lltok::APSInt || Lex.getAPSIntVal().isSigned() ||
       Lex.getAPSIntVal().getBitWidth() > 64)
     return TokError("expected number in address space");
@@ -2807,6 +2832,32 @@ bool LLParser::ParseArrayVectorType(Type *&Result, bool isVector) {
   Type *EltTy = nullptr;
   if (ParseType(EltTy)) return true;
 
+
+  uint64_t PackSize = 0;
+  Type *BasTy = nullptr;
+  if (Subword) { // < subword PackSz x EltTy in BasTy > -> parse 'PackSz inreg BasTy'
+    //LocTy PackSzLoc = Lex.getLoc();
+    if (Lex.getKind() != lltok::APSInt || Lex.getAPSIntVal().isSigned() ||
+        Lex.getAPSIntVal().getBitWidth() > 64)
+      return TokError("expected number as packsize");
+    //SizeLoc = Lex.getLoc();
+    PackSize = Lex.getAPSIntVal().getZExtValue();
+    Lex.Lex();
+    if (Size == 0)
+      return Error(SizeLoc, "zero packsize in subword is illegal");
+
+    if (ParseToken(lltok::kw_in, "expected 'in' after packsize"))
+        return true;
+
+    //TypeLoc = Lex.getLoc();
+    if (ParseType(BasTy)) return true;
+
+    if (Lex.getKind() == lltok::star) {
+      Signed = true;
+      Lex.Lex();
+    }
+  }
+
   if (ParseToken(isVector ? lltok::greater : lltok::rsquare,
                  "expected end of sequential type"))
     return true;
@@ -2816,9 +2867,13 @@ bool LLParser::ParseArrayVectorType(Type *&Result, bool isVector) {
       return Error(SizeLoc, "zero element vector is illegal");
     if ((unsigned)Size != Size)
       return Error(SizeLoc, "size too large for vector");
-    if (!VectorType::isValidElementType(EltTy))
-      return Error(TypeLoc, "invalid vector element type");
-    Result = VectorType::get(EltTy, unsigned(Size), Scalable);
+    if (Subword && EltTy->isIntegerTy()) {
+      Result = VectorType::get(BasTy, EltTy, unsigned(PackSize), Signed);
+    } else {
+      if (!VectorType::isValidElementType(EltTy))
+        return Error(TypeLoc, "invalid vector element type");
+      Result = VectorType::get(EltTy, unsigned(Size), Scalable);
+    }
   } else {
     if (!ArrayType::isValidElementType(EltTy))
       return Error(TypeLoc, "invalid array element type");
diff --git a/llvm/lib/AsmParser/LLToken.h b/llvm/lib/AsmParser/LLToken.h
index e430e0f6faa0..b8592081de7d 100644
--- a/llvm/lib/AsmParser/LLToken.h
+++ b/llvm/lib/AsmParser/LLToken.h
@@ -37,6 +37,8 @@ enum Kind {
   bar,     // |
   colon,   // :
 
+  kw_subword,
+  kw_in,
   kw_vscale,
   kw_x,
   kw_true,
diff --git a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
index 33464412edc5..101c6cd4db5b 100644
--- a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
+++ b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
@@ -1897,16 +1897,24 @@ Error BitcodeReader::parseTypeTableBody() {
       ResultTy = ArrayType::get(ResultTy, Record[0]);
       break;
     case bitc::TYPE_CODE_VECTOR:    // VECTOR: [numelts, eltty] or
-                                    //         [numelts, eltty, scalable]
-      if (Record.size() < 2)
+                                    //         [numelts, eltty, scalable] or
+                                    //         [numelts, eltty, packsz, basty, BTsigned]
+      if (Record.size() < 2 || Record.size()==4 || Record.size()>5)
         return error("Invalid record");
       if (Record[0] == 0)
         return error("Invalid vector length");
       ResultTy = getTypeByID(Record[1]);
       if (!ResultTy || !StructType::isValidElementType(ResultTy))
         return error("Invalid type");
-      bool Scalable = Record.size() > 2 ? Record[2] : false;
-      ResultTy = VectorType::get(ResultTy, Record[0], Scalable);
+      if (Record.size()>3) { // SWAR subword vector
+        unsigned bid = Record[3];
+        Type *BasTy = getTypeByID(bid);
+        bool BTsigned = Record.size() > 4 ? Record[4] : false;
+        ResultTy = VectorType::get(BasTy, ResultTy, Record[2], BTsigned);
+      } else { // Scalable vector
+        bool Scalable = Record.size() > 2 ? Record[2] : false;
+        ResultTy = VectorType::get(ResultTy, Record[0], Scalable);
+      }
       break;
     }
 
@@ -3889,7 +3897,7 @@ Error BitcodeReader::parseFunctionBody(Function *F) {
       unsigned OpNum = 0;
       Value *LHS, *RHS;
       if (getValueTypePair(Record, OpNum, NextValueNo, LHS) ||
-          popValue(Record, OpNum, NextValueNo, LHS->getType(), RHS) ||
+          getValueTypePair(Record, OpNum, NextValueNo, RHS) ||
           OpNum+1 > Record.size())
         return error("Invalid record");
 
@@ -4147,8 +4155,13 @@ Error BitcodeReader::parseFunctionBody(Function *F) {
         return error("Invalid record");
       if (!Vec->getType()->isVectorTy())
         return error("Invalid type for value");
-      if (popValue(Record, OpNum, NextValueNo,
-                   cast<VectorType>(Vec->getType())->getElementType(), Elt) ||
+      bool pv = popValue(Record, OpNum, NextValueNo,
+                   cast<VectorType>(Vec->getType())->getElementType(), Elt);
+      if (pv && cast<VectorType>(Vec->getType())->getVectorIsSubword()) {
+        pv = popValue(Record, OpNum, NextValueNo,
+                   cast<VectorType>(Vec->getType())->getBasicType(), Elt);
+      }
+      if (pv ||
           getValueTypePair(Record, OpNum, NextValueNo, Idx))
         return error("Invalid record");
       I = InsertElementInst::Create(Vec, Elt, Idx);
@@ -4183,9 +4196,16 @@ Error BitcodeReader::parseFunctionBody(Function *F) {
 
       unsigned OpNum = 0;
       Value *LHS, *RHS;
+
+#if 0
       if (getValueTypePair(Record, OpNum, NextValueNo, LHS) ||
           popValue(Record, OpNum, NextValueNo, LHS->getType(), RHS))
         return error("Invalid record");
+#else
+      if (getValueTypePair(Record, OpNum, NextValueNo, LHS) ||
+          getValueTypePair(Record, OpNum, NextValueNo, RHS))
+        return error("Invalid record");
+#endif
 
       if (OpNum >= Record.size())
         return error(
diff --git a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
index dcff7c421fc4..3890193fa75e 100644
--- a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
+++ b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
@@ -949,12 +949,19 @@ void ModuleBitcodeWriter::writeTypeTable() {
     case Type::VectorTyID: {
       VectorType *VT = cast<VectorType>(T);
       // VECTOR [numelts, eltty] or
-      //        [numelts, eltty, scalable]
+      //        [numelts, eltty, scalable] or
+      //        [numelts, eltty, packsz, basty, btsign]
       Code = bitc::TYPE_CODE_VECTOR;
       TypeVals.push_back(VT->getNumElements());
       TypeVals.push_back(VE.getTypeID(VT->getElementType()));
-      if (VT->isScalable())
+      if (VT->isScalable()) {
         TypeVals.push_back(VT->isScalable());
+      } else if (VT->isSubword()) {
+        TypeVals.push_back(VT->getPackSize());
+        TypeVals.push_back(VE.getTypeID(VT->getBasicType()));
+        TypeVals.push_back(VT->getBasicSign());
+        //AbbrevToUse=0;
+      }
       break;
     }
     }
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index c41aef34b539..8c48b1cd524d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -139,7 +139,7 @@ private:
 
   SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
 
-  void ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
+  void ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F16, RTLIB::Libcall Call_F32,
                        RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
                        RTLIB::Libcall Call_F128,
                        RTLIB::Libcall Call_PPCF128,
@@ -150,7 +150,7 @@ private:
                            RTLIB::Libcall Call_I32,
                            RTLIB::Libcall Call_I64,
                            RTLIB::Libcall Call_I128);
-  void ExpandArgFPLibCall(SDNode *Node,
+  void ExpandArgFPLibCall(SDNode *Node, RTLIB::Libcall Call_F16,
                           RTLIB::Libcall Call_F32, RTLIB::Libcall Call_F64,
                           RTLIB::Libcall Call_F80, RTLIB::Libcall Call_F128,
                           RTLIB::Libcall Call_PPCF128,
@@ -970,12 +970,18 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
              TargetLowering::TypeLegal &&
            "Unexpected illegal type!");
 
-  for (const SDValue &Op : Node->op_values())
+  for (const SDValue &Op : Node->op_values()) {
+    if (TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) !=
+              TargetLowering::TypeLegal &&
+            Op.getOpcode() != ISD::TargetConstant &&
+            Op.getOpcode() != ISD::Register) {
+    }
     assert((TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) ==
               TargetLowering::TypeLegal ||
             Op.getOpcode() == ISD::TargetConstant ||
             Op.getOpcode() == ISD::Register) &&
             "Unexpected illegal type!");
+  }
 #endif
 
   // Figure out the correct action; the way to query this varies by opcode
@@ -2083,6 +2089,7 @@ SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
 }
 
 void SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
+                                           RTLIB::Libcall Call_F16,
                                            RTLIB::Libcall Call_F32,
                                            RTLIB::Libcall Call_F64,
                                            RTLIB::Libcall Call_F80,
@@ -2092,6 +2099,7 @@ void SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
   RTLIB::Libcall LC;
   switch (Node->getSimpleValueType(0).SimpleTy) {
   default: llvm_unreachable("Unexpected request for libcall!");
+  case MVT::f16: LC = Call_F16; break;
   case MVT::f32: LC = Call_F32; break;
   case MVT::f64: LC = Call_F64; break;
   case MVT::f80: LC = Call_F80; break;
@@ -2137,6 +2145,7 @@ SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
 /// Expand the node to a libcall based on first argument type (for instance
 /// lround and its variant).
 void SelectionDAGLegalize::ExpandArgFPLibCall(SDNode* Node,
+                                            RTLIB::Libcall Call_F16,
                                             RTLIB::Libcall Call_F32,
                                             RTLIB::Libcall Call_F64,
                                             RTLIB::Libcall Call_F80,
@@ -2148,6 +2157,7 @@ void SelectionDAGLegalize::ExpandArgFPLibCall(SDNode* Node,
   RTLIB::Libcall LC;
   switch (InVT.getSimpleVT().SimpleTy) {
   default: llvm_unreachable("Unexpected request for libcall!");
+  case MVT::f16:     LC = Call_F16; break;
   case MVT::f32:     LC = Call_F32; break;
   case MVT::f64:     LC = Call_F64; break;
   case MVT::f80:     LC = Call_F80; break;
@@ -3917,36 +3927,36 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
   }
   case ISD::FMINNUM:
   case ISD::STRICT_FMINNUM:
-    ExpandFPLibCall(Node, RTLIB::FMIN_F32, RTLIB::FMIN_F64,
+    ExpandFPLibCall(Node, RTLIB::FMIN_F16, RTLIB::FMIN_F32, RTLIB::FMIN_F64,
                     RTLIB::FMIN_F80, RTLIB::FMIN_F128,
                     RTLIB::FMIN_PPCF128, Results);
     break;
   case ISD::FMAXNUM:
   case ISD::STRICT_FMAXNUM:
-    ExpandFPLibCall(Node, RTLIB::FMAX_F32, RTLIB::FMAX_F64,
+    ExpandFPLibCall(Node, RTLIB::FMAX_F16, RTLIB::FMAX_F32, RTLIB::FMAX_F64,
                     RTLIB::FMAX_F80, RTLIB::FMAX_F128,
                     RTLIB::FMAX_PPCF128, Results);
     break;
   case ISD::FSQRT:
   case ISD::STRICT_FSQRT:
-    ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
+    ExpandFPLibCall(Node, RTLIB::SQRT_F16, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
                     RTLIB::SQRT_F80, RTLIB::SQRT_F128,
                     RTLIB::SQRT_PPCF128, Results);
     break;
   case ISD::FCBRT:
-    ExpandFPLibCall(Node, RTLIB::CBRT_F32, RTLIB::CBRT_F64,
+    ExpandFPLibCall(Node, RTLIB::CBRT_F16, RTLIB::CBRT_F32, RTLIB::CBRT_F64,
                     RTLIB::CBRT_F80, RTLIB::CBRT_F128,
                     RTLIB::CBRT_PPCF128, Results);
     break;
   case ISD::FSIN:
   case ISD::STRICT_FSIN:
-    ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
+    ExpandFPLibCall(Node, RTLIB::SIN_F16, RTLIB::SIN_F32, RTLIB::SIN_F64,
                     RTLIB::SIN_F80, RTLIB::SIN_F128,
                     RTLIB::SIN_PPCF128, Results);
     break;
   case ISD::FCOS:
   case ISD::STRICT_FCOS:
-    ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
+    ExpandFPLibCall(Node, RTLIB::COS_F16, RTLIB::COS_F32, RTLIB::COS_F64,
                     RTLIB::COS_F80, RTLIB::COS_F128,
                     RTLIB::COS_PPCF128, Results);
     break;
@@ -3957,95 +3967,95 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
   case ISD::FLOG:
   case ISD::STRICT_FLOG:
     if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_log_finite))
-      ExpandFPLibCall(Node, RTLIB::LOG_FINITE_F32,
+      ExpandFPLibCall(Node, RTLIB::LOG_FINITE_F16, RTLIB::LOG_FINITE_F32,
                       RTLIB::LOG_FINITE_F64,
                       RTLIB::LOG_FINITE_F80,
                       RTLIB::LOG_FINITE_F128,
                       RTLIB::LOG_FINITE_PPCF128, Results);
     else
-      ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
+      ExpandFPLibCall(Node, RTLIB::LOG_F16, RTLIB::LOG_F32, RTLIB::LOG_F64,
                       RTLIB::LOG_F80, RTLIB::LOG_F128,
                       RTLIB::LOG_PPCF128, Results);
     break;
   case ISD::FLOG2:
   case ISD::STRICT_FLOG2:
     if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_log2_finite))
-      ExpandFPLibCall(Node, RTLIB::LOG2_FINITE_F32,
+      ExpandFPLibCall(Node, RTLIB::LOG2_FINITE_F16, RTLIB::LOG2_FINITE_F32,
                       RTLIB::LOG2_FINITE_F64,
                       RTLIB::LOG2_FINITE_F80,
                       RTLIB::LOG2_FINITE_F128,
                       RTLIB::LOG2_FINITE_PPCF128, Results);
     else
-      ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
+      ExpandFPLibCall(Node, RTLIB::LOG2_F16, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
                       RTLIB::LOG2_F80, RTLIB::LOG2_F128,
                       RTLIB::LOG2_PPCF128, Results);
     break;
   case ISD::FLOG10:
   case ISD::STRICT_FLOG10:
     if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_log10_finite))
-      ExpandFPLibCall(Node, RTLIB::LOG10_FINITE_F32,
+      ExpandFPLibCall(Node, RTLIB::LOG10_FINITE_F16, RTLIB::LOG10_FINITE_F32,
                       RTLIB::LOG10_FINITE_F64,
                       RTLIB::LOG10_FINITE_F80,
                       RTLIB::LOG10_FINITE_F128,
                       RTLIB::LOG10_FINITE_PPCF128, Results);
     else
-      ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
+      ExpandFPLibCall(Node, RTLIB::LOG10_F16, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
                       RTLIB::LOG10_F80, RTLIB::LOG10_F128,
                       RTLIB::LOG10_PPCF128, Results);
     break;
   case ISD::FEXP:
   case ISD::STRICT_FEXP:
     if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_exp_finite))
-      ExpandFPLibCall(Node, RTLIB::EXP_FINITE_F32,
+      ExpandFPLibCall(Node, RTLIB::EXP_FINITE_F16, RTLIB::EXP_FINITE_F32,
                       RTLIB::EXP_FINITE_F64,
                       RTLIB::EXP_FINITE_F80,
                       RTLIB::EXP_FINITE_F128,
                       RTLIB::EXP_FINITE_PPCF128, Results);
     else
-      ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
+      ExpandFPLibCall(Node, RTLIB::EXP_F16, RTLIB::EXP_F32, RTLIB::EXP_F64,
                       RTLIB::EXP_F80, RTLIB::EXP_F128,
                       RTLIB::EXP_PPCF128, Results);
     break;
   case ISD::FEXP2:
   case ISD::STRICT_FEXP2:
     if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_exp2_finite))
-      ExpandFPLibCall(Node, RTLIB::EXP2_FINITE_F32,
+      ExpandFPLibCall(Node, RTLIB::EXP2_FINITE_F16, RTLIB::EXP2_FINITE_F32,
                       RTLIB::EXP2_FINITE_F64,
                       RTLIB::EXP2_FINITE_F80,
                       RTLIB::EXP2_FINITE_F128,
                       RTLIB::EXP2_FINITE_PPCF128, Results);
     else
-      ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
+      ExpandFPLibCall(Node, RTLIB::EXP2_F16, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
                       RTLIB::EXP2_F80, RTLIB::EXP2_F128,
                       RTLIB::EXP2_PPCF128, Results);
     break;
   case ISD::FTRUNC:
   case ISD::STRICT_FTRUNC:
-    ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
+    ExpandFPLibCall(Node, RTLIB::TRUNC_F16, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
                     RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
                     RTLIB::TRUNC_PPCF128, Results);
     break;
   case ISD::FFLOOR:
   case ISD::STRICT_FFLOOR:
-    ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
+    ExpandFPLibCall(Node, RTLIB::FLOOR_F16, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
                     RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
                     RTLIB::FLOOR_PPCF128, Results);
     break;
   case ISD::FCEIL:
   case ISD::STRICT_FCEIL:
-    ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
+    ExpandFPLibCall(Node, RTLIB::CEIL_F16, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
                     RTLIB::CEIL_F80, RTLIB::CEIL_F128,
                     RTLIB::CEIL_PPCF128, Results);
     break;
   case ISD::FRINT:
   case ISD::STRICT_FRINT:
-    ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
+    ExpandFPLibCall(Node, RTLIB::RINT_F16, RTLIB::RINT_F32, RTLIB::RINT_F64,
                     RTLIB::RINT_F80, RTLIB::RINT_F128,
                     RTLIB::RINT_PPCF128, Results);
     break;
   case ISD::FNEARBYINT:
   case ISD::STRICT_FNEARBYINT:
-    ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
+    ExpandFPLibCall(Node, RTLIB::NEARBYINT_F16, RTLIB::NEARBYINT_F32,
                     RTLIB::NEARBYINT_F64,
                     RTLIB::NEARBYINT_F80,
                     RTLIB::NEARBYINT_F128,
@@ -4053,7 +4063,7 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
     break;
   case ISD::FROUND:
   case ISD::STRICT_FROUND:
-    ExpandFPLibCall(Node, RTLIB::ROUND_F32,
+    ExpandFPLibCall(Node, RTLIB::ROUND_F16, RTLIB::ROUND_F32,
                     RTLIB::ROUND_F64,
                     RTLIB::ROUND_F80,
                     RTLIB::ROUND_F128,
@@ -4064,6 +4074,7 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
     RTLIB::Libcall LC;
     switch (Node->getSimpleValueType(0).SimpleTy) {
     default: llvm_unreachable("Unexpected request for libcall!");
+    case MVT::f16: LC = RTLIB::POWI_F16; break;
     case MVT::f32: LC = RTLIB::POWI_F32; break;
     case MVT::f64: LC = RTLIB::POWI_F64; break;
     case MVT::f80: LC = RTLIB::POWI_F80; break;
@@ -4080,7 +4091,7 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
                                     Exponent));
       break;
     }
-    ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
+    ExpandFPLibCall(Node, RTLIB::POWI_F16, RTLIB::POWI_F32, RTLIB::POWI_F64,
                     RTLIB::POWI_F80, RTLIB::POWI_F128,
                     RTLIB::POWI_PPCF128, Results);
     break;
@@ -4088,71 +4099,71 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
   case ISD::FPOW:
   case ISD::STRICT_FPOW:
     if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_pow_finite))
-      ExpandFPLibCall(Node, RTLIB::POW_FINITE_F32,
+      ExpandFPLibCall(Node, RTLIB::POW_FINITE_F16, RTLIB::POW_FINITE_F32,
                       RTLIB::POW_FINITE_F64,
                       RTLIB::POW_FINITE_F80,
                       RTLIB::POW_FINITE_F128,
                       RTLIB::POW_FINITE_PPCF128, Results);
     else
-      ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
+      ExpandFPLibCall(Node, RTLIB::POW_F16, RTLIB::POW_F32, RTLIB::POW_F64,
                       RTLIB::POW_F80, RTLIB::POW_F128,
                       RTLIB::POW_PPCF128, Results);
     break;
   case ISD::LROUND:
   case ISD::STRICT_LROUND:
-    ExpandArgFPLibCall(Node, RTLIB::LROUND_F32,
+    ExpandArgFPLibCall(Node, RTLIB::LROUND_F16, RTLIB::LROUND_F32,
                        RTLIB::LROUND_F64, RTLIB::LROUND_F80,
                        RTLIB::LROUND_F128,
                        RTLIB::LROUND_PPCF128, Results);
     break;
   case ISD::LLROUND:
   case ISD::STRICT_LLROUND:
-    ExpandArgFPLibCall(Node, RTLIB::LLROUND_F32,
+    ExpandArgFPLibCall(Node, RTLIB::LLROUND_F16, RTLIB::LLROUND_F32,
                        RTLIB::LLROUND_F64, RTLIB::LLROUND_F80,
                        RTLIB::LLROUND_F128,
                        RTLIB::LLROUND_PPCF128, Results);
     break;
   case ISD::LRINT:
   case ISD::STRICT_LRINT:
-    ExpandArgFPLibCall(Node, RTLIB::LRINT_F32,
+    ExpandArgFPLibCall(Node, RTLIB::LRINT_F16, RTLIB::LRINT_F32,
                        RTLIB::LRINT_F64, RTLIB::LRINT_F80,
                        RTLIB::LRINT_F128,
                        RTLIB::LRINT_PPCF128, Results);
     break;
   case ISD::LLRINT:
   case ISD::STRICT_LLRINT:
-    ExpandArgFPLibCall(Node, RTLIB::LLRINT_F32,
+    ExpandArgFPLibCall(Node, RTLIB::LLRINT_F16, RTLIB::LLRINT_F32,
                        RTLIB::LLRINT_F64, RTLIB::LLRINT_F80,
                        RTLIB::LLRINT_F128,
                        RTLIB::LLRINT_PPCF128, Results);
     break;
   case ISD::FDIV:
   case ISD::STRICT_FDIV:
-    ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
+    ExpandFPLibCall(Node, RTLIB::DIV_F16, RTLIB::DIV_F32, RTLIB::DIV_F64,
                     RTLIB::DIV_F80, RTLIB::DIV_F128,
                     RTLIB::DIV_PPCF128, Results);
     break;
   case ISD::FREM:
   case ISD::STRICT_FREM:
-    ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
+    ExpandFPLibCall(Node, RTLIB::REM_F16, RTLIB::REM_F32, RTLIB::REM_F64,
                     RTLIB::REM_F80, RTLIB::REM_F128,
                     RTLIB::REM_PPCF128, Results);
     break;
   case ISD::FMA:
   case ISD::STRICT_FMA:
-    ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
+    ExpandFPLibCall(Node, RTLIB::FMA_F16, RTLIB::FMA_F32, RTLIB::FMA_F64,
                     RTLIB::FMA_F80, RTLIB::FMA_F128,
                     RTLIB::FMA_PPCF128, Results);
     break;
   case ISD::FADD:
   case ISD::STRICT_FADD:
-    ExpandFPLibCall(Node, RTLIB::ADD_F32, RTLIB::ADD_F64,
+    ExpandFPLibCall(Node, RTLIB::ADD_F16, RTLIB::ADD_F32, RTLIB::ADD_F64,
                     RTLIB::ADD_F80, RTLIB::ADD_F128,
                     RTLIB::ADD_PPCF128, Results);
     break;
   case ISD::FMUL:
   case ISD::STRICT_FMUL:
-    ExpandFPLibCall(Node, RTLIB::MUL_F32, RTLIB::MUL_F64,
+    ExpandFPLibCall(Node, RTLIB::MUL_F16, RTLIB::MUL_F32, RTLIB::MUL_F64,
                     RTLIB::MUL_F80, RTLIB::MUL_F128,
                     RTLIB::MUL_PPCF128, Results);
     break;
@@ -4160,6 +4171,9 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
     if (Node->getValueType(0) == MVT::f32) {
       Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
     }
+    if (Node->getValueType(0) == MVT::f64) {
+      Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F64, Node, false));
+    }
     break;
   case ISD::FP_TO_FP16: {
     RTLIB::Libcall LC =
@@ -4170,7 +4184,7 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
   }
   case ISD::FSUB:
   case ISD::STRICT_FSUB:
-    ExpandFPLibCall(Node, RTLIB::SUB_F32, RTLIB::SUB_F64,
+    ExpandFPLibCall(Node, RTLIB::SUB_F16, RTLIB::SUB_F32, RTLIB::SUB_F64,
                     RTLIB::SUB_F80, RTLIB::SUB_F128,
                     RTLIB::SUB_PPCF128, Results);
     break;
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 463c7a6bbee0..e3f3e96aa9ea 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1385,9 +1385,13 @@ SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
   // Promote the inserted value.  The type does not need to match the
   // vector element type.  Check that any extra bits introduced will be
   // truncated away.
-  assert(N->getOperand(0).getValueSizeInBits() >=
-         N->getValueType(0).getScalarSizeInBits() &&
-         "Type of inserted value narrower than vector element type!");
+  if (VecVT.isSubwordVector()) {
+    // do not check
+  } else {
+    assert(N->getOperand(0).getValueSizeInBits() >=
+           N->getValueType(0).getScalarSizeInBits() &&
+           "Type of inserted value narrower than vector element type!");
+  }
 
   SmallVector<SDValue, 16> NewOps;
   for (unsigned i = 0; i < NumElts; ++i)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 6dcf271a81c7..56b6e4eda442 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -818,14 +818,25 @@ static void VerifySDNode(SDNode *N) {
     assert(N->getValueType(0).isVector() && "Wrong return type!");
     assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() &&
            "Wrong number of operands!");
-    EVT EltVT = N->getValueType(0).getVectorElementType();
-    for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) {
-      assert((I->getValueType() == EltVT ||
-             (EltVT.isInteger() && I->getValueType().isInteger() &&
-              EltVT.bitsLE(I->getValueType()))) &&
-            "Wrong operand type!");
-      assert(I->getValueType() == N->getOperand(0).getValueType() &&
-             "Operands must all have the same type");
+
+    if (N->getValueType(0).isSubwordVector()) { /* build subword packed type */
+      EVT EltVT = N->getValueType(0).getVectorElementType(); /* output element type */
+      assert(EltVT.isInteger() && "Only integer result is allowed");
+      for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) {
+        assert(I->getValueType().isInteger() && "Only integer operand types are allowed");
+      }
+
+    } else {
+      EVT EltVT = N->getValueType(0).getVectorElementType(); /* output element type */
+      for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) {
+        assert((I->getValueType() == EltVT ||
+               (EltVT.isInteger() && I->getValueType().isInteger() &&
+                EltVT.bitsLE(I->getValueType()))) &&
+              "Wrong operand type!");
+
+        assert(I->getValueType() == N->getOperand(0).getValueType() &&
+               "Operands must all have the same type");
+      }
     }
     break;
   }
@@ -1309,11 +1320,14 @@ SDValue SelectionDAG::getConstant(const ConstantInt &Val, const SDLoc &DL,
   }
 
   SDValue Result(N, 0);
-  if (VT.isScalableVector())
+
+  if (VT.isSubwordVector()) { // vector is a subword type
+    Result = getNode(ISD::BITCAST, DL, VT);
+  } else if (VT.isScalableVector()) {
     Result = getSplatVector(VT, DL, Result);
-  else if (VT.isVector())
+  } else if (VT.isVector()) {
     Result = getSplatBuildVector(VT, DL, Result);
-
+  }
   return Result;
 }
 
@@ -5120,11 +5134,25 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
     break;
   case ISD::OR:
   case ISD::XOR:
+    assert(VT.isInteger() && "This operator does not apply to FP types!");
+    assert(N1.getValueType() == N2.getValueType() &&
+           N1.getValueType() == VT && "Binary operator types must match!");
+    // (X ^|+- 0) -> X.  This commonly occurs when legalizing i64 values, so
+    // it's worth handling here.
+    if (N2C && N2C->isNullValue())
+      return N1;
+    break;
   case ISD::ADD:
   case ISD::SUB:
     assert(VT.isInteger() && "This operator does not apply to FP types!");
+if ((N1.getValueType().isSubwordVector() && N1.getValueType().isVector()) || (N1.getValueType().isVector() && N2.getValueType().isSubwordVector())) { // for vector-subword vector
+  assert(//N1.getValueType().getVectorElementType()==N2.getValueType().getVectorElementType() &&
+         N1.getValueType().getVectorNumElements()==N2.getValueType().getVectorNumElements() &&
+         "Binary operator types must have the same size!");
+} else {
     assert(N1.getValueType() == N2.getValueType() &&
            N1.getValueType() == VT && "Binary operator types must match!");
+}
     // (X ^|+- 0) -> X.  This commonly occurs when legalizing i64 values, so
     // it's worth handling here.
     if (N2C && N2C->isNullValue())
@@ -5134,7 +5162,6 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
   case ISD::UREM:
   case ISD::MULHU:
   case ISD::MULHS:
-  case ISD::MUL:
   case ISD::SDIV:
   case ISD::SREM:
   case ISD::SMIN:
@@ -5149,6 +5176,12 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
     assert(N1.getValueType() == N2.getValueType() &&
            N1.getValueType() == VT && "Binary operator types must match!");
     break;
+  case ISD::MUL:
+    assert(VT.isInteger() && "This operator does not apply to FP types!");
+    assert(N1.getValueType() == N2.getValueType() &&
+           N1.getValueType() == VT && "Binary operator types must match!");
+    break;
+
   case ISD::FADD:
   case ISD::FSUB:
   case ISD::FMUL:
@@ -5259,9 +5292,12 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
     break;
   }
   case ISD::EXTRACT_VECTOR_ELT:
-    assert(VT.getSizeInBits() >= N1.getValueType().getScalarSizeInBits() &&
+    if (N1.getValueType().isSubwordVector()) {
+    } else {
+      assert(VT.getSizeInBits() >= N1.getValueType().getScalarSizeInBits() &&
            "The result of EXTRACT_VECTOR_ELT must be at least as wide as the \
              element type of the vector.");
+    }
 
     // Extract from an undefined value or using an undefined index is undefined.
     if (N1.isUndef() || N2.isUndef())
@@ -5511,8 +5547,21 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
   }
   case ISD::SETCC: {
     assert(VT.isInteger() && "SETCC result type must be an integer!");
+
+    if (N1.getValueType() != N2.getValueType()) {
+      unsigned n1bw = N1.getValueType().getSizeInBits();
+      unsigned n2bw = N2.getValueType().getSizeInBits();
+fprintf(stderr,">RB< ISD::SETCC n1bw=%u ? n1bw=%u\n", n1bw, n2bw);
+      if (n1bw<n2bw) {
+        N1 = getNode(ISD::ZERO_EXTEND, DL, N2.getValueType(), N1);
+      } else {
+        N2 = getNode(ISD::ZERO_EXTEND, DL, N1.getValueType(), N2);
+      }
+    }
+
     assert(N1.getValueType() == N2.getValueType() &&
            "SETCC operands must have the same type!");
+
     assert(VT.isVector() == N1.getValueType().isVector() &&
            "SETCC type should be vector iff the operand type is vector!");
     assert((!VT.isVector() ||
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index e879df2f2d9c..4fde763b7f64 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -4124,8 +4124,18 @@ void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
                             MMOFlags, AAInfo, Ranges);
     Chains[ChainI] = L.getValue(1);
 
-    if (MemVTs[i] != ValueVTs[i])
-      L = DAG.getZExtOrTrunc(L, dl, ValueVTs[i]);
+    if (ValueVTs[i].isSubwordVector()) {
+      if (MemVTs[i].isInteger() &&
+          MemVTs[i].getSimpleVT()==ValueVTs[i].getVectorElementType().getSimpleVT()) { /* all subword vectors are placed */
+        L = DAG.getBitcast(ValueVTs[i], L);
+      } else {
+        L = DAG.getPtrExtOrTrunc(L, dl, ValueVTs[i]);
+      }
+    } else {
+
+      if (MemVTs[i] != ValueVTs[i])
+        L = DAG.getZExtOrTrunc(L, dl, ValueVTs[i]);
+    }
 
     Values[i] = L;
   }
@@ -4267,8 +4277,17 @@ void SelectionDAGBuilder::visitStore(const StoreInst &I) {
     }
     SDValue Add = DAG.getMemBasePlusOffset(Ptr, Offsets[i], dl, Flags);
     SDValue Val = SDValue(Src.getNode(), Src.getResNo() + i);
-    if (MemVTs[i] != ValueVTs[i])
-      Val = DAG.getPtrExtOrTrunc(Val, dl, MemVTs[i]);
+    if (ValueVTs[i].isSubwordVector()) {
+      if (MemVTs[i].isInteger() &&
+          MemVTs[i].getSimpleVT()==ValueVTs[i].getVectorElementType().getSimpleVT()) { /* all subword vectors are placed */
+        Val = DAG.getBitcast(MemVTs[i], Val);
+      } else {
+        Val = DAG.getPtrExtOrTrunc(Val, dl, MemVTs[i]);
+      }
+    } else {
+      if (MemVTs[i] != ValueVTs[i])
+        Val = DAG.getPtrExtOrTrunc(Val, dl, MemVTs[i]);
+    }
     SDValue St =
         DAG.getStore(Root, dl, Val, Add, MachinePointerInfo(PtrV, Offsets[i]),
                      Alignment, MMOFlags, AAInfo);
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index 9198ae07c00e..5dbb8794bc25 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -222,6 +222,8 @@ RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
   if (OpVT == MVT::f16) {
     if (RetVT == MVT::f32)
       return FPEXT_F16_F32;
+    if (RetVT == MVT::f64)
+      return FPEXT_F16_F64;
   } else if (OpVT == MVT::f32) {
     if (RetVT == MVT::f64)
       return FPEXT_F32_F64;
diff --git a/llvm/lib/CodeGen/ValueTypes.cpp b/llvm/lib/CodeGen/ValueTypes.cpp
index 41cbdf035558..e52150044ab0 100644
--- a/llvm/lib/CodeGen/ValueTypes.cpp
+++ b/llvm/lib/CodeGen/ValueTypes.cpp
@@ -35,7 +35,8 @@ EVT EVT::getExtendedIntegerVT(LLVMContext &Context, unsigned BitWidth) {
 EVT EVT::getExtendedVectorVT(LLVMContext &Context, EVT VT,
                              unsigned NumElements) {
   EVT ResultVT;
-  ResultVT.LLVMTy = VectorType::get(VT.getTypeForEVT(Context), NumElements);
+  Type *elty = VT.getTypeForEVT(Context);
+  ResultVT.LLVMTy = VectorType::get(elty, NumElements);
   assert(ResultVT.isExtended() && "Type is not extended!");
   return ResultVT;
 }
@@ -60,6 +61,14 @@ bool EVT::isExtendedVector() const {
   return LLVMTy->isVectorTy();
 }
 
+bool EVT::isExtendedSubword() const {
+  assert(isExtended() && "Type is not extended!");
+  if (LLVMTy->isVectorTy()) {
+    return LLVMTy->getVectorIsSubword();
+  }
+  return false;
+}
+
 bool EVT::isExtended16BitVector() const {
   return isExtendedVector() && getExtendedSizeInBits() == 16;
 }
@@ -131,6 +140,13 @@ std::string EVT::getEVTString() const {
   case MVT::Metadata:return "Metadata";
   case MVT::Untyped: return "Untyped";
   case MVT::exnref : return "exnref";
+
+  case MVT::vs1p32:  return "vs1p32";
+  case MVT::vs2p32:  return "vs2p32";
+  case MVT::vs3p32:  return "vs3p32";
+  case MVT::vs4p32:  return "vs4p32";
+  case MVT::vs8p32:  return "vs8p32";
+  case MVT::vs16p32: return "vs16p32";
   }
 }
 
@@ -315,6 +331,21 @@ Type *EVT::getTypeForEVT(LLVMContext &Context) const {
   case MVT::nxv8f64: 
     return VectorType::get(Type::getDoubleTy(Context), 8, /*Scalable=*/ true);
   case MVT::Metadata: return Type::getMetadataTy(Context);
+
+  /* return type for basic vector of packed elements */
+  case MVT::vs1p32:
+    return VectorType::get(Type::getInt32Ty(Context), Type::getIntNTy(Context, 1), packing, false);
+  case MVT::vs2p32:
+    return VectorType::get(Type::getInt32Ty(Context), Type::getIntNTy(Context, 2), packing, false);
+  case MVT::vs3p32:
+    return VectorType::get(Type::getInt32Ty(Context), Type::getIntNTy(Context, 3), packing, false);
+  case MVT::vs4p32:
+    return VectorType::get(Type::getInt32Ty(Context), Type::getIntNTy(Context, 4), packing, false);
+  case MVT::vs8p32:
+    return VectorType::get(Type::getInt32Ty(Context), Type::getIntNTy(Context, 8), packing, false);
+  case MVT::vs16p32:
+    return VectorType::get(Type::getInt32Ty(Context), Type::getIntNTy(Context, 16), packing, false);
+
   }
 }
 
@@ -340,9 +371,15 @@ MVT MVT::getVT(Type *Ty, bool HandleUnknown){
   case Type::PointerTyID:   return MVT(MVT::iPTR);
   case Type::VectorTyID: {
     VectorType *VTy = cast<VectorType>(Ty);
-    return getVectorVT(
-      getVT(VTy->getElementType(), /*HandleUnknown=*/ false),
-            VTy->getElementCount());
+    if (VTy->isSubword()) { // vector is a subword type
+      return getSubwordVT(getVT(VTy->getBasicType(), false),
+                          VTy->getElementType()->getPrimitiveSizeInBits());
+
+    } else {
+      return getVectorVT(
+        getVT(VTy->getElementType(), /*HandleUnknown=*/ false),
+              VTy->getElementCount());
+    }
   }
   }
 }
@@ -358,9 +395,15 @@ EVT EVT::getEVT(Type *Ty, bool HandleUnknown){
     return getIntegerVT(Ty->getContext(), cast<IntegerType>(Ty)->getBitWidth());
   case Type::VectorTyID: {
     VectorType *VTy = cast<VectorType>(Ty);
+
+    if (VTy->isSubword()) { // vector is a subword type
+      return getSubwordVT(Ty->getContext(), MVT::getVT(Ty, false), VTy->getNumElements());
+
+    } else {
     return getVectorVT(Ty->getContext(),
                        getEVT(VTy->getElementType(), /*HandleUnknown=*/ false),
                        VTy->getElementCount());
+    }
   }
   }
 }
diff --git a/llvm/lib/IR/AsmWriter.cpp b/llvm/lib/IR/AsmWriter.cpp
index cda5fd0a3812..884302c61ed1 100644
--- a/llvm/lib/IR/AsmWriter.cpp
+++ b/llvm/lib/IR/AsmWriter.cpp
@@ -626,10 +626,20 @@ void TypePrinting::print(Type *Ty, raw_ostream &OS) {
   case Type::VectorTyID: {
     VectorType *PTy = cast<VectorType>(Ty);
     OS << "<";
-    if (PTy->isScalable())
-      OS << "vscale x ";
-    OS << PTy->getNumElements() << " x ";
-    print(PTy->getElementType(), OS);
+    if (PTy->isSubword()) {
+      OS << "subword ";
+      OS << " " << PTy->getNumElements() << " x ";
+      print(PTy->getElementType(), OS);
+      OS << " in ";
+      print(PTy->getBasicType(), OS);
+      if (PTy->getBasicSign())
+        OS << " *";
+    } else {
+      if (PTy->isScalable())
+        OS << "vscale x ";
+      OS << PTy->getNumElements() << " x ";
+      print(PTy->getElementType(), OS);
+    }
     OS << '>';
     return;
   }
diff --git a/llvm/lib/IR/ConstantFold.cpp b/llvm/lib/IR/ConstantFold.cpp
index 6e24f03c4cfd..d724f921e99b 100644
--- a/llvm/lib/IR/ConstantFold.cpp
+++ b/llvm/lib/IR/ConstantFold.cpp
@@ -138,8 +138,10 @@ static Constant *FoldBitCast(Constant *V, Type *DestTy) {
   // and dest type have the same size (otherwise its an illegal cast).
   if (VectorType *DestPTy = dyn_cast<VectorType>(DestTy)) {
     if (VectorType *SrcTy = dyn_cast<VectorType>(V->getType())) {
-      assert(DestPTy->getBitWidth() == SrcTy->getBitWidth() &&
-             "Not cast between same sized vectors!");
+      if (!DestPTy->getVectorIsSubword() && !SrcTy->getVectorIsSubword()) {
+        assert(DestPTy->getBitWidth() == SrcTy->getBitWidth() &&
+               "Not cast between same sized vectors!");
+      }
       SrcTy = nullptr;
       // First, check for null.  Undef is already handled.
       if (isa<ConstantAggregateZero>(V))
diff --git a/llvm/lib/IR/Constants.cpp b/llvm/lib/IR/Constants.cpp
index cafb412b795b..36660448eadc 100644
--- a/llvm/lib/IR/Constants.cpp
+++ b/llvm/lib/IR/Constants.cpp
@@ -1046,9 +1046,12 @@ ConstantAggregate::ConstantAggregate(CompositeType *T, ValueTy VT,
   if (auto *ST = dyn_cast<StructType>(T))
     if (ST->isOpaque())
       return;
-  for (unsigned I = 0, E = V.size(); I != E; ++I)
-    assert(V[I]->getType() == T->getTypeAtIndex(I) &&
+  if (!T->getVectorIsSubword()) {
+    for (unsigned I = 0, E = V.size(); I != E; ++I) {
+      assert(V[I]->getType() == T->getTypeAtIndex(I) &&
            "Initializer for composite element doesn't match!");
+    }
+  }
 }
 
 ConstantArray::ConstantArray(ArrayType *T, ArrayRef<Constant *> V)
@@ -1626,7 +1629,8 @@ Constant *ConstantExpr::getCast(unsigned oc, Constant *C, Type *Ty,
   Instruction::CastOps opc = Instruction::CastOps(oc);
   assert(Instruction::isCast(opc) && "opcode out of range");
   assert(C && Ty && "Null arguments to getCast");
-  assert(CastInst::castIsValid(opc, C, Ty) && "Invalid constantexpr cast!");
+  if (!Ty->getVectorIsSubword())
+    assert(CastInst::castIsValid(opc, C, Ty) && "Invalid constantexpr cast!");
 
   switch (opc) {
   default:
@@ -1930,11 +1934,20 @@ Constant *ConstantExpr::get(unsigned Opcode, Constant *C, unsigned Flags,
 
 Constant *ConstantExpr::get(unsigned Opcode, Constant *C1, Constant *C2,
                             unsigned Flags, Type *OnlyIfReducedTy) {
-  // Check the operands for consistency first.
   assert(Instruction::isBinaryOp(Opcode) &&
          "Invalid opcode in binary constant expression");
-  assert(C1->getType() == C2->getType() &&
-         "Operand types in binary constant expression should match");
+
+  if (C1->getType()->getVectorIsSubword() || C2->getType()->getVectorIsSubword()) {
+    if (!C1->getType()->isVectorTy() || !C2->getType()->isVectorTy()) {
+      assert(false &&
+             "Operand types (SWAR) are not vectors");
+    }
+
+  } else {
+    // Check the operands for consistency first.
+    assert(C1->getType() == C2->getType() &&
+           "Operand types in binary constant expression should match");
+  }
 
 #ifndef NDEBUG
   switch (Opcode) {
@@ -2201,8 +2214,17 @@ Constant *ConstantExpr::getInsertElement(Constant *Val, Constant *Elt,
                                          Constant *Idx, Type *OnlyIfReducedTy) {
   assert(Val->getType()->isVectorTy() &&
          "Tried to create insertelement operation on non-vector type!");
-  assert(Elt->getType() == Val->getType()->getVectorElementType() &&
-         "Insertelement types must match!");
+
+  if (Val->getType()->getVectorIsSubword()) {
+    // Subword vectors allow integer value or vector element type.
+    if (!Elt->getType()->isIntegerTy() &&
+        Elt->getType() != cast<VectorType>(Val->getType())->getVectorElementType())
+      return nullptr;
+  } else {
+
+    assert(Elt->getType() == Val->getType()->getVectorElementType() &&
+           "Insertelement types must match!");
+  }
   assert(Idx->getType()->isIntegerTy() &&
          "Insertelement index must be i32 type!");
 
diff --git a/llvm/lib/IR/DIBuilder.cpp b/llvm/lib/IR/DIBuilder.cpp
index c89f404e4296..a36ff31bb4ac 100644
--- a/llvm/lib/IR/DIBuilder.cpp
+++ b/llvm/lib/IR/DIBuilder.cpp
@@ -536,6 +536,21 @@ DICompositeType *DIBuilder::createVectorType(uint64_t Size,
   return R;
 }
 
+/* subword type is an array type with flag Subword and set strip_size */
+/* Ty = BaseType */
+/* ESize = element size */
+/* ECount = number of element */
+DICompositeType *DIBuilder::createSubwordType(uint64_t ESize, uint64_t ECount,
+                                              DIType *Ty,
+                                              DINodeArray Subscripts) {
+
+  auto *R = DICompositeType::get(VMContext, dwarf::DW_TAG_array_type, "",
+                                 nullptr, 0, nullptr, Ty, ESize*ECount, ESize, 0,
+                                 DINode::FlagSubword, Subscripts, 0, nullptr);
+  trackIfUnresolved(R);
+  return R;
+}
+
 DISubprogram *DIBuilder::createArtificialSubprogram(DISubprogram *SP) {
   auto NewSP = SP->cloneWithFlags(SP->getFlags() | DINode::FlagArtificial);
   return MDNode::replaceWithDistinct(std::move(NewSP));
diff --git a/llvm/lib/IR/Instructions.cpp b/llvm/lib/IR/Instructions.cpp
index c264277fa53c..4cf6be6d0408 100644
--- a/llvm/lib/IR/Instructions.cpp
+++ b/llvm/lib/IR/Instructions.cpp
@@ -394,10 +394,17 @@ void CallInst::init(FunctionType *FTy, Value *Func, ArrayRef<Value *> Args,
           (FTy->isVarArg() && Args.size() > FTy->getNumParams())) &&
          "Calling a function with bad signature!");
 
-  for (unsigned i = 0; i != Args.size(); ++i)
+  for (unsigned i = 0; i != Args.size(); ++i) {
+  if (Args[i]->getType()->getVectorIsSubword()) {
+    VectorType *vty = cast<VectorType>(Args[i]->getType());
+    assert((i >= FTy->getNumParams() ||
+            FTy->getParamType(i) == vty->getBasicType()) &&
+           "Calling a function with a bad signature!");
+  } else
     assert((i >= FTy->getNumParams() ||
             FTy->getParamType(i) == Args[i]->getType()) &&
            "Calling a function with a bad signature!");
+  }
 #endif
 
   llvm::copy(Args, op_begin());
@@ -1353,9 +1360,24 @@ void StoreInst::AssertOK() {
   assert(getOperand(0) && getOperand(1) && "Both operands must be non-null!");
   assert(getOperand(1)->getType()->isPointerTy() &&
          "Ptr must have pointer type!");
+if ((getOperand(0)->getType()->isVectorTy() && getOperand(0)->getType()->getVectorIsSubword()) ||
+    (cast<PointerType>(getOperand(1)->getType())->getElementType()->isVectorTy() &&
+     cast<PointerType>(getOperand(1)->getType())->getElementType()->getVectorIsSubword()) ) {
+
+  if (getOperand(0)->getType()->isVectorTy() && getOperand(0)->getType()->getVectorIsSubword()) {
+    VectorType *vty = cast<VectorType>(getOperand(0)->getType());
+  }
+
+  Type *pop1 = cast<PointerType>(getOperand(1)->getType())->getElementType();
+  if (pop1->isVectorTy() && pop1->getVectorIsSubword()) {
+    VectorType *vty = cast<VectorType>(pop1);
+  }
+  /* TODO : store subword to i32 or i32 to subword */
+} else {
   assert(getOperand(0)->getType() ==
                  cast<PointerType>(getOperand(1)->getType())->getElementType()
          && "Ptr must be a pointer to Val type!");
+}
   assert(!(isAtomic() && getAlignment() == 0) &&
          "Alignment required for atomic store");
 }
@@ -1764,13 +1786,25 @@ InsertElementInst::InsertElementInst(Value *Vec, Value *Elt, Value *Index,
 bool InsertElementInst::isValidOperands(const Value *Vec, const Value *Elt,
                                         const Value *Index) {
   if (!Vec->getType()->isVectorTy())
-    return false;   // First operand of insertelement must be vector type.
-
-  if (Elt->getType() != cast<VectorType>(Vec->getType())->getElementType())
-    return false;// Second operand of insertelement must be vector element type.
+    return false;   // First operand of insertelement must be vector type (can be subword vector type).
 
   if (!Index->getType()->isIntegerTy())
     return false;  // Third operand of insertelement must be i32.
+
+  if (Vec->getType()->getVectorIsSubword()) {
+    VectorType *vVec = dyn_cast<VectorType>(Vec->getType());
+    // Subword vectors allow integer value or vector element type.
+    if (Elt->getType()->isIntegerTy()) return true;
+    if (Elt->getType()->getVectorIsSubword()) {
+      VectorType *vElt = dyn_cast<VectorType>(Elt->getType());
+      if (vVec->getElementType()->getPrimitiveSizeInBits()==vElt->getElementType()->getPrimitiveSizeInBits() && vElt->getNumElements()==1) return true;
+    }
+    return false;
+  } else {
+    if (Elt->getType() != cast<VectorType>(Vec->getType())->getElementType())
+      return false;// Second operand of insertelement must be vector element type.
+  }
+
   return true;
 }
 
@@ -2240,6 +2274,15 @@ BinaryOperator::BinaryOperator(BinaryOps iType, Value *S1, Value *S2,
                 OperandTraits<BinaryOperator>::op_begin(this),
                 OperandTraits<BinaryOperator>::operands(this),
                 InsertBefore) {
+  SubwordOp = false;
+  if (S1->getType()->isVectorTy() && S2->getType()->isVectorTy()) {
+    VectorType *S1VecTy = dyn_cast<VectorType>(S1->getType());
+    VectorType *S2VecTy = dyn_cast<VectorType>(S1->getType());
+    if (S1VecTy->isSubword() && S2VecTy->isSubword()) {
+      SubwordOp = true;
+    }
+  }
+
   Op<0>() = S1;
   Op<1>() = S2;
   setName(Name);
@@ -2253,6 +2296,15 @@ BinaryOperator::BinaryOperator(BinaryOps iType, Value *S1, Value *S2,
                 OperandTraits<BinaryOperator>::op_begin(this),
                 OperandTraits<BinaryOperator>::operands(this),
                 InsertAtEnd) {
+  SubwordOp = false;
+  if (S1->getType()->isVectorTy() && S2->getType()->isVectorTy()) {
+    VectorType *S1VecTy = dyn_cast<VectorType>(S1->getType());
+    VectorType *S2VecTy = dyn_cast<VectorType>(S2->getType());
+    if (S1VecTy->isSubword() && S2VecTy->isSubword()) {
+      SubwordOp = true;
+    }
+  }
+
   Op<0>() = S1;
   Op<1>() = S2;
   setName(Name);
@@ -2262,14 +2314,23 @@ BinaryOperator::BinaryOperator(BinaryOps iType, Value *S1, Value *S2,
 void BinaryOperator::AssertOK() {
   Value *LHS = getOperand(0), *RHS = getOperand(1);
   (void)LHS; (void)RHS; // Silence warnings.
-  assert(LHS->getType() == RHS->getType() &&
-         "Binary operator operand types must match!");
+
+  if (!SubwordOp) {  /* BinaryOperator with Subword operands allows different types */
+    assert(LHS->getType() == RHS->getType() &&
+           "Binary operator operand types must match!");
+  }
 #ifndef NDEBUG
   switch (getOpcode()) {
   case Add: case Sub:
   case Mul:
-    assert(getType() == LHS->getType() &&
-           "Arithmetic operation should return same type as operands!");
+    if (SubwordOp) {
+      // TODO: result type should be the largest one
+      assert((getType() == LHS->getType() || getType() == RHS->getType()) &&
+            "Arithmetic operation should return same type as operands!");
+    } else {
+      assert(getType() == LHS->getType() &&
+            "Arithmetic operation should return same type as operands!");
+    }
     assert(getType()->isIntOrIntVectorTy() &&
            "Tried to create an integer operation on a non-integer type!");
     break;
@@ -2330,8 +2391,30 @@ void BinaryOperator::AssertOK() {
 BinaryOperator *BinaryOperator::Create(BinaryOps Op, Value *S1, Value *S2,
                                        const Twine &Name,
                                        Instruction *InsertBefore) {
-  assert(S1->getType() == S2->getType() &&
+  if (S1->getType()->isVectorTy() && S1->getType()->isVectorTy()) {
+    VectorType *S1VecTy = dyn_cast<VectorType>(S1->getType());
+    VectorType *S2VecTy = dyn_cast<VectorType>(S2->getType());
+    if (S1VecTy->isSubword() && S2VecTy->isSubword()) {
+      // type of the result is bigger type from both operands:
+      unsigned s1sz = S1VecTy->getScalarSizeInBits();
+      unsigned s2sz = S2VecTy->getScalarSizeInBits();
+
+      assert(S1VecTy->getPackSize() == S2VecTy->getPackSize() &&
+         "Cannot create binary operator when subword operands havedifferent packing!");
+
+      Type *ResType = (s2sz>s1sz) ? S2->getType() : S1->getType();
+      return new BinaryOperator(Op, S1, S2, ResType, Name, InsertBefore);
+    }
+    // both are vectors, one is subword and one is normal vector (for initialization)
+    assert( S1->getType()->getVectorNumElements() ==
+            S2->getType()->getVectorNumElements() &&
+            S1->getType()->getVectorElementType() ==
+            S2->getType()->getVectorElementType() &&
+            "Cannot create binary operator with two differing vectors!");
+  } else {
+    assert(S1->getType() == S2->getType() &&
          "Cannot create binary operator with two operands of differing type!");
+  }
   return new BinaryOperator(Op, S1, S2, S1->getType(), Name, InsertBefore);
 }
 
@@ -3197,6 +3280,11 @@ CastInst::castIsValid(Instruction::CastOps op, Value *S, Type *DstTy) {
   unsigned DstLength = DstTy->isVectorTy() ?
     cast<VectorType>(DstTy)->getNumElements() : 0;
 
+  unsigned SrcSubwordLength = SrcTy->getVectorIsSubword() ?
+    cast<VectorType>(SrcTy)->getPackSize() : 100;
+  unsigned DstSubwordLength = DstTy->getVectorIsSubword() ?
+    cast<VectorType>(DstTy)->getPackSize() : 100;
+
   // Switch on the opcode provided
   switch (op) {
   default: return false; // This is an input error
@@ -3248,8 +3336,15 @@ CastInst::castIsValid(Instruction::CastOps op, Value *S, Type *DstTy) {
 
     // For non-pointer cases, the cast is okay if the source and destination bit
     // widths are identical.
-    if (!SrcPtrTy)
+    if (!SrcPtrTy) {
+      if (SrcTy->getVectorIsSubword() && !DstTy->getVectorIsSubword()) { // source is a subword, destination is not
+        return (DstTy->getScalarSizeInBits() == cast<VectorType>(SrcTy)->getBasicType()->getScalarSizeInBits());
+      }
+      if (DstTy->getVectorIsSubword() && !SrcTy->getVectorIsSubword()) { // destination is a subword, source is not
+        return (SrcTy->getScalarSizeInBits() == cast<VectorType>(DstTy)->getBasicType()->getScalarSizeInBits());
+      }
       return SrcTy->getPrimitiveSizeInBits() == DstTy->getPrimitiveSizeInBits();
+    }
 
     // If both are pointers then the address spaces must match.
     if (SrcPtrTy->getAddressSpace() != DstPtrTy->getAddressSpace())
diff --git a/llvm/lib/IR/Type.cpp b/llvm/lib/IR/Type.cpp
index 3eab5042b542..4b1d68db7fdd 100644
--- a/llvm/lib/IR/Type.cpp
+++ b/llvm/lib/IR/Type.cpp
@@ -125,7 +125,11 @@ TypeSize Type::getPrimitiveSizeInBits() const {
     return TypeSize::Fixed(cast<IntegerType>(this)->getBitWidth());
   case Type::VectorTyID: {
     const VectorType *VTy = cast<VectorType>(this);
-    return TypeSize(VTy->getBitWidth(), VTy->isScalable());
+    if (VTy->isSubword()) {
+      unsigned wsz = VTy->getBasicType()->getScalarSizeInBits();
+      return TypeSize::Fixed(wsz); /* return always size of the basic type */
+    } else
+      return TypeSize(VTy->getBitWidth(), VTy->isScalable());
   }
   default: return TypeSize::Fixed(0);
   }
@@ -609,7 +613,8 @@ bool ArrayType::isValidElementType(Type *ElemTy) {
 //===----------------------------------------------------------------------===//
 
 VectorType::VectorType(Type *ElType, ElementCount EC)
-  : SequentialType(VectorTyID, ElType, EC.Min), Scalable(EC.Scalable) {}
+  : SequentialType(VectorTyID, ElType, EC.Min), Scalable(EC.Scalable),
+    Subword(false), BasicType(NULL), SubwordSubTys{NULL,NULL}, signedBasicType(false) {}
 
 VectorType *VectorType::get(Type *ElementType, ElementCount EC) {
   assert(EC.Min > 0 && "#Elements of a VectorType must be greater than 0");
@@ -630,6 +635,33 @@ bool VectorType::isValidElementType(Type *ElemTy) {
     ElemTy->isPointerTy();
 }
 
+
+/* subword specific VectorType - array of Subwords */
+VectorType::VectorType(Type *BasType, Type *ElType, unsigned Packing, bool IsSigned)
+  : SequentialType(VectorTyID, ElType, Packing), Subword(true), BasicType(BasType),
+                   SubwordSubTys{ElType,BasType}, signedBasicType(IsSigned) {
+  /* exchange underlying component types */
+  //ContainedType = getElementType();
+  //BasicType = BasType;
+  ContainedTys = SubwordSubTys;
+  NumContainedTys = 2;
+}
+
+VectorType *VectorType::get(Type *BasicType, Type *ElementType, unsigned Packing, bool IsSigned) {
+  assert(BasicType->isIntegerTy() && ElementType->isIntegerTy() &&
+         "Basic type and Element type must be an integer");
+  unsigned btsz = BasicType->getIntegerBitWidth();
+  unsigned etsz = ElementType->getIntegerBitWidth();
+  unsigned mxpack = btsz/etsz;
+  if (Packing==0) Packing=mxpack;
+  assert((etsz*Packing)<=btsz && "Size of packed elements cannot be greater than"
+                                " size of basic type.");
+
+  LLVMContextImpl *pImpl = BasicType->getContext().pImpl;
+  VectorType *Entry = new (pImpl->Alloc) VectorType(BasicType, ElementType, Packing, IsSigned);
+  return Entry;
+}
+
 //===----------------------------------------------------------------------===//
 //                         PointerType Implementation
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index e3a3d91b455b..284493cf1caa 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -2846,10 +2846,17 @@ void Verifier::visitCallBase(CallBase &Call) {
            "Incorrect number of arguments passed to called function!", Call);
 
   // Verify that all arguments to the call match the function type.
-  for (unsigned i = 0, e = FTy->getNumParams(); i != e; ++i)
+  for (unsigned i = 0, e = FTy->getNumParams(); i != e; ++i) {
+    if (Call.getArgOperand(i)->getType()->getVectorIsSubword()) {
+      VectorType *vty = cast<VectorType>(Call.getArgOperand(i)->getType());
+      Assert(vty->getBasicType() == FTy->getParamType(i),
+             "Call parameter type does not match function signature!",
+            Call.getArgOperand(i), FTy->getParamType(i), Call);
+    } else
     Assert(Call.getArgOperand(i)->getType() == FTy->getParamType(i),
            "Call parameter type does not match function signature!",
            Call.getArgOperand(i), FTy->getParamType(i), Call);
+  }
 
   AttributeList Attrs = Call.getAttributes();
 
@@ -3165,8 +3172,10 @@ void Verifier::visitUnaryOperator(UnaryOperator &U) {
 /// of the same type!
 ///
 void Verifier::visitBinaryOperator(BinaryOperator &B) {
-  Assert(B.getOperand(0)->getType() == B.getOperand(1)->getType(),
-         "Both operands to a binary operator are not of the same type!", &B);
+  if (!B.isSubwordOp()) {
+    Assert(B.getOperand(0)->getType() == B.getOperand(1)->getType(),
+           "Both operands to a binary operator are not of the same type!", &B);
+  }
 
   switch (B.getOpcode()) {
   // Check that integer arithmetic operators are only used with
@@ -3180,10 +3189,17 @@ void Verifier::visitBinaryOperator(BinaryOperator &B) {
   case Instruction::URem:
     Assert(B.getType()->isIntOrIntVectorTy(),
            "Integer arithmetic operators only work with integral types!", &B);
-    Assert(B.getType() == B.getOperand(0)->getType(),
-           "Integer arithmetic operators must have same type "
-           "for operands and result!",
-           &B);
+    if (B.isSubwordOp()) {
+      Assert(B.getType() == B.getOperand(0)->getType() || B.getType() == B.getOperand(1)->getType(),
+             "Integer (subword) arithmetic operators must have same type "
+             "for result and one of operands!",
+             &B);
+    } else {
+      Assert(B.getType() == B.getOperand(0)->getType(),
+             "Integer arithmetic operators must have same type "
+             "for operands and result!",
+             &B);
+    }
     break;
   // Check that floating-point arithmetic operators are only used with
   // floating-point operands.
@@ -3230,11 +3246,13 @@ void Verifier::visitICmpInst(ICmpInst &IC) {
   // Check that the operands are the same type
   Type *Op0Ty = IC.getOperand(0)->getType();
   Type *Op1Ty = IC.getOperand(1)->getType();
-  Assert(Op0Ty == Op1Ty,
-         "Both operands to ICmp instruction are not of the same type!", &IC);
+  //Assert(Op0Ty == Op1Ty,
+         //"Both operands to ICmp instruction are not of the same type!", &IC);
   // Check that the operands are the right type
   Assert(Op0Ty->isIntOrIntVectorTy() || Op0Ty->isPtrOrPtrVectorTy(),
          "Invalid operand types for ICmp instruction", &IC);
+  Assert(Op1Ty->isIntOrIntVectorTy() || Op1Ty->isPtrOrPtrVectorTy(),
+         "Invalid second operand types for ICmp instruction", &IC);
   // Check that the predicate is valid.
   Assert(IC.isIntPredicate(),
          "Invalid predicate in ICmp instruction!", &IC);
@@ -3412,8 +3430,29 @@ void Verifier::visitStoreInst(StoreInst &SI) {
   PointerType *PTy = dyn_cast<PointerType>(SI.getOperand(1)->getType());
   Assert(PTy, "Store operand must be a pointer.", &SI);
   Type *ElTy = PTy->getElementType();
-  Assert(ElTy == SI.getOperand(0)->getType(),
+  if (SI.getOperand(0)->getType()->isVectorTy() &&
+      SI.getOperand(0)->getType()->getVectorIsSubword()) {
+    VectorType *pvt = cast<VectorType>(SI.getOperand(0)->getType());
+
+    if (ElTy->isVectorTy() && ElTy->getVectorIsSubword()) { // both are subwords
+      Assert(ElTy == pvt,
+        "Stored value does not match pointer operand subword type!", pvt, ElTy);
+    } else {
+      Assert(ElTy == pvt->getBasicType(),
+        "Stored value does not match pointer operand subword basic type!", pvt->getBasicType(), ElTy);
+    }
+
+  } else if (ElTy->isVectorTy() && ElTy->getVectorIsSubword()) { // destination is a subword but source is not
+    VectorType *pvt = cast<VectorType>(ElTy);
+    Assert(pvt->getBasicType() == SI.getOperand(0)->getType(),
+      "Stored value does not match pointer operand subword basic type!", pvt->getBasicType(), SI.getOperand(0)->getType());
+
+  } else {
+
+    Assert(ElTy == SI.getOperand(0)->getType(),
          "Stored value type does not match pointer operand type!", &SI, ElTy);
+  }
+
   Assert(SI.getAlignment() <= Value::MaximumAlignment,
          "huge alignment values are unsupported", &SI);
   Assert(ElTy->isSized(), "storing unsized types is not allowed", &SI);
diff --git a/llvm/lib/Support/Triple.cpp b/llvm/lib/Support/Triple.cpp
index d419463e6a5e..df1c51c5c7ab 100644
--- a/llvm/lib/Support/Triple.cpp
+++ b/llvm/lib/Support/Triple.cpp
@@ -167,6 +167,7 @@ StringRef Triple::getVendorTypeName(VendorType Kind) {
   case Mesa: return "mesa";
   case SUSE: return "suse";
   case OpenEmbedded: return "oe";
+  case Daiteq: return "daiteq";
   }
 
   llvm_unreachable("Invalid VendorType!");
@@ -476,6 +477,7 @@ static Triple::VendorType parseVendor(StringRef VendorName) {
     .Case("mesa", Triple::Mesa)
     .Case("suse", Triple::SUSE)
     .Case("oe", Triple::OpenEmbedded)
+    .Case("daiteq", Triple::Daiteq)
     .Default(Triple::UnknownVendor);
 }
 
diff --git a/llvm/lib/Target/Sparc/DelaySlotFiller.cpp b/llvm/lib/Target/Sparc/DelaySlotFiller.cpp
index 7319924a24ba..036361b7b615 100644
--- a/llvm/lib/Target/Sparc/DelaySlotFiller.cpp
+++ b/llvm/lib/Target/Sparc/DelaySlotFiller.cpp
@@ -123,7 +123,9 @@ bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
     // TODO: If we ever want to support v7, this needs to be extended
     // to cover all floating point operations.
     if (!Subtarget->isV9() &&
-        (MI->getOpcode() == SP::FCMPS || MI->getOpcode() == SP::FCMPD
+        (MI->getOpcode() == SP::FCMPH
+         || MI->getOpcode() == SP::FCMPS
+         || MI->getOpcode() == SP::FCMPD
          || MI->getOpcode() == SP::FCMPQ)) {
       BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP));
       Changed = true;
diff --git a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
index bee331874e96..80b8a74ff420 100644
--- a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
+++ b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
@@ -165,6 +165,30 @@ static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst,
   return MCDisassembler::Success;
 }
 
+/* the same as for IntRegs */
+static DecodeStatus DecodeSwarRegsRegisterClass(MCInst &Inst,
+                                               unsigned RegNo,
+                                               uint64_t Address,
+                                               const void *Decoder) {
+  if (RegNo > 31)
+    return MCDisassembler::Fail;
+  unsigned Reg = IntRegDecoderTable[RegNo];
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
+
+static DecodeStatus DecodeHFPRegsRegisterClass(MCInst &Inst,
+                                               unsigned RegNo,
+                                               uint64_t Address,
+                                               const void *Decoder) {
+  if (RegNo > 31)
+    return MCDisassembler::Fail;
+  unsigned Reg = FPRegDecoderTable[RegNo];
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
 
 static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst,
                                               unsigned RegNo,
@@ -204,6 +228,31 @@ static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst,
   return MCDisassembler::Success;
 }
 
+
+static DecodeStatus DecodePFPHRegsRegisterClass(MCInst &Inst,
+                                               unsigned RegNo,
+                                               uint64_t Address,
+                                               const void *Decoder) {
+  if (RegNo > 31)
+    return MCDisassembler::Fail;
+  unsigned Reg = FPRegDecoderTable[RegNo];
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
+
+static DecodeStatus DecodePFPSRegsRegisterClass(MCInst &Inst,
+                                               unsigned RegNo,
+                                               uint64_t Address,
+                                               const void *Decoder) {
+  if (RegNo > 31)
+    return MCDisassembler::Fail;
+  unsigned Reg = DFPRegDecoderTable[RegNo];
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
+
 static DecodeStatus DecodeCPRegsRegisterClass(MCInst &Inst,
                                                unsigned RegNo,
                                                uint64_t Address,
@@ -271,12 +320,20 @@ static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
                                   const void *Decoder);
 static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Address,
                                   const void *Decoder);
+static DecodeStatus DecodeLoadSwar(MCInst &Inst, unsigned insn, uint64_t Address,
+                                  const void *Decoder);
+static DecodeStatus DecodeLoadHFP(MCInst &Inst, unsigned insn, uint64_t Address,
+                                 const void *Decoder);
 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
                                  const void *Decoder);
 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
                                   const void *Decoder);
 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
                                   const void *Decoder);
+static DecodeStatus DecodeLoadPFPH(MCInst &Inst, unsigned insn, uint64_t Address,
+                                 const void *Decoder);
+static DecodeStatus DecodeLoadPFPS(MCInst &Inst, unsigned insn, uint64_t Address,
+                                 const void *Decoder);
 static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address,
                                   const void *Decoder);
 static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address,
@@ -285,12 +342,20 @@ static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
                                    uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn,
                                    uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeStoreSwar(MCInst &Inst, unsigned insn,
+                                   uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeStoreHFP(MCInst &Inst, unsigned insn,
+                                  uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn,
                                   uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
                                    uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
                                    uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeStorePFPH(MCInst &Inst, unsigned insn,
+                                  uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeStorePFPS(MCInst &Inst, unsigned insn,
+                                  uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn,
                                    uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn,
@@ -428,6 +493,18 @@ static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Addr
                    DecodeIntPairRegisterClass);
 }
 
+static DecodeStatus DecodeLoadSwar(MCInst &Inst, unsigned insn, uint64_t Address,
+                                  const void *Decoder) {
+  return DecodeMem(Inst, insn, Address, Decoder, true,
+                   DecodeSwarRegsRegisterClass);
+}
+
+static DecodeStatus DecodeLoadHFP(MCInst &Inst, unsigned insn, uint64_t Address,
+                                 const void *Decoder) {
+  return DecodeMem(Inst, insn, Address, Decoder, true,
+                   DecodeHFPRegsRegisterClass);
+}
+
 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
                                  const void *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, true,
@@ -446,6 +523,18 @@ static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
                    DecodeQFPRegsRegisterClass);
 }
 
+static DecodeStatus DecodeLoadPFPH(MCInst &Inst, unsigned insn, uint64_t Address,
+                                 const void *Decoder) {
+  return DecodeMem(Inst, insn, Address, Decoder, true,
+                   DecodePFPHRegsRegisterClass);
+}
+
+static DecodeStatus DecodeLoadPFPS(MCInst &Inst, unsigned insn, uint64_t Address,
+                                 const void *Decoder) {
+  return DecodeMem(Inst, insn, Address, Decoder, true,
+                   DecodePFPSRegsRegisterClass);
+}
+
 static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address,
                                   const void *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, true,
@@ -470,6 +559,18 @@ static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn,
                    DecodeIntPairRegisterClass);
 }
 
+static DecodeStatus DecodeStoreSwar(MCInst &Inst, unsigned insn,
+                                   uint64_t Address, const void *Decoder) {
+  return DecodeMem(Inst, insn, Address, Decoder, false,
+                   DecodeSwarRegsRegisterClass);
+}
+
+static DecodeStatus DecodeStoreHFP(MCInst &Inst, unsigned insn, uint64_t Address,
+                                  const void *Decoder) {
+  return DecodeMem(Inst, insn, Address, Decoder, false,
+                   DecodeHFPRegsRegisterClass);
+}
+
 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address,
                                   const void *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, false,
@@ -488,6 +589,18 @@ static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
                    DecodeQFPRegsRegisterClass);
 }
 
+static DecodeStatus DecodeStorePFPH(MCInst &Inst, unsigned insn, uint64_t Address,
+                                  const void *Decoder) {
+  return DecodeMem(Inst, insn, Address, Decoder, false,
+                   DecodePFPHRegsRegisterClass);
+}
+
+static DecodeStatus DecodeStorePFPS(MCInst &Inst, unsigned insn, uint64_t Address,
+                                  const void *Decoder) {
+  return DecodeMem(Inst, insn, Address, Decoder, false,
+                   DecodePFPSRegsRegisterClass);
+}
+
 static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn,
                                    uint64_t Address, const void *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, false,
diff --git a/llvm/lib/Target/Sparc/LeonFeatures.td b/llvm/lib/Target/Sparc/LeonFeatures.td
index e0ea4e9c7645..d7aa3f937f9a 100644
--- a/llvm/lib/Target/Sparc/LeonFeatures.td
+++ b/llvm/lib/Target/Sparc/LeonFeatures.td
@@ -61,3 +61,10 @@ def FixAllFDIVSQRT : SubtargetFeature<
 def LeonCycleCounter
   : SubtargetFeature<"leoncyclecounter", "HasLeonCycleCounter", "true",
                      "Use the Leon cycle counter register">;
+
+def InsertNOPYDIV: SubtargetFeature<
+  "insertnopydiv",
+  "InsertNOPYDIV",
+  "true",
+  "LEON2 fix: Insert three NOP instructions between every WRY and SDIV/UDIV instructions"
+>;
diff --git a/llvm/lib/Target/Sparc/LeonPasses.cpp b/llvm/lib/Target/Sparc/LeonPasses.cpp
index e9d3aaeb9cfe..612faec5c4d3 100644
--- a/llvm/lib/Target/Sparc/LeonPasses.cpp
+++ b/llvm/lib/Target/Sparc/LeonPasses.cpp
@@ -155,3 +155,52 @@ bool FixAllFDIVSQRT::runOnMachineFunction(MachineFunction &MF) {
 
   return Modified;
 }
+
+
+//*****************************************************************************
+//**** InsertNOPYDIV pass
+//*****************************************************************************
+// This pass fixes the using of old value from Y register in SDIV/UDIV
+// instruction if the Y register is set immediately before the SDIV/UDIV
+// instruction. Three NOP are inserted before these two instructions.
+// The bug is in the LEON processors at least.
+//
+// This pass inserts three NOP instructions between WRY and SDIV/UDIV
+// instructions.
+//
+char InsertNOPYDIV::ID = 0;
+
+InsertNOPYDIV::InsertNOPYDIV() : LEONMachineFunctionPass(ID) {}
+
+bool InsertNOPYDIV::runOnMachineFunction(MachineFunction &MF) {
+  Subtarget = &MF.getSubtarget<SparcSubtarget>();
+  const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
+  DebugLoc DL = DebugLoc();
+
+  bool Modified = false;
+  for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
+    MachineBasicBlock &MBB = *MFI;
+    for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
+      MachineInstr &MI = *MBBI;
+      unsigned Opcode = MI.getOpcode();
+      unsigned PrevOpcode = 0;
+      if (MBBI!=MBB.begin()) {
+        auto PMBBI = std::prev(MBBI);
+        MachineInstr &PMI = *PMBBI;
+        PrevOpcode = PMI.getOpcode();
+      }
+      /* TO DO: There should be a test for WRY instruction (WRASR with rd=0) and not only for any WRASR. */
+      if ((PrevOpcode == SP::WRASRrr || PrevOpcode == SP::WRASRri) &&
+          (Opcode == SP::SDIVrr || Opcode == SP::SDIVri ||
+           Opcode == SP::UDIVrr || Opcode == SP::UDIVri)) {
+        for (int InsertedCount = 0; InsertedCount < 3; InsertedCount++)
+          BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
+
+        Modified = true;
+      }
+
+    }
+  }
+
+  return Modified;
+}
diff --git a/llvm/lib/Target/Sparc/LeonPasses.h b/llvm/lib/Target/Sparc/LeonPasses.h
index b165bc93780f..fcb3b5918a40 100644
--- a/llvm/lib/Target/Sparc/LeonPasses.h
+++ b/llvm/lib/Target/Sparc/LeonPasses.h
@@ -82,6 +82,19 @@ public:
            "instructions with NOPs and floating-point store";
   }
 };
+
+class LLVM_LIBRARY_VISIBILITY InsertNOPYDIV : public LEONMachineFunctionPass {
+public:
+  static char ID;
+
+  InsertNOPYDIV();
+  bool runOnMachineFunction(MachineFunction &MF) override;
+
+  StringRef getPassName() const override {
+    return "InsertNOPYDIV: insert three NOP instructions between "
+           "every WRY and SDIV/UDIV instructions";
+  }
+};
 } // namespace llvm
 
 #endif // LLVM_LIB_TARGET_SPARC_LEON_PASSES_H
diff --git a/llvm/lib/Target/Sparc/Sparc.td b/llvm/lib/Target/Sparc/Sparc.td
index ca6147edc46b..71f6d99b77a2 100644
--- a/llvm/lib/Target/Sparc/Sparc.td
+++ b/llvm/lib/Target/Sparc/Sparc.td
@@ -62,6 +62,101 @@ def UsePopc : SubtargetFeature<"popc", "UsePopc", "true",
 def FeatureSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
                               "Use software emulation for floating point">;
 
+def FeatureSoftFADDHalf : SubtargetFeature<"soft-fops-half-fadd", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_ADD]", "true",
+           "Use software emulation for FADDh">;
+def FeatureSoftFSUBHalf : SubtargetFeature<"soft-fops-half-fsub", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_SUB]", "true",
+           "Use software emulation for FSUBh">;
+def FeatureSoftFMULHalf : SubtargetFeature<"soft-fops-half-fmul", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_MUL]", "true",
+           "Use software emulation for FMULh">;
+def FeatureSoftFDIVHalf : SubtargetFeature<"soft-fops-half-fdiv", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_DIV]", "true",
+           "Use software emulation for FDIVh">;
+def FeatureSoftFMULEXHalf : SubtargetFeature<"soft-fops-half-fmulex", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_MULEX]", "true",
+           "Use software emulation for FHMULS">;
+def FeatureSoftFSQRTHalf : SubtargetFeature<"soft-fops-half-fsqrt", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_SQRT]", "true",
+           "Use software emulation for FSQRTh">;
+def FeatureSoftFCMPHalf : SubtargetFeature<"soft-fops-half-fcmp", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_CMP]", "true",
+           "Use software emulation for FCMPh, FCMPEh">;
+def FeatureSoftFCI2FHalf : SubtargetFeature<"soft-fops-half-fci2f", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_CI2F]", "true",
+           "Use software emulation for FITOH">;
+def FeatureSoftFCF2IHalf : SubtargetFeature<"soft-fops-half-fcf2i", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_CF2I]", "true",
+           "Use software emulation for FHTOI">;
+def FeatureSoftFCFUPHalf : SubtargetFeature<"soft-fops-half-fcfup", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_CFUP]", "true",
+           "Use software emulation for FHTOS">;
+def FeatureSoftFCFDNHalf : SubtargetFeature<"soft-fops-half-fcfdn", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_CFDN]", "true",
+           "Use software emulation for FHTOS">;
+def FeatureSoftFABSHalf : SubtargetFeature<"soft-fops-half-fabs", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_ABS]", "true",
+           "Use software emulation for FABSh">;
+def FeatureSoftFMOVHalf : SubtargetFeature<"soft-fops-half-fmov", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_MOV]", "true",
+           "Use software emulation for FMOVh">;
+def FeatureSoftFNEGHalf : SubtargetFeature<"soft-fops-half-fneg", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_NEG]", "true",
+           "Use software emulation for FNEGh">;
+
+def FeatureSoftFADDSingle : SubtargetFeature<"soft-fops-single-fadd", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_ADD]", "true",
+           "Use software emulation for FADDs">;
+def FeatureSoftFSUBSingle : SubtargetFeature<"soft-fops-single-fsub", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_SUB]", "true",
+           "Use software emulation for FSUBs">;
+def FeatureSoftFMULSingle : SubtargetFeature<"soft-fops-single-fmul", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_MUL]", "true",
+           "Use software emulation for FMULs">;
+def FeatureSoftFDIVSingle : SubtargetFeature<"soft-fops-single-fdiv", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_DIV]", "true",
+           "Use software emulation for FDIVs">;
+def FeatureSoftFMULEXSingle : SubtargetFeature<"soft-fops-single-fmulex", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_MULEX]", "true",
+           "Use software emulation for FSMULD">;
+def FeatureSoftFSQRTSingle : SubtargetFeature<"soft-fops-single-fsqrt", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_SQRT]", "true",
+           "Use software emulation for FSQRTs">;
+def FeatureSoftFCMPSingle : SubtargetFeature<"soft-fops-single-fcmp", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_CMP]", "true",
+           "Use software emulation for FCMPs, FCMPEs">;
+def FeatureSoftFCI2FSingle : SubtargetFeature<"soft-fops-single-fci2f", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_CI2F]", "true",
+           "Use software emulation for FITOS">;
+def FeatureSoftFCF2ISingle : SubtargetFeature<"soft-fops-single-fcf2i", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_CF2I]", "true",
+           "Use software emulation for FSTOI">;
+def FeatureSoftFCFUPSingle : SubtargetFeature<"soft-fops-single-fcfup", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_CFUP]", "true",
+           "Use software emulation for FSTOD">;
+def FeatureSoftFCFDNSingle : SubtargetFeature<"soft-fops-single-fcfdn", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_CFDN]", "true",
+           "Use software emulation for FSTOH">;
+def FeatureSoftFABSSingle : SubtargetFeature<"soft-fops-single-fabs", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_ABS]", "true",
+           "Use software emulation for FABSs">;
+def FeatureSoftFMOVSingle : SubtargetFeature<"soft-fops-single-fmov", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_MOV]", "true",
+           "Use software emulation for FMOVs">;
+def FeatureSoftFNEGSingle : SubtargetFeature<"soft-fops-single-fneg", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_NEG]", "true",
+           "Use software emulation for FNEGs">;
+
+def FeatureSoftFADDDouble : SubtargetFeature<"soft-fops-double-fadd", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_ADD]", "true",
+           "Use software emulation for FADDd">;
+def FeatureSoftFSUBDouble : SubtargetFeature<"soft-fops-double-fsub", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_SUB]", "true",
+           "Use software emulation for FSUBd">;
+def FeatureSoftFMULDouble : SubtargetFeature<"soft-fops-double-fmul", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_MUL]", "true",
+           "Use software emulation for FMULd">;
+def FeatureSoftFDIVDouble : SubtargetFeature<"soft-fops-double-fdiv", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_DIV]", "true",
+           "Use software emulation for FDIVd">;
+def FeatureSoftFMULEXDouble : SubtargetFeature<"soft-fops-double-fmulex", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_MULEX]", "true",
+           "Use software emulation for FDMULQ">;
+def FeatureSoftFSQRTDouble : SubtargetFeature<"soft-fops-double-fsqrt", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_SQRT]", "true",
+           "Use software emulation for FSQRTd">;
+def FeatureSoftFCMPDouble : SubtargetFeature<"soft-fops-double-fcmp", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_CMP]", "true",
+           "Use software emulation for FCMPd, FCMPEd">;
+def FeatureSoftFCI2FDouble : SubtargetFeature<"soft-fops-double-fci2f", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_CI2F]", "true",
+           "Use software emulation for FITOD">;
+def FeatureSoftFCF2IDouble : SubtargetFeature<"soft-fops-double-fcf2i", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_CF2I]", "true",
+           "Use software emulation for FDTOI">;
+def FeatureSoftFCFUPDouble : SubtargetFeature<"soft-fops-double-fcfup", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_CFUP]", "true",
+           "Use software emulation for FDTOQ">;
+def FeatureSoftFCFDNDouble : SubtargetFeature<"soft-fops-double-fcfdn", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_CFDN]", "true",
+           "Use software emulation for FDTOS">;
+def FeatureSoftFABSDouble : SubtargetFeature<"soft-fops-double-fabs", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_ABS]", "true",
+           "Use software emulation for FABSd">;
+def FeatureSoftFMOVDouble : SubtargetFeature<"soft-fops-double-fmov", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_MOV]", "true",
+           "Use software emulation for FMOVd">;
+def FeatureSoftFNEGDouble : SubtargetFeature<"soft-fops-double-fneg", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_NEG]", "true",
+           "Use software emulation for FNEGd">;
+
+
+def FeaturePackedHalf : SubtargetFeature<"enable-packedhalf", "UseFPPackedHalf", "true",
+           "Use packed half FP type">;
+def FeaturePackedSingle : SubtargetFeature<"enable-packedsingle", "UseFPPackedSingle", "true",
+           "Use packed single FP type">;
+def FeatureUnalignedPackedFP : SubtargetFeature<"unaligned-packed-fp", "AllowUnalignedPackedFP", "true",
+           "Allow unaligned packed FP variables">;
+
 //==== Features added predmoninantly for LEON subtarget support
 include "LeonFeatures.td"
 
@@ -127,17 +222,17 @@ def : Proc<"niagara4",        [FeatureV9, FeatureV8Deprecated, UsePopc,
 
 // LEON 2 FT generic
 def : Processor<"leon2", LEON2Itineraries,
-                [FeatureLeon]>;
+                [FeatureLeon, InsertNOPYDIV]>;
 
 // LEON 2 FT (AT697E)
 // TO DO: Place-holder: Processor specific features will be added *very* soon here.
 def : Processor<"at697e", LEON2Itineraries,
-                [FeatureLeon, InsertNOPLoad]>;
+                [FeatureLeon, InsertNOPLoad, InsertNOPYDIV]>;
 
 // LEON 2 FT (AT697F)
 // TO DO: Place-holder: Processor specific features will be added *very* soon here.
 def : Processor<"at697f", LEON2Itineraries,
-                [FeatureLeon, InsertNOPLoad]>;
+                [FeatureLeon, InsertNOPLoad, InsertNOPYDIV]>;
 
 
 // LEON 3 FT generic
diff --git a/llvm/lib/Target/Sparc/SparcCallingConv.td b/llvm/lib/Target/Sparc/SparcCallingConv.td
index 4be432211f1d..6fb0f531d828 100644
--- a/llvm/lib/Target/Sparc/SparcCallingConv.td
+++ b/llvm/lib/Target/Sparc/SparcCallingConv.td
@@ -17,10 +17,10 @@
 def CC_Sparc32 : CallingConv<[
   // Custom assign SRet to [sp+64].
   CCIfSRet<CCCustom<"CC_Sparc_Assign_SRet">>,
-  // i32 f32 arguments get passed in integer registers if there is space.
-  CCIfType<[i32, f32], CCAssignToReg<[I0, I1, I2, I3, I4, I5]>>,
+  // i32 f16 f32 arguments get passed in integer registers if there is space.
+  CCIfType<[i32, f16, f32], CCAssignToReg<[I0, I1, I2, I3, I4, I5]>>,
   // f64 arguments are split and passed through registers or through stack.
-  CCIfType<[f64], CCCustom<"CC_Sparc_Assign_Split_64">>,
+  CCIfType<[f64, v2f32], CCCustom<"CC_Sparc_Assign_Split_64">>,
   // As are v2i32 arguments (this would be the default behavior for
   // v2i32 if it wasn't allocated to the IntPair register-class)
   CCIfType<[v2i32], CCCustom<"CC_Sparc_Assign_Split_64">>,
@@ -32,8 +32,8 @@ def CC_Sparc32 : CallingConv<[
 
 def RetCC_Sparc32 : CallingConv<[
   CCIfType<[i32], CCAssignToReg<[I0, I1, I2, I3, I4, I5]>>,
-  CCIfType<[f32], CCAssignToReg<[F0, F1, F2, F3]>>,
-  CCIfType<[f64], CCAssignToReg<[D0, D1]>>,
+  CCIfType<[f16, f32, v2f16], CCAssignToReg<[F0, F1, F2, F3]>>,
+  CCIfType<[f64, v2f32], CCAssignToReg<[D0, D1]>>,
   CCIfType<[v2i32], CCCustom<"CC_Sparc_Assign_Ret_Split_64">>
 ]>;
 
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index 4a2ba00ac6c2..3296bed50abc 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -415,7 +415,9 @@ SDValue SparcTargetLowering::LowerFormalArguments_32(
 
     if (VA.isRegLoc()) {
       if (VA.needsCustom()) {
-        assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
+        assert(VA.getLocVT() == MVT::f64 ||
+               VA.getLocVT() == MVT::v2i32 ||
+               VA.getLocVT() == MVT::v2f32);
 
         Register VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
         MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
@@ -448,9 +450,12 @@ SDValue SparcTargetLowering::LowerFormalArguments_32(
       Register VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
       MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
       SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
-      if (VA.getLocVT() == MVT::f32)
+      if (VA.getLocVT() == MVT::f16) {
+        Arg = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Arg);
+        Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f16, Arg);
+      } else if (VA.getLocVT() == MVT::f32) {
         Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
-      else if (VA.getLocVT() != MVT::i32) {
+      } else if (VA.getLocVT() != MVT::i32) {
         Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg,
                           DAG.getValueType(VA.getLocVT()));
         Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg);
@@ -465,7 +470,9 @@ SDValue SparcTargetLowering::LowerFormalArguments_32(
     auto PtrVT = getPointerTy(DAG.getDataLayout());
 
     if (VA.needsCustom()) {
-      assert(VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::v2i32);
+      assert(VA.getValVT() == MVT::f64 ||
+             VA.getValVT() == MVT::v2i32 ||
+             VA.getValVT() == MVT::v2f32);
       // If it is double-word aligned, just load.
       if (Offset % 8 == 0) {
         int FI = MF.getFrameInfo().CreateFixedObject(8,
@@ -507,11 +514,16 @@ SDValue SparcTargetLowering::LowerFormalArguments_32(
                                                  true);
     SDValue FIPtr = DAG.getFrameIndex(FI, PtrVT);
     SDValue Load ;
-    if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) {
+    if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32 ||
+        VA.getValVT() == MVT::f16) {
       Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, MachinePointerInfo());
     } else if (VA.getValVT() == MVT::f128) {
       report_fatal_error("SPARCv8 does not handle f128 in calls; "
                          "pass indirectly");
+    } else if (VA.getValVT() == MVT::v2f16) {
+      Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, MachinePointerInfo());
+    } else if (VA.getValVT() == MVT::v2f32) {
+      Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, MachinePointerInfo());
     } else {
       // We shouldn't see any other value types here.
       llvm_unreachable("Unexpected ValVT encountered in frame lowering.");
@@ -834,7 +846,9 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
     }
 
     if (VA.needsCustom()) {
-      assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
+      assert(VA.getLocVT() == MVT::f64 ||
+             VA.getLocVT() == MVT::v2i32 ||
+             VA.getLocVT()==MVT::v2f32);
 
       if (VA.isMemLoc()) {
         unsigned Offset = VA.getLocMemOffset() + StackOffset;
@@ -853,9 +867,11 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
         // Move from the float value from float registers into the
         // integer registers.
         if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Arg))
-          Arg = bitcastConstantFPToInt(C, dl, DAG);
+          Arg = bitcastConstantFPToInt64(C, dl, DAG);
         else
           Arg = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, Arg);
+      } else if (VA.getLocVT() == MVT::v2f32) {
+        Arg = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, Arg);
       }
 
       SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
@@ -900,11 +916,23 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
     // Arguments that can be passed on register must be kept at
     // RegsToPass vector
     if (VA.isRegLoc()) {
-      if (VA.getLocVT() != MVT::f32) {
+      if (VA.getLocVT() == MVT::f16) {
+        // store f16 and load it as i32 (and shift to LSB
+        MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
+        int FI = MFI.CreateStackObject(4, 4, false);
+        SDValue FIPtr = DAG.getFrameIndex(FI, MVT::i32); // getPointerTy(DAG.getDataLayout()));
+        MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIPtr, MachinePointerInfo()));
+        SDValue NArg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, MachinePointerInfo());
+        NArg = DAG.getNode(ISD::SRL, dl, MVT::i32, NArg, DAG.getConstant(16, dl, MVT::i32));
+        RegsToPass.push_back(std::make_pair(VA.getLocReg(), NArg));
+        continue;
+      } else
+      if (VA.getLocVT() == MVT::f32 || VA.getLocVT() == MVT::v2f16) {
+        Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
         RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
         continue;
       }
-      Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
+      // all types others than custom (i64/f64,v2i32), f16, f32, v2f16
       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
       continue;
     }
@@ -1377,7 +1405,7 @@ static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
   }
 }
 
-/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
+/// FPCondCCodeToFCC - Convert a DAG floating point condition code to a SPARC
 /// FCC condition.
 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
   switch (CC) {
@@ -1420,11 +1448,35 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
 
   // Set up the register classes.
   addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
-  if (!Subtarget->useSoftFloat()) {
+
+  if (!Subtarget->useSoftFloat() &&
+     (Subtarget->useHardHalf() || Subtarget->useHardSingle() ||
+      Subtarget->useHardDouble())) {
+    addRegisterClass(MVT::f16, &SP::HFPRegsRegClass);
     addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
     addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
     addRegisterClass(MVT::f128, &SP::QFPRegsRegClass);
+    if (Subtarget->usePackedHalf())
+      addRegisterClass(MVT::v2f16, &SP::PFPHRegsRegClass);
+    if (Subtarget->usePackedSingle())
+      addRegisterClass(MVT::v2f32, &SP::PFPSRegsRegClass);
+  }
+
+/* TODO: option for enabling swar */
+  for (MVT VT : MVT::subword_vector_valuetypes()) {
+    addRegisterClass(VT, &SP::SwarRegsRegClass);
+    setOperationAction(ISD::LOAD, VT, Legal);
+    setOperationAction(ISD::STORE, VT, Legal);
+
+    setOperationAction(ISD::ADD, VT, Custom);
+    setOperationAction(ISD::SUB, VT, Custom);
+    setOperationAction(ISD::MUL, VT, Custom);
+    setOperationAction(ISD::BITCAST, VT, Expand);
+    setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);  /* vs1p32-vs16p32 = insert(svec, selm, const idx) or (svec, const i32, const idx) */
+    setOperationAction(ISD::BUILD_VECTOR, VT, Custom);  /* vs1p32-vs16p32 = build_vector(svec, selm, const idx) or (svec, const i32, const idx) */
+    setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);  /* vs1p32-vs16p32 = extract(svec, selm, const idx) or (svec, const i32, const idx) */
   }
+
   if (Subtarget->is64Bit()) {
     addRegisterClass(MVT::i64, &SP::I64RegsRegClass);
   } else {
@@ -1465,8 +1517,31 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
     //    AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
   }
 
+  // daiteq
+  if (Subtarget->usePackedHalf()) {
+    setOperationAction(ISD::LOAD, MVT::v2f16, Legal);
+    setOperationAction(ISD::STORE, MVT::v2f16, Legal);
+    setTruncStoreAction(MVT::v2f16, MVT::f32, Expand);
+    setTruncStoreAction(MVT::f32, MVT::v2f16, Expand);
+    setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom); /* use different operations for each element */
+    setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f16, Custom);  /* v2f16 = insert(v2f16, f16, const idx) */
+    setOperationAction(ISD::BUILD_VECTOR, MVT::v2f16, Custom);
+    setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f16, Expand);
+  }
+
+  if (Subtarget->usePackedSingle()) {
+    setOperationAction(ISD::LOAD, MVT::v2f32, Custom);
+    setOperationAction(ISD::STORE, MVT::v2f32, Custom);
+    setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f32, Legal);
+    setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Legal);
+    setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Legal);
+    setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f32, Expand);
+  }
+
+
   // Turn FP extload into load/fpextend
   for (MVT VT : MVT::fp_valuetypes()) {
+    setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
     setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
     setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
   }
@@ -1476,6 +1551,8 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
 
   // Turn FP truncstore into trunc + store.
+  setTruncStoreAction(MVT::f32, MVT::f16, Expand);
+  setTruncStoreAction(MVT::f64, MVT::f16, Expand);
   setTruncStoreAction(MVT::f64, MVT::f32, Expand);
   setTruncStoreAction(MVT::f128, MVT::f32, Expand);
   setTruncStoreAction(MVT::f128, MVT::f64, Expand);
@@ -1505,6 +1582,13 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
   }
 
+  // Custom expand fp<->fp16
+  // Lower f16 conversion operations into library calls
+  setOperationAction(ISD::FP16_TO_FP,        MVT::f32,   Expand);
+  setOperationAction(ISD::FP_TO_FP16,        MVT::f32,   Expand);
+  setOperationAction(ISD::FP16_TO_FP,        MVT::f64,   Expand);
+  setOperationAction(ISD::FP_TO_FP16,        MVT::f64,   Expand);
+
   // Custom expand fp<->sint
   setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
   setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
@@ -1517,16 +1601,21 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
   setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
 
+  setOperationAction(ISD::BITCAST, MVT::f16, Custom);
+  setOperationAction(ISD::BITCAST, MVT::i16, Expand);
   setOperationAction(ISD::BITCAST, MVT::f32, Expand);
   setOperationAction(ISD::BITCAST, MVT::i32, Expand);
+  setOperationAction(ISD::BITCAST, MVT::f64, Expand);
 
   // Sparc has no select or setcc: expand to SELECT_CC.
   setOperationAction(ISD::SELECT, MVT::i32, Expand);
+  setOperationAction(ISD::SELECT, MVT::f16, Expand);
   setOperationAction(ISD::SELECT, MVT::f32, Expand);
   setOperationAction(ISD::SELECT, MVT::f64, Expand);
   setOperationAction(ISD::SELECT, MVT::f128, Expand);
 
   setOperationAction(ISD::SETCC, MVT::i32, Expand);
+  setOperationAction(ISD::SETCC, MVT::f16, Expand);
   setOperationAction(ISD::SETCC, MVT::f32, Expand);
   setOperationAction(ISD::SETCC, MVT::f64, Expand);
   setOperationAction(ISD::SETCC, MVT::f128, Expand);
@@ -1536,11 +1625,13 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::BRIND, MVT::Other, Expand);
   setOperationAction(ISD::BR_JT, MVT::Other, Expand);
   setOperationAction(ISD::BR_CC, MVT::i32, Custom);
+  setOperationAction(ISD::BR_CC, MVT::f16, Custom);
   setOperationAction(ISD::BR_CC, MVT::f32, Custom);
   setOperationAction(ISD::BR_CC, MVT::f64, Custom);
   setOperationAction(ISD::BR_CC, MVT::f128, Custom);
 
   setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
+  setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
   setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
   setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
   setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
@@ -1788,14 +1879,227 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
   if (Subtarget->fixAllFDIVSQRT()) {
     // Promote FDIVS and FSQRTS to FDIVD and FSQRTD instructions instead as
     // the former instructions generate errata on LEON processors.
-    setOperationAction(ISD::FDIV, MVT::f32, Promote);
-    setOperationAction(ISD::FSQRT, MVT::f32, Promote);
+    if (Subtarget->useSoftFopDouble(SoftFops::SOFTFP_DIV) &&
+       !Subtarget->useSoftFopSingle(SoftFops::SOFTFP_DIV)) {
+      setOperationAction(ISD::FDIV, MVT::f32, Promote);
+    }
+
+    if (Subtarget->useSoftFopDouble(SoftFops::SOFTFP_SQRT) &&
+       !Subtarget->useSoftFopSingle(SoftFops::SOFTFP_SQRT)) {
+      setOperationAction(ISD::FSQRT, MVT::f32, Promote);
+    }
   }
 
   if (Subtarget->hasNoFMULS()) {
     setOperationAction(ISD::FMUL, MVT::f32, Promote);
   }
 
+  if (Subtarget->usePackedHalf())
+    setOperationAction(ISD::BITCAST, MVT::v2f16, Expand);
+
+  if (Subtarget->usePackedSingle())
+    setOperationAction(ISD::BITCAST, MVT::v2f32, Expand);
+
+  if (Subtarget->useSoftFopHalf(SoftFops::SOFTFP_ADD)) {
+    setOperationAction(ISD::FADD, MVT::f16, Custom);
+  } else {
+    setOperationAction(ISD::FADD, MVT::f16, Legal);
+  }
+
+  if (!Subtarget->useSoftFopHalf(SoftFops::SOFTFP_ADD) &&
+        Subtarget->usePackedHalf())
+    setOperationAction(ISD::FADD,  MVT::v2f16, Legal);
+  else
+    setOperationAction(ISD::FADD,  MVT::v2f16, Custom);
+
+  if (Subtarget->useSoftFopHalf(SoftFops::SOFTFP_SUB))
+    setOperationAction(ISD::FSUB, MVT::f16, Custom);
+  else
+    setOperationAction(ISD::FSUB,  MVT::f16, Legal);
+
+  if (!Subtarget->useSoftFopHalf(SoftFops::SOFTFP_SUB) &&
+        Subtarget->usePackedHalf())
+    setOperationAction(ISD::FSUB,  MVT::v2f16, Legal);
+  else
+    setOperationAction(ISD::FSUB,  MVT::v2f16, Custom);
+
+  if (Subtarget->useSoftFopHalf(SoftFops::SOFTFP_MUL))
+    setOperationAction(ISD::FMUL, MVT::f16, Custom);
+  else
+    setOperationAction(ISD::FMUL, MVT::f16, Legal);
+
+  if (!Subtarget->useSoftFopHalf(SoftFops::SOFTFP_MUL) &&
+        Subtarget->usePackedHalf())
+    setOperationAction(ISD::FMUL,  MVT::v2f16, Legal);
+  else
+    setOperationAction(ISD::FMUL,  MVT::v2f16, Custom);
+
+  if (Subtarget->useSoftFopHalf(SoftFops::SOFTFP_DIV))
+    setOperationAction(ISD::FDIV, MVT::f16, Custom);
+  else
+    setOperationAction(ISD::FDIV, MVT::f16, Legal);
+
+  if (!Subtarget->useSoftFopHalf(SoftFops::SOFTFP_DIV) &&
+        Subtarget->usePackedHalf())
+    setOperationAction(ISD::FDIV,  MVT::v2f16, Legal);
+  else
+    setOperationAction(ISD::FDIV,  MVT::v2f16, Custom);
+
+  if (Subtarget->useSoftFopHalf(SoftFops::SOFTFP_SQRT))
+    setOperationAction(ISD::FSQRT, MVT::f16, Custom);
+  else
+    setOperationAction(ISD::FSQRT, MVT::f16, Legal);
+
+  if (!Subtarget->useSoftFopHalf(SoftFops::SOFTFP_SQRT) &&
+        Subtarget->usePackedHalf())
+    setOperationAction(ISD::FSQRT,  MVT::v2f16, Legal);
+  else
+    setOperationAction(ISD::FSQRT,  MVT::v2f16, Custom);
+
+  if (Subtarget->useSoftFopHalf(SoftFops::SOFTFP_CFUP) ||
+      Subtarget->useSoftFopSingle(SoftFops::SOFTFP_CFDN)) {
+    setOperationAction(ISD::FP_EXTEND, MVT::f32, Custom);
+    setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
+  }
+  if (Subtarget->useSoftFopSingle(SoftFops::SOFTFP_CFUP) ||
+      Subtarget->useSoftFopDouble(SoftFops::SOFTFP_CFDN)) {
+    setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
+    setOperationAction(ISD::FP_ROUND,  MVT::f32, Custom);
+  }
+  setOperationAction(ISD::FP_ROUND,  MVT::f64, Custom);
+
+  if (Subtarget->useSoftFopHalf(SoftFops::SOFTFP_CFUP) ||
+      Subtarget->useSoftFopDouble(SoftFops::SOFTFP_CFDN)) {
+    setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
+    setOperationAction(ISD::FP_ROUND,  MVT::f16, Custom);
+  } else {
+    setOperationAction(ISD::FP_ROUND,  MVT::f16, Custom);
+  }
+
+
+  if (Subtarget->useSoftFopHalf(SoftFops::SOFTFP_ABS))
+    setOperationAction(ISD::FABS, MVT::f16, Custom);
+  else
+    setOperationAction(ISD::FABS, MVT::f16, Legal);
+  if (!Subtarget->useSoftFopHalf(SoftFops::SOFTFP_ABS) &&
+       Subtarget->usePackedHalf())
+    setOperationAction(ISD::FABS, MVT::v2f16, Legal);
+  else
+    setOperationAction(ISD::FABS, MVT::v2f16, Expand);
+
+  if (Subtarget->useSoftFopHalf(SoftFops::SOFTFP_NEG))
+    setOperationAction(ISD::FNEG, MVT::f16, Custom);
+  else
+    setOperationAction(ISD::FNEG, MVT::f16, Legal);
+  if (!Subtarget->useSoftFopHalf(SoftFops::SOFTFP_NEG) &&
+       Subtarget->usePackedHalf())
+    setOperationAction(ISD::FNEG, MVT::v2f16, Legal);
+  else
+    setOperationAction(ISD::FNEG, MVT::v2f16, Expand);
+
+  setOperationAction(ISD::FFLOOR, MVT::f16, Promote);
+  setOperationAction(ISD::FFLOOR, MVT::f32, Promote);
+  setOperationAction(ISD::FFLOOR, MVT::v2f16, Promote);
+  setOperationAction(ISD::FFLOOR, MVT::v2f32, Promote);
+
+  if (Subtarget->useSoftFopSingle(SoftFops::SOFTFP_ABS))
+    setOperationAction(ISD::FABS, MVT::f32, Custom);
+  else
+    setOperationAction(ISD::FABS, MVT::f32, Legal);
+
+  if (Subtarget->useSoftFopSingle(SoftFops::SOFTFP_NEG))
+    setOperationAction(ISD::FNEG, MVT::f32, Custom);
+  else
+    setOperationAction(ISD::FNEG, MVT::f32, Legal);
+
+  if (Subtarget->useSoftFopSingle(SoftFops::SOFTFP_ADD))
+    setOperationAction(ISD::FADD, MVT::f32, Custom);
+  else
+    setOperationAction(ISD::FADD, MVT::f32, Legal);
+
+  if (!Subtarget->useSoftFopSingle(SoftFops::SOFTFP_ADD) &&
+        Subtarget->usePackedSingle())
+    setOperationAction(ISD::FADD,  MVT::v2f32, Legal);
+  else
+    setOperationAction(ISD::FADD,  MVT::v2f32, Custom);
+
+  if (Subtarget->useSoftFopSingle(SoftFops::SOFTFP_SUB))
+    setOperationAction(ISD::FSUB, MVT::f32, Custom);
+  else
+    setOperationAction(ISD::FSUB, MVT::f32, Legal);
+
+  if (!Subtarget->useSoftFopSingle(SoftFops::SOFTFP_SUB) &&
+        Subtarget->usePackedSingle())
+    setOperationAction(ISD::FSUB,  MVT::v2f32, Legal);
+  else
+    setOperationAction(ISD::FSUB,  MVT::v2f32, Custom);
+
+  if (Subtarget->useSoftFopSingle(SoftFops::SOFTFP_MUL))
+    setOperationAction(ISD::FMUL, MVT::f32, Custom);
+  else
+    setOperationAction(ISD::FMUL, MVT::f32, Legal);
+
+  if (!Subtarget->useSoftFopSingle(SoftFops::SOFTFP_MUL) &&
+        Subtarget->usePackedSingle())
+    setOperationAction(ISD::FMUL,  MVT::v2f32, Legal);
+  else
+    setOperationAction(ISD::FMUL,  MVT::v2f32, Custom);
+
+  if (Subtarget->useSoftFopSingle(SoftFops::SOFTFP_DIV))
+    setOperationAction(ISD::FDIV, MVT::f32, Custom);
+  else
+    setOperationAction(ISD::FDIV, MVT::f32, Legal);
+
+  if (!Subtarget->useSoftFopSingle(SoftFops::SOFTFP_DIV) &&
+        Subtarget->usePackedSingle())
+    setOperationAction(ISD::FDIV,  MVT::v2f32, Legal);
+  else
+    setOperationAction(ISD::FDIV,  MVT::v2f32, Custom);
+
+  if (Subtarget->useSoftFopSingle(SoftFops::SOFTFP_SQRT))
+    setOperationAction(ISD::FSQRT, MVT::f32, Custom);
+  else
+    setOperationAction(ISD::FSQRT, MVT::f32, Legal);
+
+  if (!Subtarget->useSoftFopSingle(SoftFops::SOFTFP_SQRT) &&
+        Subtarget->usePackedSingle())
+    setOperationAction(ISD::FSQRT,  MVT::v2f32, Legal);
+  else
+    setOperationAction(ISD::FSQRT,  MVT::v2f32, Custom);
+
+//  if (Subtarget->useSoftFopSingle(SoftFops::SOFTFP_CMP))
+
+//  if (Subtarget->useSoftFopSingle(SoftFops::SOFTFP_MULEX))
+//    setOperationAction(ISD::FMUL, MVT::f32, Custom);
+
+//  if (Subtarget->useSoftFopSingle(SoftFops::SOFTFP_CI2F))
+//  if (Subtarget->useSoftFopSingle(SoftFops::SOFTFP_CF2I))
+
+  setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
+  if (Subtarget->useSoftFopSingle(SoftFops::SOFTFP_CFUP) ||
+      Subtarget->useSoftFopSingle(SoftFops::SOFTFP_CFDN)) {
+    setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
+  }
+
+  // --
+  if (Subtarget->useSoftFopDouble(SoftFops::SOFTFP_ADD))
+    setOperationAction(ISD::FADD, MVT::f64, Custom);
+  if (Subtarget->useSoftFopDouble(SoftFops::SOFTFP_SUB))
+    setOperationAction(ISD::FSUB, MVT::f64, Custom);
+  if (Subtarget->useSoftFopDouble(SoftFops::SOFTFP_MUL))
+    setOperationAction(ISD::FMUL, MVT::f64, Custom);
+  if (Subtarget->useSoftFopDouble(SoftFops::SOFTFP_DIV))
+    setOperationAction(ISD::FDIV, MVT::f64, Custom);
+  if (Subtarget->useSoftFopDouble(SoftFops::SOFTFP_SQRT))
+    setOperationAction(ISD::FSQRT, MVT::f64, Custom);
+
+//  if (Subtarget->useSoftFopDouble(SoftFops::SOFTFP_MULEX))
+//  if (Subtarget->useSoftFopDouble(SoftFops::SOFTFP_CMP))
+
+
+
+
+
   // Custom combine bitcast between f64 and v2i32
   if (!Subtarget->is64Bit())
     setTargetDAGCombine(ISD::BITCAST);
@@ -1814,6 +2118,33 @@ bool SparcTargetLowering::useSoftFloat() const {
   return Subtarget->useSoftFloat();
 }
 
+bool SparcTargetLowering::isHalfFopSoft(unsigned softfp) const {
+  return Subtarget->useSoftFopHalf(softfp);
+}
+bool SparcTargetLowering::isSingleFopSoft(unsigned softfp) const {
+  return Subtarget->useSoftFopSingle(softfp);
+}
+bool SparcTargetLowering::isDoubleFopSoft(unsigned softfp) const {
+  return Subtarget->useSoftFopDouble(softfp);
+}
+
+bool SparcTargetLowering::isAnySoftHalf() const {
+  return Subtarget->useSoftHalf();
+}
+bool SparcTargetLowering::isAnySingle() const {
+  return Subtarget->useSoftSingle();
+}
+bool SparcTargetLowering::isAnySoftDouble() const {
+  return Subtarget->useSoftDouble();
+}
+bool SparcTargetLowering::isPackedHalf() const {
+  return Subtarget->usePackedHalf();
+}
+bool SparcTargetLowering::isPackedSingle() const {
+  return Subtarget->usePackedSingle();
+}
+
+
 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
   switch ((SPISD::NodeType)Opcode) {
   case SPISD::FIRST_NUMBER:    break;
@@ -1838,6 +2169,20 @@ const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case SPISD::TLS_ADD:         return "SPISD::TLS_ADD";
   case SPISD::TLS_LD:          return "SPISD::TLS_LD";
   case SPISD::TLS_CALL:        return "SPISD::TLS_CALL";
+  case SPISD::PACKINSHI:       return "SPISD::PACKINSHI";
+  case SPISD::PACKINSLO:       return "SPISD::PACKINSLO";
+  case SPISD::PACKEXT:         return "SPISD::PACKEXT";
+  case SPISD::SWAR:            return "SPISD::SWAR";
+  case SPISD::SWARCC:          return "SPISD::SWARACC";
+  case SPISD::SWARCTRL:        return "SPISD::SWARCTRL";
+  case SPISD::SWAPPH:          return "SPISD::SWAPPH";
+  case SPISD::MOVVUU:          return "SPISD::MOVVUU";
+  case SPISD::MOVVLL:          return "SPISD::MOVVLL";
+  case SPISD::MOVVUL:          return "SPISD::MOVVUL";
+  case SPISD::MOVVLU:          return "SPISD::MOVVLU";
+  case SPISD::MOVVZL:          return "SPISD::MOVVZL";
+  case SPISD::MOVVZU:          return "SPISD::MOVVZU";
+  case SPISD::ANDCC:           return "SPISD::ANDCC";
   }
   return nullptr;
 }
@@ -2117,6 +2462,75 @@ SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op,
                      DAG.getRegister(SP::G7, PtrVT), Offset);
 }
 
+/* universal function based on LowerF128Op */
+SDValue SparcTargetLowering::LowerFloatOp(SDValue Op, SelectionDAG &DAG,
+                            const char *LibFuncName, unsigned numArgs) const {
+  ArgListTy Args;
+
+  MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
+  auto PtrVT = getPointerTy(DAG.getDataLayout());
+
+  SDValue Callee = DAG.getExternalSymbol(LibFuncName, PtrVT);
+  Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext());
+  Type *RetTyABI = RetTy;
+  SDValue Chain = DAG.getEntryNode();
+  SDValue RetPtr;
+
+  // Create a Stack Object to receive the return value of type f128.
+  ArgListEntry Entry;
+  int RetFI;
+  switch (RetTy->getTypeID()) {
+    case Type::HalfTyID:
+      RetFI = MFI.CreateStackObject(2, 4, false);
+      break;
+    case Type::FloatTyID:
+      RetFI = MFI.CreateStackObject(4, 4, false);
+      break;
+    case Type::DoubleTyID:
+      RetFI = MFI.CreateStackObject(8, 8, false);
+      break;
+    default:
+      llvm_unreachable("Sparc LowerFloatOp RetTp!");
+  }
+  RetPtr = DAG.getFrameIndex(RetFI, PtrVT);
+  Entry.Node = RetPtr;
+  Entry.Ty   = PointerType::getUnqual(RetTy);
+  Entry.IsReturned = false;
+  Args.push_back(Entry);
+  RetTyABI = Type::getVoidTy(*DAG.getContext());
+
+  assert(Op->getNumOperands() >= numArgs && "Not enough operands!");
+  for (unsigned i = 0, e = numArgs; i != e; ++i) {
+    Chain = LowerF128_LibCallArg(Chain, Args, Op.getOperand(i), SDLoc(Op), DAG);
+  }
+  TargetLowering::CallLoweringInfo CLI(DAG);
+  CLI.setDebugLoc(SDLoc(Op)).setChain(Chain)
+    .setCallee(CallingConv::C, RetTyABI, Callee, std::move(Args));
+
+  std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
+
+  // chain is in second result.
+  if (RetTyABI == RetTy)
+    return CallInfo.first;
+
+  Chain = CallInfo.second;
+
+  // Load RetPtr to get the return value.
+    switch (RetTy->getTypeID()) {
+      case Type::HalfTyID:
+      case Type::FloatTyID:
+        return DAG.getLoad(Op.getValueType(), SDLoc(Op), Chain, RetPtr,
+                     MachinePointerInfo(), /* Alignment = */ 4);
+        break;
+      case Type::DoubleTyID:
+        return DAG.getLoad(Op.getValueType(), SDLoc(Op), Chain, RetPtr,
+                     MachinePointerInfo(), /* Alignment = */ 8);
+        break;
+      default:
+        llvm_unreachable("Sparc LowerFloatOp RetTp!");
+    }
+}
+
 SDValue SparcTargetLowering::LowerF128_LibCallArg(SDValue Chain,
                                                   ArgListTy &Args, SDValue Arg,
                                                   const SDLoc &DL,
@@ -2201,23 +2615,82 @@ SDValue SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS,
                                               SelectionDAG &DAG) const {
 
   const char *LibCall = nullptr;
-  bool is64Bit = Subtarget->is64Bit();
-  switch(SPCC) {
-  default: llvm_unreachable("Unhandled conditional code!");
-  case SPCC::FCC_E  : LibCall = is64Bit? "_Qp_feq" : "_Q_feq"; break;
-  case SPCC::FCC_NE : LibCall = is64Bit? "_Qp_fne" : "_Q_fne"; break;
-  case SPCC::FCC_L  : LibCall = is64Bit? "_Qp_flt" : "_Q_flt"; break;
-  case SPCC::FCC_G  : LibCall = is64Bit? "_Qp_fgt" : "_Q_fgt"; break;
-  case SPCC::FCC_LE : LibCall = is64Bit? "_Qp_fle" : "_Q_fle"; break;
-  case SPCC::FCC_GE : LibCall = is64Bit? "_Qp_fge" : "_Q_fge"; break;
-  case SPCC::FCC_UL :
-  case SPCC::FCC_ULE:
-  case SPCC::FCC_UG :
-  case SPCC::FCC_UGE:
-  case SPCC::FCC_U  :
-  case SPCC::FCC_O  :
-  case SPCC::FCC_LG :
-  case SPCC::FCC_UE : LibCall = is64Bit? "_Qp_cmp" : "_Q_cmp"; break;
+  EVT lhsVT = LHS.getValueType();
+  if (lhsVT==MVT::f16) {
+    switch(SPCC) {
+    default: llvm_unreachable("Unhandled F16 conditional code!");
+    case SPCC::FCC_E  : LibCall = "__eqhf2"; break;
+    case SPCC::FCC_NE : LibCall = "__nehf2"; break;
+    case SPCC::FCC_L  : LibCall = "__lthf2"; break;
+    case SPCC::FCC_G  : LibCall = "__gthf2"; break;
+    case SPCC::FCC_LE : LibCall = "__lehf2"; break;
+    case SPCC::FCC_GE : LibCall = "__gehf2"; break;
+    case SPCC::FCC_UL :
+    case SPCC::FCC_ULE:
+    case SPCC::FCC_UG :
+    case SPCC::FCC_UGE:
+    case SPCC::FCC_U  :
+    case SPCC::FCC_O  :
+    case SPCC::FCC_LG :
+    case SPCC::FCC_UE : LibCall = "_H_cmp"; break;
+    }
+  } else if (lhsVT==MVT::f32) {
+    switch(SPCC) {
+    default: llvm_unreachable("Unhandled F32 conditional code!");
+    case SPCC::FCC_E  : LibCall = getLibcallName(RTLIB::OEQ_F32); break;
+    case SPCC::FCC_NE : LibCall = getLibcallName(RTLIB::UNE_F32); break;
+    case SPCC::FCC_L  : LibCall = getLibcallName(RTLIB::OLT_F32); break;
+    case SPCC::FCC_G  : LibCall = getLibcallName(RTLIB::OGT_F32); break;
+    case SPCC::FCC_LE : LibCall = getLibcallName(RTLIB::OLE_F32); break;
+    case SPCC::FCC_GE : LibCall = getLibcallName(RTLIB::OGE_F32); break;
+    case SPCC::FCC_UL :
+    case SPCC::FCC_ULE:
+    case SPCC::FCC_UG :
+    case SPCC::FCC_UGE:
+    case SPCC::FCC_U  :
+    case SPCC::FCC_O  :
+    case SPCC::FCC_LG :
+    case SPCC::FCC_UE : LibCall = "_S_cmp"; break;
+    }
+  } else if (lhsVT==MVT::f64) {
+    switch(SPCC) {
+    default: llvm_unreachable("Unhandled F64 conditional code!");
+    case SPCC::FCC_E  : LibCall = getLibcallName(RTLIB::OEQ_F64); break;
+    case SPCC::FCC_NE : LibCall = getLibcallName(RTLIB::UNE_F64); break;
+    case SPCC::FCC_L  : LibCall = getLibcallName(RTLIB::OLT_F64); break;
+    case SPCC::FCC_G  : LibCall = getLibcallName(RTLIB::OGT_F64); break;
+    case SPCC::FCC_LE : LibCall = getLibcallName(RTLIB::OLE_F64); break;
+    case SPCC::FCC_GE : LibCall = getLibcallName(RTLIB::OGE_F64); break;
+    case SPCC::FCC_UL :
+    case SPCC::FCC_ULE:
+    case SPCC::FCC_UG :
+    case SPCC::FCC_UGE:
+    case SPCC::FCC_U  :
+    case SPCC::FCC_O  :
+    case SPCC::FCC_LG :
+    case SPCC::FCC_UE : LibCall = "_D_cmp"; break;
+    }
+  } else if (lhsVT==MVT::f128) {
+    bool is64Bit = Subtarget->is64Bit();
+    switch(SPCC) {
+    default: llvm_unreachable("Unhandled conditional code!");
+    case SPCC::FCC_E  : LibCall = is64Bit? "_Qp_feq" : "_Q_feq"; break;
+    case SPCC::FCC_NE : LibCall = is64Bit? "_Qp_fne" : "_Q_fne"; break;
+    case SPCC::FCC_L  : LibCall = is64Bit? "_Qp_flt" : "_Q_flt"; break;
+    case SPCC::FCC_G  : LibCall = is64Bit? "_Qp_fgt" : "_Q_fgt"; break;
+    case SPCC::FCC_LE : LibCall = is64Bit? "_Qp_fle" : "_Q_fle"; break;
+    case SPCC::FCC_GE : LibCall = is64Bit? "_Qp_fge" : "_Q_fge"; break;
+    case SPCC::FCC_UL :
+    case SPCC::FCC_ULE:
+    case SPCC::FCC_UG :
+    case SPCC::FCC_UGE:
+    case SPCC::FCC_U  :
+    case SPCC::FCC_O  :
+    case SPCC::FCC_LG :
+    case SPCC::FCC_UE : LibCall = is64Bit? "_Qp_cmp" : "_Q_cmp"; break;
+    }
+  } else {
+    llvm_unreachable("LowerFcompare for unsupported type");
   }
 
   auto PtrVT = getPointerTy(DAG.getDataLayout());
@@ -2243,22 +2716,40 @@ SDValue SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS,
     SPCC = SPCC::ICC_NE;
     return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
   }
+  case SPCC::FCC_E  : {
+    SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType());
+    SPCC = SPCC::ICC_E;
+    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
+  }
+  case SPCC::FCC_G  : {
+    SDValue RHS = DAG.getTargetConstant(1, DL, Result.getValueType());
+    SPCC = SPCC::ICC_E;
+    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
+  }
+  case SPCC::FCC_LE  : { /* not equal to 1 (a<=b : <-1,0> ) */
+    SDValue RHS = DAG.getTargetConstant(1, DL, Result.getValueType());
+    SPCC = SPCC::ICC_NE;
+    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
+  }
+  case SPCC::FCC_L  : {
+    SDValue RHS = DAG.getTargetConstant(-1, DL, Result.getValueType());
+    SPCC = SPCC::ICC_E;
+    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
+  }
   case SPCC::FCC_UL : {
-    SDValue Mask   = DAG.getConstant(1, DL, Result.getValueType());
-    Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
     SDValue RHS    = DAG.getTargetConstant(0, DL, Result.getValueType());
-    SPCC = SPCC::ICC_NE;
+    SPCC = SPCC::ICC_G;
     return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
   }
   case SPCC::FCC_ULE: {
-    SDValue RHS = DAG.getTargetConstant(2, DL, Result.getValueType());
+    SDValue RHS = DAG.getTargetConstant(-1, DL, Result.getValueType());
     SPCC = SPCC::ICC_NE;
     return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
   }
   case SPCC::FCC_UG :  {
-    SDValue RHS = DAG.getTargetConstant(1, DL, Result.getValueType());
-    SPCC = SPCC::ICC_G;
-    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
+    SDValue RHS = DAG.getTargetConstant(2, DL, Result.getValueType());
+    SPCC = SPCC::ICC_NE;
+    return DAG.getNode(SPISD::ANDCC, DL, MVT::Glue, Result, RHS);
   }
   case SPCC::FCC_UGE: {
     SDValue RHS = DAG.getTargetConstant(1, DL, Result.getValueType());
@@ -2296,11 +2787,32 @@ SDValue SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS,
 static SDValue
 LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG,
                    const SparcTargetLowering &TLI) {
+  // f16->f32
+  if (Op.getOperand(0).getValueType() == MVT::f16 &&
+      Op.getValueType()==MVT::f32) {
+    if (TLI.isHalfFopSoft(SoftFops::SOFTFP_CFUP) || TLI.isSingleFopSoft(SoftFops::SOFTFP_CFDN)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::FPEXT_F16_F32), 1);
+    }
+    return Op;
+  }
+  // f16->f64
+  if (Op.getOperand(0).getValueType() == MVT::f16 &&
+      Op.getValueType()==MVT::f64) {
+    return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::FPEXT_F16_F64), 1);
+  }
+  // f32->f64
+  if (Op.getOperand(0).getValueType() == MVT::f32 &&
+      Op.getValueType()==MVT::f64) {
+    if (TLI.isSingleFopSoft(SoftFops::SOFTFP_CFUP) || TLI.isDoubleFopSoft(SoftFops::SOFTFP_CFDN))
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::FPEXT_F32_F64), 1);
+    return Op;
+  }
 
+  // f64->f128
   if (Op.getOperand(0).getValueType() == MVT::f64)
     return TLI.LowerF128Op(Op, DAG,
                            TLI.getLibcallName(RTLIB::FPEXT_F64_F128), 1);
-
+  // f32->f128
   if (Op.getOperand(0).getValueType() == MVT::f32)
     return TLI.LowerF128Op(Op, DAG,
                            TLI.getLibcallName(RTLIB::FPEXT_F32_F128), 1);
@@ -2312,6 +2824,35 @@ LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG,
 static SDValue
 LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG,
                   const SparcTargetLowering &TLI) {
+  // round f64->f32 but soft-float for double
+  if (Op.getOperand(0).getValueType()==MVT::f64 &&
+      Op.getValueType()==MVT::f32) {
+    if (TLI.isSingleFopSoft(SoftFops::SOFTFP_CFUP) || TLI.isDoubleFopSoft(SoftFops::SOFTFP_CFDN))
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::FPROUND_F64_F32), 1);
+    return Op;
+  }
+  // round f32->f16 but soft-float for single
+  if (Op.getOperand(0).getValueType()==MVT::f32 &&
+      Op.getValueType()==MVT::f16) {
+    if (TLI.isHalfFopSoft(SoftFops::SOFTFP_CFUP) || TLI.isSingleFopSoft(SoftFops::SOFTFP_CFDN)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::FPROUND_F32_F16), 1);
+    }
+    return Op;
+  }
+  // round f64->f16 but soft-float for double
+  if (Op.getOperand(0).getValueType()==MVT::f64 &&
+      Op.getValueType()==MVT::f16) {
+    if (TLI.isHalfFopSoft(SoftFops::SOFTFP_CFUP) || TLI.isSingleFopSoft(SoftFops::SOFTFP_CFDN) ||
+        TLI.isSingleFopSoft(SoftFops::SOFTFP_CFUP) || TLI.isDoubleFopSoft(SoftFops::SOFTFP_CFDN)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::FPROUND_F64_F16), 1);
+    } else {
+      SDLoc dl(Op);
+      SDValue dtos = SDValue(DAG.getMachineNode(SP::FDTOS, dl, MVT::f32, Op.getOperand(0)),0);
+      SDValue stoh = SDValue(DAG.getMachineNode(SP::FSTOH, dl, MVT::f16, dtos),0);
+      return stoh;
+    }
+  }
+
   // FP_ROUND on f64 and f32 are legal.
   if (Op.getOperand(0).getValueType() != MVT::f128)
     return Op;
@@ -2327,6 +2868,199 @@ LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG,
   return SDValue();
 }
 
+// for v2f16 only
+static SDValue LowerBuildVector(SDValue Op, SelectionDAG &DAG,
+                                      const SparcTargetLowering &TLI,
+                                      const SparcSubtarget *Subtarget) {
+// build v2f16 from two f16 values, other combinations are not allowed now.
+  SDLoc dl(Op);
+  EVT VT = Op.getValueType();
+  if (VT == MVT::v2f16) { /* for v2f16 - vector packed half */
+    unsigned NumElts = VT.getVectorNumElements();
+    assert(NumElts==2);
+
+    EVT inVT1 = Op.getOperand(0).getValueType();
+    EVT inVT2 = Op.getOperand(1).getValueType();
+    assert(inVT1 == MVT::f16 && inVT2 == MVT::f16);
+  // build vector with MUVVUL
+    SDValue El1 = DAG.getNode(ISD::BITCAST, dl, MVT::f16, Op.getOperand(0));
+    SDValue El2 = DAG.getNode(ISD::BITCAST, dl, MVT::f16, Op.getOperand(1));
+    return DAG.getNode(SPISD::MOVVUU, dl, MVT::v2f16, El1, El2);
+
+  } else if (VT.isSubwordVector()) { /* build subword packed word */
+    unsigned num = Op.getNumOperands();
+    unsigned val = 0;
+    // only constant - compute in compile time
+    unsigned ebw = VT.getSimpleVT().getSubwordSizeInBits();
+    uint32_t elmMask = ((1<<ebw)-1);
+
+    // step 1 - compute the value
+    for(unsigned n=0;n<num;++n) {
+      ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Op.getOperand(n));
+      if (!Const) return SDValue(); /* not all constants ... TODO: process */
+      assert(Const && "Element for subword vector is not a constant.");
+
+      uint64_t cv = Op.getConstantOperandVal(n);
+      val = val | ((cv & elmMask)<<(ebw*n));
+    }
+    // create and return the output value
+    SDValue out = DAG.getNode(ISD::BITCAST, dl, VT, DAG.getConstant(val, dl, MVT::i32));
+    return out;
+
+  } else {
+    return SDValue();
+  }
+}
+
+static SDValue LowerInsertIntoVector(SDValue Op, SelectionDAG &DAG,
+                                      const SparcTargetLowering &TLI,
+                                      const SparcSubtarget *Subtarget) {
+  SDLoc dl(Op);
+  EVT VT = Op.getValueType();
+
+  if (VT == MVT::v2f16) { /* for v2f16 - vector packed half */
+    EVT inVT1 = Op.getOperand(0).getValueType();
+    EVT inVT2 = Op.getOperand(1).getValueType();
+    assert(inVT1 == MVT::v2f16 && inVT2 == MVT::f16);
+    uint64_t idx = Op->getConstantOperandVal(2);
+
+    if (idx==0) {
+      SDValue Step1 = DAG.getNode(ISD::BITCAST, dl, MVT::f16, Op.getOperand(1));
+      return DAG.getNode(SPISD::MOVVUL, dl, MVT::v2f16, Step1, Op.getOperand(1));
+    } else {
+      SDValue Step1 = DAG.getNode(ISD::BITCAST, dl, MVT::f16, Op.getOperand(1));
+      return DAG.getNode(SPISD::MOVVUU, dl, MVT::v2f16, Op.getOperand(0), Step1);
+    }
+
+  } else if (VT.isSubwordVector()) {  /* insert element to subword packed word */
+    unsigned NumElts = VT.getVectorNumElements();
+    EVT inVT1 = Op.getOperand(0).getValueType();
+    EVT inVT2 = Op.getOperand(1).getValueType();
+
+    assert(VT == inVT1); /* the output type is the same as the input type */
+    unsigned bw = inVT1.getSizeInBits();
+    unsigned ebw = inVT1.getSimpleVT().getSubwordSizeInBits();
+
+    ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Op.getOperand(2));
+    if (Const) { /* index is constant */
+      uint64_t idx = Op->getConstantOperandVal(2);
+
+      unsigned shift = ebw*idx;
+      uint32_t valMask = ((1<<ebw)-1)<<shift;
+      uint32_t remMask = ~valMask;
+
+      // s0=bitcast(newelm) /* useful for vsXp32 */
+      SDValue Step0 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(1));
+      // s1=s0 << shift
+      SDValue Step1 = DAG.getNode(ISD::SHL, dl, MVT::i32, Step0, DAG.getConstant(shift, dl, MVT::i32));
+      // s2 = s1 & valmask
+      SDValue Step2 = DAG.getNode(ISD::AND, dl, MVT::i32, Step1, DAG.getConstant(valMask, dl, MVT::i32));
+      // s3 = bitcast(vec)
+      SDValue Step3 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(0));
+      // s4 = s3 & remmask
+      SDValue Step4 = DAG.getNode(ISD::AND, dl, MVT::i32, Step3, DAG.getConstant(remMask, dl, MVT::i32));
+      // out = s2 or s4
+      SDValue Step5 = DAG.getNode(ISD::OR, dl, MVT::i32, Step2, Step4);
+      // bitcast to subword type
+      return DAG.getNode(ISD::BITCAST, dl, VT, Step5);
+    } else {
+      // shift=Op(2)*ebw
+      SDValue shift = DAG.getNode(ISD::MUL, dl, MVT::i32, Op.getOperand(2), DAG.getConstant(ebw, dl, MVT::i32));
+      // valMask = ((1<<ebw)-1)<<shift
+      SDValue valmask = DAG.getNode(ISD::SHL, dl, MVT::i32, DAG.getConstant( ((1<<ebw)-1) , dl, MVT::i32), shift);
+      // remMask = ~valMask
+      SDValue remmask = DAG.getNode(ISD::XOR, dl, MVT::i32, valmask, DAG.getConstant( -1 , dl, MVT::i32));
+
+      // s0=bitcast(newelm) /* useful for vsXp32 */
+      SDValue Step0 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(1));
+      // s1=s0 << shift
+      SDValue Step1 = DAG.getNode(ISD::SHL, dl, MVT::i32, Step0, shift);
+      // s2 = s1 & valmask
+      SDValue Step2 = DAG.getNode(ISD::AND, dl, MVT::i32, Step1, valmask);
+      // s3 = bitcast(vec)
+      SDValue Step3 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(0));
+      // s4 = s3 & remmask
+      SDValue Step4 = DAG.getNode(ISD::AND, dl, MVT::i32, Step3, remmask);
+      // out = s2 or s4
+      SDValue Step5 = DAG.getNode(ISD::OR, dl, MVT::i32, Step2, Step4);
+      // bitcast to subword type
+      return DAG.getNode(ISD::BITCAST, dl, VT, Step5);
+
+    }
+
+  } else {
+    return SDValue();
+  }
+}
+
+static SDValue LowerExtractFromVector(SDValue Op, SelectionDAG &DAG,
+                                      const SparcTargetLowering &TLI,
+                                      const SparcSubtarget *Subtarget) {
+  SDLoc dl(Op);
+  EVT VT = Op.getValueType();
+  EVT inVT = Op.getOperand(0).getValueType();
+
+  if (VT == MVT::f16) { /* output type */
+    assert(inVT == MVT::v2f16);
+
+    uint64_t idx = Op->getConstantOperandVal(1);
+    if (idx==0) {
+      return DAG.getNode(SPISD::MOVVUU, dl, MVT::f16, Op.getOperand(0), Op.getOperand(0));
+    } else {
+      return DAG.getNode(SPISD::MOVVLL, dl, MVT::f16, Op.getOperand(0), Op.getOperand(0));
+    }
+
+  } else if (inVT.isSubwordVector()) {  /* extract element from subword packed word */
+
+    unsigned NumElts = inVT.getVectorNumElements();
+
+    unsigned bw = inVT.getSizeInBits();
+    unsigned ebw = inVT.getSimpleVT().getSubwordSizeInBits();
+
+    assert(VT.getSizeInBits() >= ebw); /* the output type has at least the same size as an element of the input type */
+
+    ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Op.getOperand(1));
+    if (Const) { /* index is constant */
+      uint64_t idx = Op.getConstantOperandVal(1);
+
+      unsigned shift = ebw*idx;
+      uint32_t valMask = ((1<<ebw)-1);
+
+      // s0=bitcast(vect)
+      SDValue Step0 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(0));
+      // s1=s0 >> shift
+      SDValue Step1 = DAG.getNode(ISD::SRL, dl, MVT::i32, Step0, DAG.getConstant(shift, dl, MVT::i32));
+      // s2 = s1 & valmask
+      SDValue Step2 = DAG.getNode(ISD::AND, dl, MVT::i32, Step1, DAG.getConstant(valMask, dl, MVT::i32));
+      // return bitcast(s2)
+      return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Step2); // VT
+    } else {
+
+      // shift=Op(1)*ebw
+      SDValue shift = DAG.getNode(ISD::MUL, dl, MVT::i32, Op.getOperand(1), DAG.getConstant(ebw, dl, MVT::i32));
+      // valMask = ((1<<ebw)-1)
+      SDValue valmask = DAG.getConstant( ((1<<ebw)-1) , dl, MVT::i32);
+      // s0=bitcast(vect)
+      SDValue Step0 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(0));
+      // s1=s0 >> shift
+      SDValue Step1 = DAG.getNode(ISD::SRL, dl, MVT::i32, Step0, shift);
+      // s2 = s1 & valmask
+      SDValue Step2 = DAG.getNode(ISD::AND, dl, MVT::i32, Step1, valmask);
+      // return bitcast(vec)
+      return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Step2); // VT
+    }
+  } else {
+    return SDValue();
+  }
+}
+
+static SDValue LowerVectorShuffle(SDValue Op, SelectionDAG &DAG,
+                                  const SparcTargetLowering &TLI,
+                                  const SparcSubtarget *Subtarget) {
+  return SDValue();
+}
+
+
 static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG,
                                const SparcTargetLowering &TLI,
                                bool hasHardQuad) {
@@ -2347,11 +3081,31 @@ static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG,
   if (!TLI.isTypeLegal(VT))
     return SDValue();
 
+  EVT inType = Op.getOperand(0).getValueType();
+
   // Otherwise, Convert the fp value to integer in an FP register.
-  if (VT == MVT::i32)
-    Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
-  else
+  if (VT == MVT::i32) {
+    if (inType==MVT::f16 && TLI.isHalfFopSoft(SoftFops::SOFTFP_CF2I)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::FPTOSINT_F16_I32), 1);
+    } else if (inType==MVT::f32 && TLI.isSingleFopSoft(SoftFops::SOFTFP_CF2I)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::FPTOSINT_F32_I32), 1);
+    } else if (inType==MVT::f64 && TLI.isDoubleFopSoft(SoftFops::SOFTFP_CF2I)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::FPTOSINT_F64_I32), 1);
+    }
+    if (inType==MVT::f32)
+      Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
+    else if (inType==MVT::f16) {
+      Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
+    } else if (inType==MVT::f64)
+      Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
+  } else {
+    if (inType==MVT::f32 && TLI.isSingleFopSoft(SoftFops::SOFTFP_CF2I)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::FPTOSINT_F32_I64), 1);
+    } else if (inType==MVT::f64 && TLI.isDoubleFopSoft(SoftFops::SOFTFP_CF2I)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::FPTOSINT_F64_I64), 1);
+    }
     Op = DAG.getNode(SPISD::FTOX, dl, MVT::f64, Op.getOperand(0));
+  }
 
   return DAG.getNode(ISD::BITCAST, dl, VT, Op);
 }
@@ -2361,7 +3115,7 @@ static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG,
                                bool hasHardQuad) {
   SDLoc dl(Op);
   EVT OpVT = Op.getOperand(0).getValueType();
-  assert(OpVT == MVT::i32 || (OpVT == MVT::i64));
+  assert(OpVT== MVT::i16 || OpVT == MVT::i32 || (OpVT == MVT::i64));
 
   EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64;
 
@@ -2378,6 +3132,32 @@ static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG,
   if (!TLI.isTypeLegal(OpVT))
     return SDValue();
 
+  EVT outType = Op.getValueType();
+  if (OpVT == MVT::i32) {
+    if (outType==MVT::f16 && TLI.isHalfFopSoft(SoftFops::SOFTFP_CI2F)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::SINTTOFP_I32_F16), 1);
+    } else if (outType==MVT::f32 && TLI.isSingleFopSoft(SoftFops::SOFTFP_CI2F)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::SINTTOFP_I32_F32), 1);
+    } else if (outType==MVT::f64 && TLI.isDoubleFopSoft(SoftFops::SOFTFP_CI2F)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::SINTTOFP_I32_F64), 1);
+    }
+  } else {
+    if (outType==MVT::f32 && TLI.isSingleFopSoft(SoftFops::SOFTFP_CI2F)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::SINTTOFP_I64_F32), 1);
+    } else if (outType==MVT::f64 && TLI.isDoubleFopSoft(SoftFops::SOFTFP_CI2F)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::SINTTOFP_I64_F64), 1);
+    }
+  }
+
+  if (outType==MVT::f16) {
+    if (TLI.isHalfFopSoft(SoftFops::SOFTFP_CI2F))
+      return TLI.LowerF128Op(Op, DAG, "__floatsihf", 1);
+    else {
+      SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
+      return DAG.getNode(SPISD::ITOF, dl, outType, Tmp);
+    }
+  }
+
   // Otherwise, Convert the int value to FP in an FP register.
   SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, floatVT, Op.getOperand(0));
   unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF;
@@ -2398,6 +3178,21 @@ static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG,
 
   assert(VT == MVT::i32 || VT == MVT::i64);
 
+  EVT inType = Op.getOperand(0).getValueType();
+  if (VT == MVT::i32) {
+    if (inType==MVT::f32 && TLI.isSingleFopSoft(SoftFops::SOFTFP_CF2I)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::FPTOUINT_F32_I32), 1);
+    } else if (inType==MVT::f64 && TLI.isDoubleFopSoft(SoftFops::SOFTFP_CF2I)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::FPTOUINT_F64_I32), 1);
+    }
+  } else {
+    if (inType==MVT::f32 && TLI.isSingleFopSoft(SoftFops::SOFTFP_CF2I)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::FPTOUINT_F32_I64), 1);
+    } else if (inType==MVT::f64 && TLI.isDoubleFopSoft(SoftFops::SOFTFP_CF2I)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::FPTOUINT_F64_I64), 1);
+    }
+  }
+
   return TLI.LowerF128Op(Op, DAG,
                          TLI.getLibcallName(VT == MVT::i32
                                             ? RTLIB::FPTOUINT_F128_I32
@@ -2417,6 +3212,21 @@ static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG,
   if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(OpVT)))
     return SDValue();
 
+  EVT outType = Op.getValueType();
+  if (OpVT == MVT::i32) {
+    if (outType==MVT::f32 && TLI.isSingleFopSoft(SoftFops::SOFTFP_CI2F)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::UINTTOFP_I32_F32), 1);
+    } else if (outType==MVT::f64 && TLI.isDoubleFopSoft(SoftFops::SOFTFP_CI2F)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::UINTTOFP_I32_F64), 1);
+    }
+  } else {
+    if (outType==MVT::f32 && TLI.isSingleFopSoft(SoftFops::SOFTFP_CI2F)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::UINTTOFP_I64_F32), 1);
+    } else if (outType==MVT::f64 && TLI.isDoubleFopSoft(SoftFops::SOFTFP_CI2F)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::UINTTOFP_I64_F64), 1);
+    }
+  }
+
   return TLI.LowerF128Op(Op, DAG,
                          TLI.getLibcallName(OpVT == MVT::i32
                                             ? RTLIB::UINTTOFP_I32_F128
@@ -2446,11 +3256,26 @@ static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
     if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
     // 32-bit compares use the icc flags, 64-bit uses the xcc flags.
     Opc = LHS.getValueType() == MVT::i32 ? SPISD::BRICC : SPISD::BRXCC;
+
   } else {
     if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
       if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
       CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
       Opc = SPISD::BRICC;
+
+    } else if (TLI.isHalfFopSoft(SoftFops::SOFTFP_CMP) && LHS.getValueType() == MVT::f16) {
+      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
+      CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
+      Opc = SPISD::BRICC;
+    } else if (TLI.isDoubleFopSoft(SoftFops::SOFTFP_CMP) && LHS.getValueType() == MVT::f64) {
+      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
+      CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
+      Opc = SPISD::BRICC;
+    } else if (TLI.isSingleFopSoft(SoftFops::SOFTFP_CMP) && LHS.getValueType() == MVT::f32) {
+      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
+      CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
+      Opc = SPISD::BRICC;
+
     } else {
       CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
       if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
@@ -2482,11 +3307,26 @@ static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
     Opc = LHS.getValueType() == MVT::i32 ?
           SPISD::SELECT_ICC : SPISD::SELECT_XCC;
     if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
+
   } else {
     if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
       if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
       CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
       Opc = SPISD::SELECT_ICC;
+
+    } else if (TLI.isHalfFopSoft(SoftFops::SOFTFP_CMP) && LHS.getValueType() == MVT::f16) {
+      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
+      CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
+      Opc = SPISD::SELECT_ICC;
+    } else if (TLI.isDoubleFopSoft(SoftFops::SOFTFP_CMP) && LHS.getValueType() == MVT::f64) {
+      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
+      CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
+      Opc = SPISD::SELECT_ICC;
+    } else if (TLI.isSingleFopSoft(SoftFops::SOFTFP_CMP) && LHS.getValueType() == MVT::f32) {
+      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
+      CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
+      Opc = SPISD::SELECT_ICC;
+
     } else {
       CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
       Opc = SPISD::SELECT_FCC;
@@ -2525,6 +3365,7 @@ static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
   EVT PtrVT = VAListPtr.getValueType();
   const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
   SDLoc DL(Node);
+
   SDValue VAList =
       DAG.getLoad(PtrVT, DL, InChain, VAListPtr, MachinePointerInfo(SV));
   // Increment the pointer, VAList, to the next vaarg.
@@ -2765,7 +3606,8 @@ static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
   return DAG.getMergeValues(Ops, dl);
 }
 
-static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG)
+static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG, 
+                          const SparcSubtarget *Subtarget)
 {
   LoadSDNode *LdNode = cast<LoadSDNode>(Op.getNode());
 
@@ -2773,6 +3615,50 @@ static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG)
   if (MemVT == MVT::f128)
     return LowerF128Load(Op, DAG);
 
+  if (MemVT == MVT::v2f32) {
+    SDLoc dl(Op);
+    unsigned alignment = LdNode->getAlignment();
+    if (alignment==4) {
+    
+      SDValue i0_32 =
+        DAG.getLoad(MVT::f32, dl, LdNode->getChain(), LdNode->getBasePtr(),
+                    LdNode->getPointerInfo(), alignment);
+      EVT addrVT = LdNode->getBasePtr().getValueType();
+      SDValue i1_Ptr = DAG.getNode(ISD::ADD, dl, addrVT,
+                                    LdNode->getBasePtr(),
+                                    DAG.getConstant(4, dl, addrVT));
+      SDValue i1_32 = DAG.getLoad(MVT::f32, dl, LdNode->getChain(), i1_Ptr,
+                                  LdNode->getPointerInfo(), alignment);
+      SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even, dl, MVT::i32);
+      SDValue SubRegOdd  = DAG.getTargetConstant(SP::sub_odd, dl, MVT::i32);
+      SDNode *InFPvec = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
+                                       dl, MVT::f64);
+      InFPvec = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
+                               MVT::v2f32,
+                               SDValue(InFPvec, 0),
+                               i0_32,
+                               SubRegEven);
+      InFPvec = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
+                               MVT::v2f32,
+                               SDValue(InFPvec, 0),
+                               i1_32,
+                               SubRegOdd);
+      SDValue OutChains[2] = {  SDValue(i0_32.getNode(), 1),
+                                SDValue(i1_32.getNode(), 1) };
+      SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
+      SDValue Ops[2] = {SDValue(InFPvec,0), OutChain};
+      return DAG.getMergeValues(Ops, dl);
+      
+    } else  if (alignment<4) {
+      if (Subtarget->isAllowedUnalignedFP()) {
+        errs() << "Warning: The packed FP variable can be unaligned.\n";
+        //LdNode->getDebugLoc().dump();
+      } else {
+        llvm_unreachable("Packed FP variable must be correctly aligned.");
+      }
+    }
+  }
+
   return Op;
 }
 
@@ -2832,17 +3718,66 @@ static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG)
     return Chain;
   }
 
+  if (MemVT == MVT::f16) {
+    SDValue Val = DAG.getNode(ISD::BITCAST, dl, MVT::i16, St->getValue());
+    SDValue Chain = DAG.getStore(
+        St->getChain(), dl, Val, St->getBasePtr(), St->getPointerInfo(),
+        St->getAlignment(), St->getMemOperand()->getFlags(), St->getAAInfo());
+    return Chain;
+  }
+  if (MemVT == MVT::v2f16) {
+    return SDValue();
+  }
+  if (MemVT == MVT::v2f32) {
+    return SDValue();
+  }
+
+
   return SDValue();
 }
 
-static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
+static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9,
+                                const SparcTargetLowering &TLI) {
   assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS)
          && "invalid opcode");
 
-  SDLoc dl(Op);
+  SDLoc Loc(Op);
+
+  if (Op.getValueType() == MVT::f16) {
+    if (Op.getOpcode() == ISD::FNEG) {
+      if (TLI.isHalfFopSoft(SoftFops::SOFTFP_NEG))
+        return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::NEG_F16), 1);
+    } else { // FABS
+      if (TLI.isHalfFopSoft(SoftFops::SOFTFP_ABS))
+        return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::ABS_F16), 1);
+    }
+  }
+  if (Op.getValueType() == MVT::f32) {
+    if (Op.getOpcode() == ISD::FNEG) {
+      if (TLI.isSingleFopSoft(SoftFops::SOFTFP_NEG))
+        return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::NEG_F32), 1);
+    } else { // FABS
+      if (TLI.isSingleFopSoft(SoftFops::SOFTFP_ABS))
+        return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::ABS_F32), 1);
+    }
+  }
+
+  if (Op.getValueType() == MVT::f64) {
+    if (Op.getOpcode() == ISD::FNEG) { // FNEG - only fnegs, not fnegd -
+      if (TLI.isSingleFopSoft(SoftFops::SOFTFP_NEG)) { // HW fnegd is replaced with HW fnegs, so f32 version has to be tested
+        return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::NEG_F64), 1);
+      } else {
+        return LowerF64Op(Op.getOperand(0), Loc, DAG, Op.getOpcode());
+      }
+    } else { // FABS
+      if (TLI.isSingleFopSoft(SoftFops::SOFTFP_ABS)) { // HW fabsd is replaced with HW fabss
+        return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::ABS_F64), 1);
+      } else {
+        return LowerF64Op(Op.getOperand(0), Loc, DAG, Op.getOpcode());
+      }
+    }
+  }
 
-  if (Op.getValueType() == MVT::f64)
-    return LowerF64Op(Op.getOperand(0), dl, DAG, Op.getOpcode());
   if (Op.getValueType() != MVT::f128)
     return Op;
 
@@ -2852,28 +3787,28 @@ static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
   // subreg)
 
   SDValue SrcReg128 = Op.getOperand(0);
-  SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64,
+  SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, Loc, MVT::f64,
                                             SrcReg128);
-  SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64,
+  SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, Loc, MVT::f64,
                                             SrcReg128);
 
   if (DAG.getDataLayout().isLittleEndian()) {
     if (isV9)
-      Lo64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Lo64);
+      Lo64 = DAG.getNode(Op.getOpcode(), Loc, MVT::f64, Lo64);
     else
-      Lo64 = LowerF64Op(Lo64, dl, DAG, Op.getOpcode());
+      Lo64 = LowerF64Op(Lo64, Loc, DAG, Op.getOpcode());
   } else {
     if (isV9)
-      Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64);
+      Hi64 = DAG.getNode(Op.getOpcode(), Loc, MVT::f64, Hi64);
     else
-      Hi64 = LowerF64Op(Hi64, dl, DAG, Op.getOpcode());
+      Hi64 = LowerF64Op(Hi64, Loc, DAG, Op.getOpcode());
   }
 
   SDValue DstReg128 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
-                                                 dl, MVT::f128), 0);
-  DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128,
+                                                 Loc, MVT::f128), 0);
+  DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, Loc, MVT::f128,
                                         DstReg128, Hi64);
-  DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128,
+  DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, Loc, MVT::f128,
                                         DstReg128, Lo64);
   return DstReg128;
 }
@@ -2999,6 +3934,38 @@ SDValue SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
   }
 }
 
+/* -------------------------------------------------------------------------- */
+/* swar ops */
+SDValue SparcTargetLowering::LowerSwarOperation(SDValue Op,
+                  SelectionDAG &DAG, const SparcTargetLowering &TLI) const {
+  SDLoc DL(Op);
+  unsigned opcode = Op.getOpcode();
+  SDValue LHS = Op.getOperand(0);
+  SDValue RHS = Op.getOperand(1);
+//  SDValue OutChains[2];
+
+  assert((opcode == ISD::ADD || opcode == ISD::SUB || opcode == ISD::MUL)
+         && "invalid SWAR A/V opcode");
+
+  // add WRASR for setting SWAR module
+  unsigned swarop = 0;
+  switch (opcode) {
+    default: return SDValue();
+
+    case ISD::ADD: swarop = 0x00; break;
+    case ISD::SUB: swarop = 0x08; break;
+    case ISD::MUL: swarop = 0x0C; break;
+  }
+
+  if (LHS.getValueType()!=RHS.getValueType()) {
+    assert(false && "SWAR-AV LHS type != RHS type");
+  }
+
+  return DAG.getNode(SPISD::SWAR, DL, LHS.getValueType(), LHS, RHS);
+}
+/* -------------------------------------------------------------------------- */
+
+
 SDValue SparcTargetLowering::
 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
 
@@ -3008,6 +3975,12 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   switch (Op.getOpcode()) {
   default: llvm_unreachable("Should not custom lower this!");
 
+  case ISD::BUILD_VECTOR: return LowerBuildVector(Op, DAG, *this, Subtarget);
+  case ISD::INSERT_VECTOR_ELT:  return LowerInsertIntoVector(Op, DAG, *this, Subtarget);
+  case ISD::EXTRACT_VECTOR_ELT:  return LowerExtractFromVector(Op, DAG, *this, Subtarget);
+  case ISD::VECTOR_SHUFFLE: return LowerVectorShuffle(Op, DAG, *this, Subtarget);
+//  case ISD::BITCAST:            return LowerBitcast(Op, DAG, *this, Subtarget);
+
   case ISD::RETURNADDR:         return LowerRETURNADDR(Op, DAG, *this,
                                                        Subtarget);
   case ISD::FRAMEADDR:          return LowerFRAMEADDR(Op, DAG,
@@ -3033,20 +4006,84 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG,
                                                                Subtarget);
 
-  case ISD::LOAD:               return LowerLOAD(Op, DAG);
+  case ISD::LOAD:               return LowerLOAD(Op, DAG, Subtarget);
   case ISD::STORE:              return LowerSTORE(Op, DAG);
-  case ISD::FADD:               return LowerF128Op(Op, DAG,
-                                       getLibcallName(RTLIB::ADD_F128), 2);
-  case ISD::FSUB:               return LowerF128Op(Op, DAG,
-                                       getLibcallName(RTLIB::SUB_F128), 2);
-  case ISD::FMUL:               return LowerF128Op(Op, DAG,
-                                       getLibcallName(RTLIB::MUL_F128), 2);
-  case ISD::FDIV:               return LowerF128Op(Op, DAG,
-                                       getLibcallName(RTLIB::DIV_F128), 2);
-  case ISD::FSQRT:              return LowerF128Op(Op, DAG,
-                                       getLibcallName(RTLIB::SQRT_F128),1);
+
+
+  case ISD::FADD:
+    if (Op.getValueType()==MVT::f16)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::ADD_F16), 2);
+    else if (Op.getValueType()==MVT::f32)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::ADD_F32), 2);
+    else if (Op.getValueType()==MVT::f64)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::ADD_F64), 2);
+    else if (Op.getValueType()==MVT::v2f16)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::ADD_V2F16), 2);
+    else if (Op.getValueType()==MVT::v2f32)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::ADD_V2F32), 2);
+    else
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::ADD_F128), 2);
+
+  case ISD::FSUB:
+    if (Op.getValueType()==MVT::f16)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::SUB_F16), 2);
+    else if (Op.getValueType()==MVT::f32)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::SUB_F32), 2);
+    else if (Op.getValueType()==MVT::f64)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::SUB_F64), 2);
+    else if (Op.getValueType()==MVT::v2f16)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::SUB_V2F16), 2);
+    else if (Op.getValueType()==MVT::v2f32)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::SUB_V2F32), 2);
+    else
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::SUB_F128), 2);
+
+  case ISD::FMUL:
+    if (Op.getValueType()==MVT::f16)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::MUL_F16), 2);
+    else if (Op.getValueType()==MVT::f32)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::MUL_F32), 2);
+    else if (Op.getValueType()==MVT::f64)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::MUL_F64), 2);
+    else if (Op.getValueType()==MVT::v2f16)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::MUL_V2F16), 2);
+    else if (Op.getValueType()==MVT::v2f32)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::MUL_V2F32), 2);
+    else
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::MUL_F128), 2);
+
+  case ISD::FDIV:
+    if (Op.getValueType()==MVT::f16)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::DIV_F16), 2);
+    else if (Op.getValueType()==MVT::f32)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::DIV_F32), 2);
+    else if (Op.getValueType()==MVT::f64)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::DIV_F64), 2);
+    else if (Op.getValueType()==MVT::v2f16)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::DIV_V2F16), 2);
+    else if (Op.getValueType()==MVT::v2f32)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::DIV_V2F32), 2);
+    else
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::DIV_F128), 2);
+
+  case ISD::FSQRT:
+    if (Op.getValueType()==MVT::f16)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::SQRT_F16), 1);
+    else if (Op.getValueType()==MVT::f32)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::SQRT_F32), 1);
+    else if (Op.getValueType()==MVT::f64)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::SQRT_F64), 1);
+    else if (Op.getValueType()==MVT::v2f16)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::SQRT_V2F16), 1);
+    else if (Op.getValueType()==MVT::v2f32)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::SQRT_V2F32), 1);
+    else
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::SQRT_F128),1);
+
   case ISD::FABS:
-  case ISD::FNEG:               return LowerFNEGorFABS(Op, DAG, isV9);
+  case ISD::FNEG:
+    return LowerFNEGorFABS(Op, DAG, isV9, *this);
+
   case ISD::FP_EXTEND:          return LowerF128_FPEXTEND(Op, DAG, *this);
   case ISD::FP_ROUND:           return LowerF128_FPROUND(Op, DAG, *this);
   case ISD::ADDC:
@@ -3058,10 +4095,16 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   case ISD::ATOMIC_LOAD:
   case ISD::ATOMIC_STORE:       return LowerATOMIC_LOAD_STORE(Op, DAG);
   case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
+
+// swar custom operations
+  case ISD::ADD:
+  case ISD::SUB:
+  case ISD::MUL:
+    return LowerSwarOperation(Op, DAG,*this);
   }
 }
 
-SDValue SparcTargetLowering::bitcastConstantFPToInt(ConstantFPSDNode *C,
+SDValue SparcTargetLowering::bitcastConstantFPToInt64(ConstantFPSDNode *C,
                                                     const SDLoc &DL,
                                                     SelectionDAG &DAG) const {
   APInt V = C->getValueAPF().bitcastToAPInt();
@@ -3072,6 +4115,14 @@ SDValue SparcTargetLowering::bitcastConstantFPToInt(ConstantFPSDNode *C,
   return DAG.getBuildVector(MVT::v2i32, DL, {Hi, Lo});
 }
 
+SDValue SparcTargetLowering::bitcastConstantFPToInt16(ConstantFPSDNode *C,
+                                                    const SDLoc &DL,
+                                                    SelectionDAG &DAG) const {
+  APInt V = C->getValueAPF().bitcastToAPInt();
+  SDValue IVal = DAG.getConstant(V.zext(16), DL, MVT::i16);
+  return IVal;
+}
+
 SDValue SparcTargetLowering::PerformBITCASTCombine(SDNode *N,
                                                    DAGCombinerInfo &DCI) const {
   SDLoc dl(N);
@@ -3079,7 +4130,11 @@ SDValue SparcTargetLowering::PerformBITCASTCombine(SDNode *N,
 
   if (isa<ConstantFPSDNode>(Src) && N->getSimpleValueType(0) == MVT::v2i32 &&
       Src.getSimpleValueType() == MVT::f64)
-    return bitcastConstantFPToInt(cast<ConstantFPSDNode>(Src), dl, DCI.DAG);
+    return bitcastConstantFPToInt64(cast<ConstantFPSDNode>(Src), dl, DCI.DAG);
+
+  if (isa<ConstantFPSDNode>(Src) && N->getSimpleValueType(0) == MVT::i16 &&
+      Src.getSimpleValueType() == MVT::f16)
+    return bitcastConstantFPToInt16(cast<ConstantFPSDNode>(Src), dl, DCI.DAG);
 
   return SDValue();
 }
@@ -3104,11 +4159,17 @@ SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
   case SP::SELECT_CC_FP_ICC:
   case SP::SELECT_CC_DFP_ICC:
   case SP::SELECT_CC_QFP_ICC:
+  case SP::SELECT_CC_HFP_ICC:
+  case SP::SELECT_CC_PFPH_ICC:
+  case SP::SELECT_CC_PFPS_ICC:
     return expandSelectCC(MI, BB, SP::BCOND);
   case SP::SELECT_CC_Int_FCC:
   case SP::SELECT_CC_FP_FCC:
   case SP::SELECT_CC_DFP_FCC:
   case SP::SELECT_CC_QFP_FCC:
+  case SP::SELECT_CC_HFP_FCC:
+  case SP::SELECT_CC_PFPH_FCC:
+  case SP::SELECT_CC_PFPS_FCC:
     return expandSelectCC(MI, BB, SP::FBCOND);
   }
 }
@@ -3271,6 +4332,12 @@ SparcTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
         return std::make_pair(0U, &SP::LowDFPRegsRegClass);
       else if (VT == MVT::f128)
         return std::make_pair(0U, &SP::LowQFPRegsRegClass);
+      else if (VT == MVT::f16)
+        return std::make_pair(0U, &SP::HFPRegsRegClass);
+      else if (VT == MVT::v2f16)
+        return std::make_pair(0U, &SP::PFPHRegsRegClass);
+      else if (VT == MVT::v2f32)
+        return std::make_pair(0U, &SP::PFPSRegsRegClass);
       // This will generate an error message
       return std::make_pair(0U, nullptr);
     case 'e':
@@ -3280,6 +4347,12 @@ SparcTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
         return std::make_pair(0U, &SP::DFPRegsRegClass);
       else if (VT == MVT::f128)
         return std::make_pair(0U, &SP::QFPRegsRegClass);
+      else if (VT == MVT::f16)
+        return std::make_pair(0U, &SP::HFPRegsRegClass);
+      else if (VT == MVT::v2f16)
+        return std::make_pair(0U, &SP::PFPHRegsRegClass);
+      else if (VT == MVT::v2f32)
+        return std::make_pair(0U, &SP::PFPSRegsRegClass);
       // This will generate an error message
       return std::make_pair(0U, nullptr);
     }
@@ -3308,9 +4381,9 @@ SparcTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
         !name.substr(1).getAsInteger(10, intVal) && intVal <= 63) {
       std::string newConstraint;
 
-      if (VT == MVT::f32 || VT == MVT::Other) {
+      if (VT == MVT::f32 || VT == MVT::f16 || VT == MVT::v2f16 || VT == MVT::Other) {
         newConstraint = "{f" + utostr(intVal) + "}";
-      } else if (VT == MVT::f64 && (intVal % 2 == 0)) {
+      } else if ((VT == MVT::f64 || VT == MVT::v2f32) && (intVal % 2 == 0)) {
         newConstraint = "{d" + utostr(intVal / 2) + "}";
       } else if (VT == MVT::f128 && (intVal % 4 == 0)) {
         newConstraint = "{q" + utostr(intVal / 4) + "}";
@@ -3402,6 +4475,27 @@ void SparcTargetLowering::ReplaceNodeResults(SDNode *N,
     Results.push_back(LoadRes.getValue(1));
     return;
   }
+
+  case ISD::BITCAST:
+  {
+    return;
+  }
+
+  case ISD::FDIV:
+  case ISD::FMUL:
+  case ISD::FADD:
+  case ISD::FSUB:
+  case ISD::FSQRT:
+  case ISD::FABS:
+  case ISD::FNEG:
+  case ISD::FP_EXTEND:
+  case ISD::FP_ROUND:
+  {
+    if (N->getValueType(0) != MVT::f16) return;
+    Results.push_back(LowerOperation(SDValue(N,0), DAG));
+    return;
+  }
+
   }
 }
 
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.h b/llvm/lib/Target/Sparc/SparcISelLowering.h
index 3d798cec0c16..57a45b8e0646 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.h
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.h
@@ -46,7 +46,26 @@ namespace llvm {
 
       TLS_ADD,     // For Thread Local Storage (TLS).
       TLS_LD,
-      TLS_CALL
+      TLS_CALL,
+
+      PACKINSHI,   // insert into packed type as higher value
+      PACKINSLO,   // insert into packed type as lower value
+      PACKEXT,    // extract from packed value
+
+      SWAR,       // swar direct operation
+      SWARCC,    // swar direct operation with accumulation
+      SWARCTRL,   // swar control -> currently wrasr
+
+      SWAPPH,     // SWAP for floating point packed half type (AuAl -> AlAu)
+      MOVVUU,     // copy upper elements from two v2f16 into one v2f16 (AuAl,BuBl -> AuBu)
+      MOVVLL,     // copy lower elements from two v2f16 into one v2f16 (AuAl,BuBl -> AlBl)
+      MOVVUL,     // copy upper element from the first register and lower element from the second register into one v2f16 (AuAl,BuBl -> AuBl)
+      MOVVLU,     // copy lower element from the first register and upper element from the second register and swap them into one v2f16 (AuAl,BuBl -> AlBu)
+
+      MOVVZU,     // copy upper element of v2f16 to lower element and set zero to upper element of v2f16 (AuAl -> 0Au)
+      MOVVZL,     // copy lower element of v2f16 to lower element and set zero to upper element of v2f16 (AuAl -> 0Al)
+
+      ANDCC,      // BTST (ANDCC) instruction
     };
   }
 
@@ -58,6 +77,15 @@ namespace llvm {
 
     bool useSoftFloat() const override;
 
+    bool isHalfFopSoft(unsigned softfp) const;
+    bool isSingleFopSoft(unsigned softfp) const;
+    bool isDoubleFopSoft(unsigned softfp) const;
+    bool isAnySoftHalf() const;
+    bool isAnySingle() const;
+    bool isAnySoftDouble() const;
+    bool isPackedHalf() const;
+    bool isPackedSingle() const;
+
     /// computeKnownBitsForTargetNode - Determine which of the bits specified
     /// in Mask are known to be either zero or one and return them in the
     /// KnownZero/KnownOne bitsets.
@@ -172,6 +200,9 @@ namespace llvm {
                          SelectionDAG &DAG) const;
     SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const;
 
+    SDValue LowerFloatOp(SDValue Op, SelectionDAG &DAG, const char *LibFuncName,
+                         unsigned numArgs) const;
+
     SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, SDValue Arg,
                                  const SDLoc &DL, SelectionDAG &DAG) const;
     SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG,
@@ -182,9 +213,14 @@ namespace llvm {
 
     SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
 
+    SDValue LowerSwarOperation(SDValue Op, SelectionDAG &DAG,
+                                  const SparcTargetLowering &TLI) const;
+
     SDValue PerformBITCASTCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 
-    SDValue bitcastConstantFPToInt(ConstantFPSDNode *C, const SDLoc &DL,
+    SDValue bitcastConstantFPToInt64(ConstantFPSDNode *C, const SDLoc &DL,
+                                   SelectionDAG &DAG) const;
+    SDValue bitcastConstantFPToInt16(ConstantFPSDNode *C, const SDLoc &DL,
                                    SelectionDAG &DAG) const;
 
     SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
index 31185aa508af..1b6e88917ad5 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
@@ -44,7 +44,9 @@ unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
                                              int &FrameIndex) const {
   if (MI.getOpcode() == SP::LDri || MI.getOpcode() == SP::LDXri ||
       MI.getOpcode() == SP::LDFri || MI.getOpcode() == SP::LDDFri ||
-      MI.getOpcode() == SP::LDQFri) {
+      MI.getOpcode() == SP::LDQFri ||
+      MI.getOpcode() == SP::LDPFHri || MI.getOpcode() == SP::LDPFSri ||
+      MI.getOpcode() == SP::LDHFri) {
     if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
         MI.getOperand(2).getImm() == 0) {
       FrameIndex = MI.getOperand(1).getIndex();
@@ -63,7 +65,9 @@ unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
                                             int &FrameIndex) const {
   if (MI.getOpcode() == SP::STri || MI.getOpcode() == SP::STXri ||
       MI.getOpcode() == SP::STFri || MI.getOpcode() == SP::STDFri ||
-      MI.getOpcode() == SP::STQFri) {
+      MI.getOpcode() == SP::STQFri ||
+      MI.getOpcode() == SP::STPFHri || MI.getOpcode() == SP::STPFSri ||
+      MI.getOpcode() == SP::STHFri) {
     if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
         MI.getOperand(1).getImm() == 0) {
       FrameIndex = MI.getOperand(0).getIndex();
@@ -326,10 +330,19 @@ void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
     numSubRegs = 2;
     movOpc     = SP::ORrr;
     ExtraG0 = true;
-  } else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
-    BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
-      .addReg(SrcReg, getKillRegState(KillSrc));
-  else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) {
+  } else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) {
+    if (!Subtarget.useSoftFopSingle(SoftFops::SOFTFP_MOV)) {
+      BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
+        .addReg(SrcReg, getKillRegState(KillSrc));
+    } else if (!Subtarget.useSoftFopHalf(SoftFops::SOFTFP_MOV)) {
+      BuildMI(MBB, I, DL, get(SP::FMOVH), DestReg)
+        .addReg(SrcReg, getKillRegState(KillSrc));
+    } else { // neither FMOVS nor FMOVH
+fprintf(stderr," Warning: Copy FP registers with instruction FMOVS in soft-float mode\n");
+      BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
+        .addReg(SrcReg, getKillRegState(KillSrc));
+    }
+  } else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) {
     if (Subtarget.isV9()) {
       BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg)
         .addReg(SrcReg, getKillRegState(KillSrc));
@@ -337,7 +350,14 @@ void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
       // Use two FMOVS instructions.
       subRegIdx  = DFP_FP_SubRegsIdx;
       numSubRegs = 2;
-      movOpc     = SP::FMOVS;
+      if (!Subtarget.useSoftFopSingle(SoftFops::SOFTFP_MOV)) {
+        movOpc     = SP::FMOVS;
+      } else if (!Subtarget.useSoftFopHalf(SoftFops::SOFTFP_MOV)) {
+        movOpc     = SP::FMOVH;
+      } else {
+fprintf(stderr," Warning: Copy FP registers with instruction FMOVS in soft-float mode\n");
+        movOpc     = SP::FMOVS;
+      }
     }
   } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) {
     if (Subtarget.isV9()) {
@@ -354,8 +374,29 @@ void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
       // Use four FMOVS instructions.
       subRegIdx  = QFP_FP_SubRegsIdx;
       numSubRegs = 4;
-      movOpc     = SP::FMOVS;
+      if (!Subtarget.useSoftFopSingle(SoftFops::SOFTFP_MOV)) {
+        movOpc     = SP::FMOVS;
+      } else if (!Subtarget.useSoftFopHalf(SoftFops::SOFTFP_MOV)) {
+        movOpc     = SP::FMOVH;
+      } else {
+fprintf(stderr," Warning: Copy FP registers with instruction FMOVS in soft-float mode\n");
+        movOpc     = SP::FMOVS;
+      }
+    }
+
+  } else if (SP::HFPRegsRegClass.contains(DestReg, SrcReg)) {
+    BuildMI(MBB, I, DL, get(SP::FMOVH), DestReg)
+      .addReg(SrcReg, getKillRegState(KillSrc));
+
+  } else if (SP::PFPHRegsRegClass.contains(DestReg, SrcReg)) {
+    if (!Subtarget.useSoftFopSingle(SoftFops::SOFTFP_MOV)) {
+      BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
+        .addReg(SrcReg, getKillRegState(KillSrc));
+    } else if (!Subtarget.useSoftFopHalf(SoftFops::SOFTFP_MOV)) {
+      BuildMI(MBB, I, DL, get(SP::FMOVH), DestReg)
+        .addReg(SrcReg, getKillRegState(KillSrc));
     }
+
   } else if (SP::ASRRegsRegClass.contains(DestReg) &&
              SP::IntRegsRegClass.contains(SrcReg)) {
     BuildMI(MBB, I, DL, get(SP::WRASRrr), DestReg)
@@ -365,8 +406,14 @@ void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
              SP::ASRRegsRegClass.contains(SrcReg)) {
     BuildMI(MBB, I, DL, get(SP::RDASR), DestReg)
         .addReg(SrcReg, getKillRegState(KillSrc));
-  } else
+
+  } else if (SP::HFPRegsRegClass.contains(SrcReg) &&
+             SP::IntRegsRegClass.contains(DestReg)) {           // copy from F16 to Int
+// copy only over SP
+    llvm_unreachable("No HFPreg to Ireg copy");
+  } else {
     llvm_unreachable("Impossible reg-to-reg copy");
+  }
 
   if (numSubRegs == 0 || subRegIdx == nullptr || movOpc == 0)
     return;
@@ -426,6 +473,14 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
     // lowered into two STDs in eliminateFrameIndex.
     BuildMI(MBB, I, DL, get(SP::STQFri)).addFrameIndex(FI).addImm(0)
       .addReg(SrcReg,  getKillRegState(isKill)).addMemOperand(MMO);
+
+  else if (RC == &SP::HFPRegsRegClass)
+    BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
+      .addReg(SrcReg,  getKillRegState(isKill)).addMemOperand(MMO);
+  else if (RC == &SP::PFPHRegsRegClass)
+    BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
+      .addReg(SrcReg,  getKillRegState(isKill)).addMemOperand(MMO);
+
   else
     llvm_unreachable("Can't store this register to stack slot");
 }
@@ -464,6 +519,14 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
     // lowered into two LDDs in eliminateFrameIndex.
     BuildMI(MBB, I, DL, get(SP::LDQFri), DestReg).addFrameIndex(FI).addImm(0)
       .addMemOperand(MMO);
+
+  else if (RC == &SP::HFPRegsRegClass)
+    BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0)
+      .addMemOperand(MMO);
+  else if (RC == &SP::PFPHRegsRegClass)
+    BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0)
+      .addMemOperand(MMO);
+
   else
     llvm_unreachable("Can't load this register from stack slot");
 }
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td
index f26f4a1c1a84..01fd5714e2f8 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.td
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td
@@ -20,6 +20,12 @@ include "SparcInstrFormats.td"
 // Feature predicates.
 //===----------------------------------------------------------------------===//
 
+class PatFPH<SDPatternOperator OpNode, InstSP Inst>
+    : Pat<(OpNode PFPHRegs:$rs1), (Inst PFPHRegs:$rs1)>;
+
+class PatFPHFPH<SDPatternOperator OpNode, InstSP Inst>
+    : Pat<(OpNode PFPHRegs:$rs1, PFPHRegs:$rs2), (Inst PFPHRegs:$rs1, PFPHRegs:$rs2)>;
+
 // True when generating 32-bit code.
 def Is32Bit : Predicate<"!Subtarget->is64Bit()">;
 
@@ -74,6 +80,32 @@ def HasFSMULD : Predicate<"!Subtarget->hasNoFSMULD()">;
 // will pick deprecated instructions.
 def UseDeprecatedInsts : Predicate<"Subtarget->useDeprecatedV8Instructions()">;
 
+// daiteq ESA extensions
+def HasAnyHalf : Predicate<"Subtarget->useHardHalf()">;
+def HasFMOVh : Predicate<"!Subtarget->useSoftFopHalf(llvm::SoftFops::SOFTFP_MOV)">;
+def HasFNEGh : Predicate<"!Subtarget->useSoftFopHalf(llvm::SoftFops::SOFTFP_NEG)">;
+def HasFABSh : Predicate<"!Subtarget->useSoftFopHalf(llvm::SoftFops::SOFTFP_ABS)">;
+def HasFSQRTh : Predicate<"!Subtarget->useSoftFopHalf(llvm::SoftFops::SOFTFP_SQRT)">;
+def HasFADDh : Predicate<"!Subtarget->useSoftFopHalf(llvm::SoftFops::SOFTFP_ADD)">;
+def HasFSUBh : Predicate<"!Subtarget->useSoftFopHalf(llvm::SoftFops::SOFTFP_SUB)">;
+def HasFMULh : Predicate<"!Subtarget->useSoftFopHalf(llvm::SoftFops::SOFTFP_MUL)">;
+def HasFDIVh : Predicate<"!Subtarget->useSoftFopHalf(llvm::SoftFops::SOFTFP_DIV)">;
+def HasFhMULs: Predicate<"!Subtarget->useSoftFopHalf(llvm::SoftFops::SOFTFP_MULEX)">;
+def HasFiTOh : Predicate<"!Subtarget->useSoftFopHalf(llvm::SoftFops::SOFTFP_CI2F)">;
+def HasFhTOi : Predicate<"!Subtarget->useSoftFopHalf(llvm::SoftFops::SOFTFP_CF2I)">;
+def HasFhTOs : Predicate<"!Subtarget->useSoftFopHalf(llvm::SoftFops::SOFTFP_CFUP)">;
+def HasFCMPh : Predicate<"!Subtarget->useSoftFopHalf(llvm::SoftFops::SOFTFP_CMP)">;
+
+def HasFPPackHalf : Predicate<"Subtarget->usePackedHalf()">;
+
+def HasFPPackSingle : Predicate<"Subtarget->usePackedSingle()">;
+
+def HasFsTOh : Predicate<"!Subtarget->useSoftFopSingle(llvm::SoftFops::SOFTFP_CFDN)">;
+
+def HasFMOVs : Predicate<"!Subtarget->useSoftFopSingle(llvm::SoftFops::SOFTFP_MOV)">;
+def HasFNEGs : Predicate<"!Subtarget->useSoftFopSingle(llvm::SoftFops::SOFTFP_NEG)">;
+def HasFABSs : Predicate<"!Subtarget->useSoftFopSingle(llvm::SoftFops::SOFTFP_ABS)">;
+
 //===----------------------------------------------------------------------===//
 // Instruction Pattern Stuff
 //===----------------------------------------------------------------------===//
@@ -201,6 +233,8 @@ def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
 def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
 def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
 
+def SPandcc : SDNode<"SPISD::ANDCC", SDTSPcmpicc, [SDNPOutGlue]>;
+
 def SPhi    : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
 def SPlo    : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
 
@@ -246,6 +280,50 @@ def getPCX        : Operand<iPTR> {
   let PrintMethod = "printGetPCX";
 }
 
+// support for swar
+def SDTPSWAR1b  : SDTypeProfile<1, 2, [SDTCisVT<0, vs1p32>, SDTCisVT<1, vs1p32>, SDTCisVT<2, vs1p32>]>;
+def SDTPSWAR2b  : SDTypeProfile<1, 2, [SDTCisVT<0, vs2p32>, SDTCisVT<1, vs2p32>, SDTCisVT<2, vs2p32>]>;
+def SDTPSWAR3b  : SDTypeProfile<1, 2, [SDTCisVT<0, vs3p32>, SDTCisVT<1, vs3p32>, SDTCisVT<2, vs3p32>]>;
+def SDTPSWAR4b  : SDTypeProfile<1, 2, [SDTCisVT<0, vs4p32>, SDTCisVT<1, vs4p32>, SDTCisVT<2, vs4p32>]>;
+def SDTPSWAR8b  : SDTypeProfile<1, 2, [SDTCisVT<0, vs8p32>, SDTCisVT<1, vs8p32>, SDTCisVT<2, vs8p32>]>;
+def SDTPSWAR16b : SDTypeProfile<1, 2, [SDTCisVT<0, vs16p32>, SDTCisVT<1, vs16p32>, SDTCisVT<2, vs16p32>]>;
+def SPswar1b    : SDNode<"SPISD::SWAR", SDTPSWAR1b>;
+def SPswar2b    : SDNode<"SPISD::SWAR", SDTPSWAR2b>;
+def SPswar3b    : SDNode<"SPISD::SWAR", SDTPSWAR3b>;
+def SPswar4b    : SDNode<"SPISD::SWAR", SDTPSWAR4b>;
+def SPswar8b    : SDNode<"SPISD::SWAR", SDTPSWAR8b>;
+def SPswar16b   : SDNode<"SPISD::SWAR", SDTPSWAR16b>;
+
+
+def SDTPSWARcc1b : SDTypeProfile<1, 3, [SDTCisVT<0, vs1p32>, SDTCisVT<1, vs1p32>, SDTCisVT<2, vs1p32>, SDTCisVT<3, i32>]>;
+def SDTPSWARcc2b : SDTypeProfile<1, 3, [SDTCisVT<0, vs2p32>, SDTCisVT<1, vs2p32>, SDTCisVT<2, vs2p32>, SDTCisVT<3, i32>]>;
+def SDTPSWARcc3b : SDTypeProfile<1, 3, [SDTCisVT<0, vs3p32>, SDTCisVT<1, vs3p32>, SDTCisVT<2, vs3p32>, SDTCisVT<3, i32>]>;
+def SDTPSWARcc4b : SDTypeProfile<1, 3, [SDTCisVT<0, vs4p32>, SDTCisVT<1, vs4p32>, SDTCisVT<2, vs4p32>, SDTCisVT<3, i32>]>;
+def SDTPSWARcc8b : SDTypeProfile<1, 3, [SDTCisVT<0, vs8p32>, SDTCisVT<1, vs8p32>, SDTCisVT<2, vs8p32>, SDTCisVT<3, i32>]>;
+def SDTPSWARcc16b: SDTypeProfile<1, 3, [SDTCisVT<0, vs16p32>, SDTCisVT<1, vs16p32>, SDTCisVT<2, vs16p32>, SDTCisVT<3, i32>]>;
+def SPswarcc1b    : SDNode<"SPISD::SWARCC", SDTPSWARcc1b, [SDNPInGlue]>;
+def SPswarcc2b    : SDNode<"SPISD::SWARCC", SDTPSWARcc2b, [SDNPInGlue]>;
+def SPswarcc3b    : SDNode<"SPISD::SWARCC", SDTPSWARcc3b, [SDNPInGlue]>;
+def SPswarcc4b    : SDNode<"SPISD::SWARCC", SDTPSWARcc4b, [SDNPInGlue]>;
+def SPswarcc8b    : SDNode<"SPISD::SWARCC", SDTPSWARcc8b, [SDNPInGlue]>;
+def SPswarcc16b   : SDNode<"SPISD::SWARCC", SDTPSWARcc16b, [SDNPInGlue]>;
+
+
+def SDTv2f16UnOp : SDTypeProfile<1, 1, [SDTCisVT<0, v2f16>, SDTCisVT<1, v2f16>]>;
+def SDTv2f16BinOp : SDTypeProfile<1, 2, [SDTCisVT<0, v2f16>, SDTCisVT<1, v2f16>, SDTCisVT<2, v2f16>]>;
+def SPswapph : SDNode<"SPISD::SWAPPH", SDTv2f16UnOp>;
+def SPmovhzu : SDNode<"SPISD::MOVVZU", SDTv2f16UnOp>;
+def SPmovhzl : SDNode<"SPISD::MOVVZL", SDTv2f16UnOp>;
+def SPmovhuu : SDNode<"SPISD::MOVVUU", SDTv2f16BinOp>;
+def SPmovhll : SDNode<"SPISD::MOVVLL", SDTv2f16BinOp>;
+def SPmovhlu : SDNode<"SPISD::MOVVLU", SDTv2f16BinOp>;
+def SPmovhul : SDNode<"SPISD::MOVVUL", SDTv2f16BinOp>;
+
+// with conversion v2f16->f16
+def SDTv2f16tof16UnOp : SDTypeProfile<1, 1, [SDTCisVT<0, f16>, SDTCisVT<1, v2f16>]>;
+def SPmovhzuconv : SDNode<"SPISD::MOVVZU", SDTv2f16tof16UnOp>;
+def SPmovhzlconv : SDNode<"SPISD::MOVVZL", SDTv2f16tof16UnOp>;
+
 //===----------------------------------------------------------------------===//
 // SPARC Flag Conditions
 //===----------------------------------------------------------------------===//
@@ -452,6 +530,7 @@ let Uses = [ICC], usesCustomInserter = 1 in {
    : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
             "; SELECT_CC_Int_ICC PSEUDO!",
             [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>;
+
   def SELECT_CC_FP_ICC
    : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
             "; SELECT_CC_FP_ICC PSEUDO!",
@@ -466,6 +545,20 @@ let Uses = [ICC], usesCustomInserter = 1 in {
    : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
             "; SELECT_CC_QFP_ICC PSEUDO!",
             [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>;
+
+  def SELECT_CC_HFP_ICC
+   : Pseudo<(outs HFPRegs:$dst), (ins HFPRegs:$T, HFPRegs:$F, i32imm:$Cond),
+            "; SELECT_CC_HFP_ICC PSEUDO!",
+            [(set f16:$dst, (SPselecticc f16:$T, f16:$F, imm:$Cond))]>;
+  def SELECT_CC_PFPH_ICC
+   : Pseudo<(outs PFPHRegs:$dst), (ins PFPHRegs:$T, PFPHRegs:$F, i32imm:$Cond),
+            "; SELECT_CC_PFPH_ICC PSEUDO!",
+            [(set v2f16:$dst, (SPselecticc v2f16:$T, v2f16:$F, imm:$Cond))]>;
+  def SELECT_CC_PFPS_ICC
+   : Pseudo<(outs PFPSRegs:$dst), (ins PFPSRegs:$T, PFPSRegs:$F, i32imm:$Cond),
+            "; SELECT_CC_PFPS_ICC PSEUDO!",
+            [(set v2f32:$dst, (SPselecticc v2f32:$T, v2f32:$F, imm:$Cond))]>;
+
 }
 
 let usesCustomInserter = 1, Uses = [FCC0] in {
@@ -487,6 +580,20 @@ let usesCustomInserter = 1, Uses = [FCC0] in {
    : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
             "; SELECT_CC_QFP_FCC PSEUDO!",
             [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>;
+
+  def SELECT_CC_HFP_FCC
+   : Pseudo<(outs HFPRegs:$dst), (ins HFPRegs:$T, HFPRegs:$F, i32imm:$Cond),
+            "; SELECT_CC_HFP_FCC PSEUDO!",
+            [(set f16:$dst, (SPselectfcc f16:$T, f16:$F, imm:$Cond))]>;
+  def SELECT_CC_PFPH_FCC
+   : Pseudo<(outs PFPHRegs:$dst), (ins PFPHRegs:$T, PFPHRegs:$F, i32imm:$Cond),
+            "; SELECT_CC_PFPH_FCC PSEUDO!",
+            [(set v2f16:$dst, (SPselectfcc v2f16:$T, v2f16:$F, imm:$Cond))]>;
+  def SELECT_CC_PFPS_FCC
+   : Pseudo<(outs PFPSRegs:$dst), (ins PFPSRegs:$T, PFPSRegs:$F, i32imm:$Cond),
+            "; SELECT_CC_PFPS_FCC PSEUDO!",
+            [(set v2f32:$dst, (SPselectfcc v2f32:$T, v2f32:$F, imm:$Cond))]>;
+
 }
 
 // Section B.1 - Load Integer Instructions, p. 90
@@ -501,7 +608,20 @@ let DecoderMethod = "DecodeLoadInt" in {
 let DecoderMethod = "DecodeLoadIntPair" in
   defm LDD : LoadA<"ldd", 0b000011, 0b010011, load, IntPair, v2i32, IIC_ldd>;
 
+let DecoderMethod = "DecodeLoadSwar" in {
+  defm LDVS1P32   : LoadA<"ld", 0b000000, 0b010000, load, SwarRegs, vs1p32>;
+  defm LDVS2P32   : LoadA<"ld", 0b000000, 0b010000, load, SwarRegs, vs2p32>;
+  defm LDVS3P32   : LoadA<"ld", 0b000000, 0b010000, load, SwarRegs, vs3p32>;
+  defm LDVS4P32   : LoadA<"ld", 0b000000, 0b010000, load, SwarRegs, vs4p32>;
+  defm LDVS8P32   : LoadA<"ld", 0b000000, 0b010000, load, SwarRegs, vs8p32>;
+  defm LDVS16P32  : LoadA<"ld", 0b000000, 0b010000, load, SwarRegs, vs16p32>;
+}
+
 // Section B.2 - Load Floating-point Instructions, p. 92
+let DecoderMethod = "DecodeLoadHFP" in {
+  defm LDHF   : Load<"ldh",  0b101010, load,    HFPRegs,  f16, IIC_iu_or_fpu_instr>;
+}
+
 let DecoderMethod = "DecodeLoadFP" in {
   defm LDF   : Load<"ld",  0b100000, load,    FPRegs,  f32, IIC_iu_or_fpu_instr>;
   def LDFArr : LoadASI<"ld",  0b110000, load, FPRegs,  f32, IIC_iu_or_fpu_instr>,
@@ -516,6 +636,14 @@ let DecoderMethod = "DecodeLoadQFP" in
   defm LDQF  : LoadA<"ldq", 0b100010, 0b110010, load, QFPRegs, f128>,
                Requires<[HasV9, HasHardQuad]>;
 
+let DecoderMethod = "DecodeLoadPFPH" in {
+  defm LDPFH   : Load<"ld",  0b100000, load,    PFPHRegs,  v2f16, IIC_iu_or_fpu_instr>;
+}
+
+let DecoderMethod = "DecodeLoadPFPS" in {
+  defm LDPFS   : Load<"ldd",  0b100011, load,    PFPSRegs,  v2f32, IIC_iu_or_fpu_instr>;
+}
+
 let DecoderMethod = "DecodeLoadCP" in
   defm LDC   : Load<"ld", 0b110000, load, CoprocRegs, i32>;
 let DecoderMethod = "DecodeLoadCPPair" in
@@ -556,7 +684,20 @@ let DecoderMethod = "DecodeStoreInt" in {
 let DecoderMethod = "DecodeStoreIntPair" in
   defm STD   : StoreA<"std", 0b000111, 0b010111, store, IntPair, v2i32, IIC_std>;
 
+let DecoderMethod = "DecodeStoreInt" in {
+  defm STVS1P32    : StoreA<"st",  0b000100, 0b010100, store,  SwarRegs, vs1p32>;
+  defm STVS2P32    : StoreA<"st",  0b000100, 0b010100, store,  SwarRegs, vs2p32>;
+  defm STVS3P32    : StoreA<"st",  0b000100, 0b010100, store,  SwarRegs, vs3p32>;
+  defm STVS4P32    : StoreA<"st",  0b000100, 0b010100, store,  SwarRegs, vs4p32>;
+  defm STVS8P32    : StoreA<"st",  0b000100, 0b010100, store,  SwarRegs, vs8p32>;
+  defm STVS16P32   : StoreA<"st",  0b000100, 0b010100, store,  SwarRegs, vs16p32>;
+}
+
 // Section B.5 - Store Floating-point Instructions, p. 97
+let DecoderMethod = "DecodeStoreHFP" in {
+  defm STHF  : Store<"sth",  0b101110, store,         HFPRegs,  f16>;
+}
+
 let DecoderMethod = "DecodeStoreFP" in {
   defm STF   : Store<"st",  0b100100, store,         FPRegs,  f32>;
   def STFArr : StoreASI<"st",  0b110100, store,      FPRegs,  f32>,
@@ -571,6 +712,13 @@ let DecoderMethod = "DecodeStoreQFP" in
   defm STQF  : StoreA<"stq", 0b100110, 0b110110, store, QFPRegs, f128>,
                Requires<[HasV9, HasHardQuad]>;
 
+let DecoderMethod = "DecodeStorePFPH" in
+  defm STPFH   : Store<"st",  0b100100, store,         PFPHRegs,  v2f16>;
+
+let DecoderMethod = "DecodeStorePFPS" in
+  defm STPFS   : Store<"std",  0b100111, store,        PFPSRegs,  v2f32>;
+
+
 let DecoderMethod = "DecodeStoreCP" in 
   defm STC   : Store<"st", 0b110100, store, CoprocRegs, i32>; 
   
@@ -675,6 +823,59 @@ def XNORri  : F3_2<2, 0b000111,
                    (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
                    "xnor $rs1, $simm13, $rd", []>;
 
+// SWAR
+def SWAR_VS1      : F3_1<2, 0b001001,
+                  (outs SwarRegs:$rd), (ins SwarRegs:$rs1, SwarRegs:$rs2),
+                  "swar $rs1, $rs2, $rd",
+                  [(set vs1p32:$rd, (SPswar1b vs1p32:$rs1, vs1p32:$rs2))]>;
+def SWAR_VS2      : F3_1<2, 0b001001,
+                  (outs SwarRegs:$rd), (ins SwarRegs:$rs1, SwarRegs:$rs2),
+                  "swar $rs1, $rs2, $rd",
+                  [(set vs2p32:$rd, (SPswar2b vs2p32:$rs1, vs2p32:$rs2))]>;
+def SWAR_VS3      : F3_1<2, 0b001001,
+                  (outs SwarRegs:$rd), (ins SwarRegs:$rs1, SwarRegs:$rs2),
+                  "swar $rs1, $rs2, $rd",
+                  [(set vs3p32:$rd, (SPswar3b vs3p32:$rs1, vs3p32:$rs2))]>;
+def SWAR_VS4      : F3_1<2, 0b001001,
+                  (outs SwarRegs:$rd), (ins SwarRegs:$rs1, SwarRegs:$rs2),
+                  "swar $rs1, $rs2, $rd",
+                  [(set vs4p32:$rd, (SPswar4b vs4p32:$rs1, vs4p32:$rs2))]>;
+def SWAR_VS8      : F3_1<2, 0b001001,
+                  (outs SwarRegs:$rd), (ins SwarRegs:$rs1, SwarRegs:$rs2),
+                  "swar $rs1, $rs2, $rd",
+                  [(set vs8p32:$rd, (SPswar8b vs8p32:$rs1, vs8p32:$rs2))]>;
+def SWAR_VS16     : F3_1<2, 0b001001,
+                  (outs SwarRegs:$rd), (ins SwarRegs:$rs1, SwarRegs:$rs2),
+                  "swar $rs1, $rs2, $rd",
+                  [(set vs16p32:$rd, (SPswar16b vs16p32:$rs1, vs16p32:$rs2))]>;
+
+// SWARCC
+def SWARCC_VS1    : F3_1<2, 0b011001,
+                  (outs SwarRegs:$rd), (ins SwarRegs:$rs1, SwarRegs:$rs2, i32imm:$Cond),
+                  "swarcc $rs1, $rs2, $rd",
+                  [(set vs1p32:$rd, (SPswarcc1b vs1p32:$rs1, vs1p32:$rs2, imm:$Cond))]>;
+def SWARCC_VS2    : F3_1<2, 0b011001,
+                  (outs SwarRegs:$rd), (ins SwarRegs:$rs1, SwarRegs:$rs2, i32imm:$Cond),
+                  "swarcc $rs1, $rs2, $rd",
+                  [(set vs2p32:$rd, (SPswarcc2b vs2p32:$rs1, vs2p32:$rs2, imm:$Cond))]>;
+def SWARCC_VS3    : F3_1<2, 0b011001,
+                  (outs SwarRegs:$rd), (ins SwarRegs:$rs1, SwarRegs:$rs2, i32imm:$Cond),
+                  "swarcc $rs1, $rs2, $rd",
+                  [(set vs3p32:$rd, (SPswarcc3b vs3p32:$rs1, vs3p32:$rs2, imm:$Cond))]>;
+def SWARCC_VS4    : F3_1<2, 0b011001,
+                  (outs SwarRegs:$rd), (ins SwarRegs:$rs1, SwarRegs:$rs2, i32imm:$Cond),
+                  "swarcc $rs1, $rs2, $rd",
+                  [(set vs4p32:$rd, (SPswarcc4b vs4p32:$rs1, vs4p32:$rs2, imm:$Cond))]>;
+def SWARCC_VS8    : F3_1<2, 0b011001,
+                  (outs SwarRegs:$rd), (ins SwarRegs:$rs1, SwarRegs:$rs2, i32imm:$Cond),
+                  "swarcc $rs1, $rs2, $rd",
+                  [(set vs8p32:$rd, (SPswarcc8b vs8p32:$rs1, vs8p32:$rs2, imm:$Cond))]>;
+def SWARCC_VS16   : F3_1<2, 0b011001,
+                  (outs SwarRegs:$rd), (ins SwarRegs:$rs1, SwarRegs:$rs2, i32imm:$Cond),
+                  "swarcc $rs1, $rs2, $rd",
+                  [(set vs16p32:$rd, (SPswarcc16b vs16p32:$rs1, vs16p32:$rs2, imm:$Cond))]>;
+
+
 def : Pat<(and IntRegs:$rs1, SETHIimm_not:$rs2),
           (ANDNrr i32:$rs1, (SETHIi SETHIimm_not:$rs2))>;
 
@@ -682,7 +883,15 @@ def : Pat<(or IntRegs:$rs1, SETHIimm_not:$rs2),
           (ORNrr i32:$rs1,  (SETHIi SETHIimm_not:$rs2))>;
 
 let Defs = [ICC] in {
-  defm ANDCC  : F3_12np<"andcc",  0b010001>;
+  def ANDCCrr   : F3_1<2, 0b010001,
+                     (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
+                     "btst $rs2, $rs1",
+                     [(set i32:$rd, (SPandcc i32:$rs1, i32:$rs2))]>;
+  def ANDCCri   : F3_2<2, 0b010001,
+                     (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
+                     "btst $simm13, $rs1",
+                     [(set i32:$rd, (SPandcc i32:$rs1, (i32 simm13:$simm13)))]>;
+
   defm ANDNCC : F3_12np<"andncc", 0b010101>;
   defm ORCC   : F3_12np<"orcc",   0b010010>;
   defm ORNCC  : F3_12np<"orncc",  0b010110>;
@@ -1102,6 +1311,12 @@ let rd = 0 in {
 // Section B.33 - Floating-point Operate (FPop) Instructions
 
 // Convert Integer to Floating-point Instructions, p. 141
+def FITOH : F3_3u<2, 0b110100, 0b011000000,
+                 (outs HFPRegs:$rd), (ins FPRegs:$rs2),
+                 "fitoh $rs2, $rd",
+                 [(set HFPRegs:$rd, (SPitof FPRegs:$rs2))],
+                 IIC_fpu_fast_instr>,
+                 Requires<[HasFiTOh]>;
 def FITOS : F3_3u<2, 0b110100, 0b011000100,
                  (outs FPRegs:$rd), (ins FPRegs:$rs2),
                  "fitos $rs2, $rd",
@@ -1119,6 +1334,13 @@ def FITOQ : F3_3u<2, 0b110100, 0b011001100,
                  Requires<[HasHardQuad]>;
 
 // Convert Floating-point to Integer Instructions, p. 142
+def FHTOI : F3_3u<2, 0b110100, 0b011010000,
+                 (outs FPRegs:$rd), (ins HFPRegs:$rs2),
+                 "fhtoi $rs2, $rd",
+                 [(set FPRegs:$rd, (SPftoi HFPRegs:$rs2))],
+                 IIC_fpu_fast_instr>,
+                 Requires<[HasFhTOi]>;
+
 def FSTOI : F3_3u<2, 0b110100, 0b011010001,
                  (outs FPRegs:$rd), (ins FPRegs:$rs2),
                  "fstoi $rs2, $rd",
@@ -1136,6 +1358,17 @@ def FQTOI : F3_3u<2, 0b110100, 0b011010011,
                  Requires<[HasHardQuad]>;
 
 // Convert between Floating-point Formats Instructions, p. 143
+def FSTOH : F3_3u<2, 0b110100, 0b011000001,
+                 (outs HFPRegs:$rd), (ins FPRegs:$rs2),
+                 "fstoh $rs2, $rd",
+                 [(set f16:$rd, (fpround f32:$rs2))]>,
+                 Requires<[HasFsTOh]>;
+def FHTOS : F3_3u<2, 0b110100, 0b011000101,
+                 (outs FPRegs:$rd), (ins HFPRegs:$rs2),
+                 "fhtos $rs2, $rd",
+                 [(set f32:$rd, (fpextend f16:$rs2))]>,
+                 Requires<[HasFhTOs]>;
+
 def FSTOD : F3_3u<2, 0b110100, 0b011001001,
                  (outs DFPRegs:$rd), (ins FPRegs:$rs2),
                  "fstod $rs2, $rd",
@@ -1167,45 +1400,165 @@ def FQTOD : F3_3u<2, 0b110100, 0b011001011,
                  [(set f64:$rd, (fpround f128:$rs2))]>,
                  Requires<[HasHardQuad]>;
 
+// daiteq - Floating-point packing/unpacking Instructions
+def FPMOVHU : F3_3u<2, 0b110100, 0b000100000,
+                   (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                   "fmovhu $rs1, $rs2, $rd",
+                   []>,
+                   Requires<[HasFPPackHalf]>;
+def : PatFPHFPH<SPmovhuu, FPMOVHU>;
+
+def FPMOVHL : F3_3u<2, 0b110100, 0b000100001,
+                   (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                   "fmovhl $rs1, $rs2, $rd",
+                   []>,
+                   Requires<[HasFPPackHalf]>;
+def : PatFPHFPH<SPmovhll, FPMOVHL>;
+
+def FPMOVHUL : F3_3u<2, 0b110100, 0b000100010,
+                   (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                   "fmovhul $rs1, $rs2, $rd",
+                   []>,
+                   Requires<[HasFPPackHalf]>;
+def : PatFPHFPH<SPmovhul, FPMOVHUL>;
+
+def FPMOVHLU : F3_3u<2, 0b110100, 0b000100011,
+                   (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                   "fmovhlu $rs1, $rs2, $rd",
+                   []>,
+                   Requires<[HasFPPackHalf]>;
+def : PatFPHFPH<SPmovhlu, FPMOVHLU>;
+
+def FPSWAPH : F3_3u<2, 0b110100, 0b000100100,
+                   (outs PFPHRegs:$rd), (ins PFPHRegs:$rs2),
+                   "fswaph $rs2, $rd",
+                   []>,
+                   Requires<[HasFPPackHalf]>;
+def : PatFPH<SPswapph, FPSWAPH>;
+
+
+def FPMOVHZU : F3_3u<2, 0b110100, 0b000100101,
+                   (outs PFPHRegs:$rd), (ins PFPHRegs:$rs2),
+                   "fmovhzu $rs2, $rd",
+                   []>,
+                   Requires<[HasFPPackHalf]>;
+def : PatFPH<SPmovhzu, FPMOVHZU>;
+def FPMOVHZUCAST : F3_3u<2, 0b110100, 0b000100101,
+                   (outs HFPRegs:$rd), (ins PFPHRegs:$rs2),
+                   "fmovhzu $rs2, $rd",
+                   []>,
+                   Requires<[HasFPPackHalf]>;
+def : PatFPH<SPmovhzuconv, FPMOVHZUCAST>;
+
+def FPMOVHZL : F3_3u<2, 0b110100, 0b000100110,
+                   (outs PFPHRegs:$rd), (ins PFPHRegs:$rs2),
+                   "fmovhzl $rs2, $rd",
+                   []>,
+                   Requires<[HasFPPackHalf]>;
+def : PatFPH<SPmovhzl, FPMOVHZL>;
+def FPMOVHZLCAST : F3_3u<2, 0b110100, 0b000100110,
+                   (outs HFPRegs:$rd), (ins PFPHRegs:$rs2),
+                   "fmovhzl $rs2, $rd",
+                   []>,
+                   Requires<[HasFPPackHalf]>;
+def : PatFPH<SPmovhzlconv, FPMOVHZLCAST>;
+
+
 // Floating-point Move Instructions, p. 144
+def FMOVH : F3_3u<2, 0b110100, 0b000000000,
+                 (outs HFPRegs:$rd), (ins HFPRegs:$rs2),
+                 "fmovh $rs2, $rd", []>,
+                 Requires<[HasFMOVh]>;
 def FMOVS : F3_3u<2, 0b110100, 0b000000001,
                  (outs FPRegs:$rd), (ins FPRegs:$rs2),
-                 "fmovs $rs2, $rd", []>;
+                 "fmovs $rs2, $rd", [], IIC_fpu_movs>;
+//                 , Requires<[HasFMOVs]>;
+
+def FNEGH : F3_3u<2, 0b110100, 0b000000100,
+                 (outs HFPRegs:$rd), (ins HFPRegs:$rs2),
+                 "fnegh $rs2, $rd",
+                 [(set f16:$rd, (fneg f16:$rs2))]>,
+                 Requires<[HasFNEGh]>;
+// fnegh can be used also for packed variables - it change both halves
+def FNEGPH: F3_3u<2, 0b110100, 0b000000100,
+                 (outs PFPHRegs:$rd), (ins PFPHRegs:$rs2),
+                 "fnegh $rs2, $rd",
+                 [(set v2f16:$rd, (fneg v2f16:$rs2))]>,
+                 Requires<[HasFNEGh]>;
 def FNEGS : F3_3u<2, 0b110100, 0b000000101,
                  (outs FPRegs:$rd), (ins FPRegs:$rs2),
                  "fnegs $rs2, $rd",
                  [(set f32:$rd, (fneg f32:$rs2))],
-                 IIC_fpu_negs>;
+                 IIC_fpu_negs>,
+                 Requires<[HasFNEGs]>;
+def FABSH : F3_3u<2, 0b110100, 0b000001000,
+                 (outs HFPRegs:$rd), (ins HFPRegs:$rs2),
+                 "fabsh $rs2, $rd",
+                 [(set f16:$rd, (fabs f16:$rs2))],
+                 IIC_fpu_abs>,
+                 Requires<[HasFABSh]>;
+def FABSPH : F3_3u<2, 0b110100, 0b000001000,
+                 (outs PFPHRegs:$rd), (ins PFPHRegs:$rs2),
+                 "fabsh $rs2, $rd",
+                 [(set v2f16:$rd, (fabs v2f16:$rs2))],
+                 IIC_fpu_abs>,
+                 Requires<[HasFABSh]>;
 def FABSS : F3_3u<2, 0b110100, 0b000001001,
                  (outs FPRegs:$rd), (ins FPRegs:$rs2),
                  "fabss $rs2, $rd",
                  [(set f32:$rd, (fabs f32:$rs2))],
-                 IIC_fpu_abs>;
+                 IIC_fpu_abs>,
+                 Requires<[HasFABSs]>;
 
 
 // Floating-point Square Root Instructions, p.145
+def FSQRTH : F3_3u<2, 0b110100, 0b000101000,
+                  (outs HFPRegs:$rd), (ins HFPRegs:$rs2),
+                  "fsqrth $rs2, $rd",
+                  [(set f16:$rd, (fsqrt f16:$rs2))]>,
+                  Requires<[HasFSQRTh]>;
 // FSQRTS generates an erratum on LEON processors, so by disabling this instruction
 // this will be promoted to use FSQRTD with doubles instead.
-let Predicates = [HasNoFdivSqrtFix] in 
+let Predicates = [HasNoFdivSqrtFix] in {
 def FSQRTS : F3_3u<2, 0b110100, 0b000101001,
                   (outs FPRegs:$rd), (ins FPRegs:$rs2),
                   "fsqrts $rs2, $rd",
                   [(set f32:$rd, (fsqrt f32:$rs2))],
                   IIC_fpu_sqrts>;
+}
+
 def FSQRTD : F3_3u<2, 0b110100, 0b000101010,
                   (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
                   "fsqrtd $rs2, $rd",
                   [(set f64:$rd, (fsqrt f64:$rs2))],
                   IIC_fpu_sqrtd>;
+
 def FSQRTQ : F3_3u<2, 0b110100, 0b000101011,
                   (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
                   "fsqrtq $rs2, $rd",
                   [(set f128:$rd, (fsqrt f128:$rs2))]>,
                   Requires<[HasHardQuad]>;
 
+def FPSQRTH : F3_3<2, 0b110100, 0b010101001,
+                  (outs PFPHRegs:$rd), (ins PFPHRegs:$rs2),
+                  "fsqrtph $rs2, $rd",
+                  [(set v2f16:$rd, (fsqrt v2f16:$rs2))]>,
+                  Requires<[HasFPPackHalf]>;
+def FPSQRTS : F3_3<2, 0b110100, 0b010101010,
+                  (outs PFPSRegs:$rd), (ins PFPSRegs:$rs2),
+                  "fsqrtps $rs2, $rd",
+                  [(set v2f32:$rd, (fsqrt v2f32:$rs2))]>,
+                  Requires<[HasFPPackSingle]>;
+
 
 
 // Floating-point Add and Subtract Instructions, p. 146
+def FADDH  : F3_3<2, 0b110100, 0b001000000,
+                  (outs HFPRegs:$rd), (ins HFPRegs:$rs1, HFPRegs:$rs2),
+                  "faddh $rs1, $rs2, $rd",
+                  [(set f16:$rd, (fadd f16:$rs1, f16:$rs2))],
+                  IIC_fpu_fast_instr>,
+                  Requires<[HasFADDh]>;
 def FADDS  : F3_3<2, 0b110100, 0b001000001,
                   (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
                   "fadds $rs1, $rs2, $rd",
@@ -1221,7 +1574,44 @@ def FADDQ  : F3_3<2, 0b110100, 0b001000011,
                   "faddq $rs1, $rs2, $rd",
                   [(set f128:$rd, (fadd f128:$rs1, f128:$rs2))]>,
                   Requires<[HasHardQuad]>;
-
+def FPADDH : F3_3<2, 0b110100, 0b010010001,
+                  (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                  "faddph $rs1, $rs2, $rd",
+                  [(set v2f16:$rd, (fadd v2f16:$rs1, v2f16:$rs2))]>,
+                  Requires<[HasFPPackHalf]>;
+def FPADDS : F3_3<2, 0b110100, 0b010010010,
+                  (outs PFPSRegs:$rd), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                  "faddps $rs1, $rs2, $rd",
+                  [(set v2f32:$rd, (fadd v2f32:$rs1, v2f32:$rs2))]>,
+                  Requires<[HasFPPackSingle]>;
+
+def FADDRPH : F3_3<2, 0b110100, 0b010000001,
+                  (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                  "faddrph $rs1, $rs2, $rd",
+                  [(set v2f16:$rd, (fadd v2f16:$rs1, v2f16:$rs2))]>,
+                  Requires<[HasFPPackHalf]>;
+def FADDRPS : F3_3<2, 0b110100, 0b010000010,
+                  (outs PFPSRegs:$rd), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                  "faddrps $rs1, $rs2, $rd",
+                  [(set v2f32:$rd, (fadd v2f32:$rs1, v2f32:$rs2))]>,
+                  Requires<[HasFPPackSingle]>;
+def FADDXPH : F3_3<2, 0b110100, 0b010110001,
+                  (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                  "faddxph $rs1, $rs2, $rd",
+                  [(set v2f16:$rd, (fadd v2f16:$rs1, v2f16:$rs2))]>,
+                  Requires<[HasFPPackHalf]>;
+def FADDXPS : F3_3<2, 0b110100, 0b010110010,
+                  (outs PFPSRegs:$rd), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                  "faddxps $rs1, $rs2, $rd",
+                  [(set v2f32:$rd, (fadd v2f32:$rs1, v2f32:$rs2))]>,
+                  Requires<[HasFPPackSingle]>;
+
+
+def FSUBH  : F3_3<2, 0b110100, 0b001000100,
+                  (outs HFPRegs:$rd), (ins HFPRegs:$rs1, HFPRegs:$rs2),
+                  "fsubh $rs1, $rs2, $rd",
+                  [(set f16:$rd, (fsub f16:$rs1, f16:$rs2))]>,
+                  Requires<[HasFSUBh]>;
 def FSUBS  : F3_3<2, 0b110100, 0b001000101,
                   (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
                   "fsubs $rs1, $rs2, $rd",
@@ -1237,15 +1627,73 @@ def FSUBQ  : F3_3<2, 0b110100, 0b001000111,
                   "fsubq $rs1, $rs2, $rd",
                   [(set f128:$rd, (fsub f128:$rs1, f128:$rs2))]>,
                   Requires<[HasHardQuad]>;
+def FSUBPH : F3_3<2, 0b110100, 0b010010101,
+                  (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                  "fsubph $rs1, $rs2, $rd",
+                  [(set v2f16:$rd, (fsub v2f16:$rs1, v2f16:$rs2))]>,
+                  Requires<[HasFPPackHalf]>;
+def FSUBPS : F3_3<2, 0b110100, 0b010010110,
+                  (outs PFPSRegs:$rd), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                  "fsubps $rs1, $rs2, $rd",
+                  [(set v2f32:$rd, (fsub v2f32:$rs1, v2f32:$rs2))]>,
+                  Requires<[HasFPPackSingle]>;
+
+def FSUBRPH : F3_3<2, 0b110100, 0b010000101,
+                  (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                  "fsubrph $rs1, $rs2, $rd",
+                  [(set v2f16:$rd, (fsub v2f16:$rs1, v2f16:$rs2))]>,
+                  Requires<[HasFPPackHalf]>;
+def FSUBRPS : F3_3<2, 0b110100, 0b010000110,
+                  (outs PFPSRegs:$rd), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                  "fsubrps $rs1, $rs2, $rd",
+                  [(set v2f32:$rd, (fsub v2f32:$rs1, v2f32:$rs2))]>,
+                  Requires<[HasFPPackSingle]>;
+def FSUBXPH : F3_3<2, 0b110100, 0b010110101,
+                  (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                  "fsubxph $rs1, $rs2, $rd",
+                  [(set v2f16:$rd, (fsub v2f16:$rs1, v2f16:$rs2))]>,
+                  Requires<[HasFPPackHalf]>;
+def FSUBXPS : F3_3<2, 0b110100, 0b010110110,
+                  (outs PFPSRegs:$rd), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                  "fsubxps $rs1, $rs2, $rd",
+                  [(set v2f32:$rd, (fsub v2f32:$rs1, v2f32:$rs2))]>,
+                  Requires<[HasFPPackSingle]>;
+
+def FADDSUBRPH : F3_3<2, 0b110100, 0b010100001,
+                  (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                  "faddsubrph $rs1, $rs2, $rd",
+                  []>,
+                  Requires<[HasFPPackHalf]>;
+def FADDSUBRPS : F3_3<2, 0b110100, 0b010100010,
+                  (outs PFPSRegs:$rd), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                  "faddsubrps $rs1, $rs2, $rd",
+                  []>,
+                  Requires<[HasFPPackSingle]>;
+def FSUBADDRPH : F3_3<2, 0b110100, 0b010100101,
+                  (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                  "fsubaddrph $rs1, $rs2, $rd",
+                  []>,
+                  Requires<[HasFPPackHalf]>;
+def FSUBADDRPS : F3_3<2, 0b110100, 0b010100110,
+                  (outs PFPSRegs:$rd), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                  "fsubaddrps $rs1, $rs2, $rd",
+                  []>,
+                  Requires<[HasFPPackSingle]>;
 
 
 // Floating-point Multiply and Divide Instructions, p. 147
+def FMULH  : F3_3<2, 0b110100, 0b001001000,
+                  (outs HFPRegs:$rd), (ins HFPRegs:$rs1, HFPRegs:$rs2),
+                  "fmulh $rs1, $rs2, $rd",
+                  [(set f16:$rd, (fmul f16:$rs1, f16:$rs2))],
+                  IIC_fpu_mulh>,
+                  Requires<[HasFMULh]>;
 def FMULS  : F3_3<2, 0b110100, 0b001001001,
                   (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
                   "fmuls $rs1, $rs2, $rd",
                   [(set f32:$rd, (fmul f32:$rs1, f32:$rs2))],
                   IIC_fpu_muls>,
-		  Requires<[HasFMULS]>;
+                  Requires<[HasFMULS]>;
 def FMULD  : F3_3<2, 0b110100, 0b001001010,
                   (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
                   "fmuld $rs1, $rs2, $rd",
@@ -1256,14 +1704,52 @@ def FMULQ  : F3_3<2, 0b110100, 0b001001011,
                   "fmulq $rs1, $rs2, $rd",
                   [(set f128:$rd, (fmul f128:$rs1, f128:$rs2))]>,
                   Requires<[HasHardQuad]>;
-
+def FMULPH : F3_3<2, 0b110100, 0b010011001,
+                  (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                  "fmulph $rs1, $rs2, $rd",
+                  [(set v2f16:$rd, (fmul v2f16:$rs1, v2f16:$rs2))]>,
+                  Requires<[HasFPPackHalf]>;
+def FMULPS : F3_3<2, 0b110100, 0b010011010,
+                  (outs PFPSRegs:$rd), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                  "fmulps $rs1, $rs2, $rd",
+                  [(set v2f32:$rd, (fmul v2f32:$rs1, v2f32:$rs2))]>,
+                  Requires<[HasFPPackSingle]>;
+
+def FMULRPH : F3_3<2, 0b110100, 0b010001001,
+                  (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                  "fmulrph $rs1, $rs2, $rd",
+                  [(set v2f16:$rd, (fmul v2f16:$rs1, v2f16:$rs2))]>,
+                  Requires<[HasFPPackHalf]>;
+def FMULRPS : F3_3<2, 0b110100, 0b010001010,
+                  (outs PFPSRegs:$rd), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                  "fmulrps $rs1, $rs2, $rd",
+                  [(set v2f32:$rd, (fmul v2f32:$rs1, v2f32:$rs2))]>,
+                  Requires<[HasFPPackSingle]>;
+def FMULXPH : F3_3<2, 0b110100, 0b010111001,
+                  (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                  "fmulxph $rs1, $rs2, $rd",
+                  [(set v2f16:$rd, (fmul v2f16:$rs1, v2f16:$rs2))]>,
+                  Requires<[HasFPPackHalf]>;
+def FMULXPS : F3_3<2, 0b110100, 0b010111010,
+                  (outs PFPSRegs:$rd), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                  "fmulxps $rs1, $rs2, $rd",
+                  [(set v2f32:$rd, (fmul v2f32:$rs1, v2f32:$rs2))]>,
+                  Requires<[HasFPPackSingle]>;
+
+
+def FHMULS : F3_3<2, 0b110100, 0b001101000,
+                  (outs FPRegs:$rd), (ins HFPRegs:$rs1, HFPRegs:$rs2),
+                  "fhmuls $rs1, $rs2, $rd",
+                  [(set f32:$rd, (fmul (fpextend f16:$rs1),
+                                        (fpextend f16:$rs2)))]>,
+                  Requires<[HasFhMULs]>;
 def FSMULD : F3_3<2, 0b110100, 0b001101001,
                   (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
                   "fsmuld $rs1, $rs2, $rd",
                   [(set f64:$rd, (fmul (fpextend f32:$rs1),
                                         (fpextend f32:$rs2)))],
                   IIC_fpu_muld>,
-		  Requires<[HasFSMULD]>;
+                  Requires<[HasFSMULD]>;
 def FDMULQ : F3_3<2, 0b110100, 0b001101110,
                   (outs QFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
                   "fdmulq $rs1, $rs2, $rd",
@@ -1271,6 +1757,11 @@ def FDMULQ : F3_3<2, 0b110100, 0b001101110,
                                          (fpextend f64:$rs2)))]>,
                   Requires<[HasHardQuad]>;
 
+def FDIVH  : F3_3<2, 0b110100, 0b001001100,
+                  (outs HFPRegs:$rd), (ins HFPRegs:$rs1, HFPRegs:$rs2),
+                  "fdivh $rs1, $rs2, $rd",
+                  [(set f16:$rd, (fdiv f16:$rs1, f16:$rs2))]>,
+                  Requires<[HasFDIVh]>;
 // FDIVS generates an erratum on LEON processors, so by disabling this instruction
 // this will be promoted to use FDIVD with doubles instead.
 def FDIVS  : F3_3<2, 0b110100, 0b001001101,
@@ -1288,6 +1779,37 @@ def FDIVQ  : F3_3<2, 0b110100, 0b001001111,
                  "fdivq $rs1, $rs2, $rd",
                  [(set f128:$rd, (fdiv f128:$rs1, f128:$rs2))]>,
                  Requires<[HasHardQuad]>;
+def FPDIVH : F3_3<2, 0b110100, 0b010011101,
+                  (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                  "fdivph $rs1, $rs2, $rd",
+                  [(set v2f16:$rd, (fdiv v2f16:$rs1, v2f16:$rs2))]>,
+                  Requires<[HasFPPackHalf]>;
+def FPDIVS : F3_3<2, 0b110100, 0b010011110,
+                  (outs PFPSRegs:$rd), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                  "fdivps $rs1, $rs2, $rd",
+                  [(set v2f32:$rd, (fdiv v2f32:$rs1, v2f32:$rs2))]>,
+                  Requires<[HasFPPackSingle]>;
+
+def FPDIVRH : F3_3<2, 0b110100, 0b010001101,
+                  (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                  "fdivrph $rs1, $rs2, $rd",
+                  [(set v2f16:$rd, (fdiv v2f16:$rs1, v2f16:$rs2))]>,
+                  Requires<[HasFPPackHalf]>;
+def FPDIVRS : F3_3<2, 0b110100, 0b010001110,
+                  (outs PFPSRegs:$rd), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                  "fdivrps $rs1, $rs2, $rd",
+                  [(set v2f32:$rd, (fdiv v2f32:$rs1, v2f32:$rs2))]>,
+                  Requires<[HasFPPackSingle]>;
+def FPDIVXH : F3_3<2, 0b110100, 0b010111101,
+                  (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                  "fdivxph $rs1, $rs2, $rd",
+                  [(set v2f16:$rd, (fdiv v2f16:$rs1, v2f16:$rs2))]>,
+                  Requires<[HasFPPackHalf]>;
+def FPDIVXS : F3_3<2, 0b110100, 0b010111110,
+                  (outs PFPSRegs:$rd), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                  "fdivxps $rs1, $rs2, $rd",
+                  [(set v2f32:$rd, (fdiv v2f32:$rs1, v2f32:$rs2))]>,
+                  Requires<[HasFPPackSingle]>;
 
 // Floating-point Compare Instructions, p. 148
 // Note: the 2nd template arg is different for these guys.
@@ -1314,6 +1836,48 @@ let Defs = [FCC0], rd = 0, isCodeGenOnly = 1 in {
                    Requires<[HasHardQuad]>;
 }
 
+let Defs = [FCC0], rd = 0 in {
+  def FCMPH  : F3_3c<2, 0b110101, 0b001010000,
+                   (outs), (ins HFPRegs:$rs1, HFPRegs:$rs2),
+                   "fcmph $rs1, $rs2",
+                   [(SPcmpfcc f16:$rs1, f16:$rs2)],
+                   IIC_fpu_fast_instr>,
+                   Requires<[HasFCMPh]>;
+  def FCMPPH : F3_3c<2, 0b110101, 0b001011001,
+                   (outs), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                   "fcmpph $rs1, $rs2",
+                   [(SPcmpfcc v2f16:$rs1, v2f16:$rs2)],
+                   IIC_fpu_fast_instr>,
+                   Requires<[HasFPPackHalf]>;
+  def FCMPPS : F3_3c<2, 0b110101, 0b001011010,
+                   (outs), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                   "fcmpps $rs1, $rs2",
+                   [(SPcmpfcc v2f32:$rs1, v2f32:$rs2)],
+                   IIC_fpu_fast_instr>,
+                   Requires<[HasFPPackSingle]>;
+}
+
+let Defs = [FCC0], rd = 0, hasSideEffects = 1 in {
+  def FCMPEH  : F3_3c<2, 0b110101, 0b001010100,
+                   (outs), (ins HFPRegs:$rs1, HFPRegs:$rs2),
+                   "fcmpeh $rs1, $rs2",
+                   [(SPcmpfcc f16:$rs1, f16:$rs2)],
+                   IIC_fpu_fast_instr>,
+                   Requires<[HasFCMPh]>;
+  def FCMPEPH : F3_3c<2, 0b110101, 0b001011101,
+                   (outs), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                   "fcmpeph $rs1, $rs2",
+                   [(SPcmpfcc v2f16:$rs1, v2f16:$rs2)],
+                   IIC_fpu_fast_instr>,
+                   Requires<[HasFPPackHalf]>;
+  def FCMPEPS : F3_3c<2, 0b110101, 0b001011110,
+                   (outs), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                   "fcmpeps $rs1, $rs2",
+                   [(SPcmpfcc v2f32:$rs1, v2f32:$rs2)],
+                   IIC_fpu_fast_instr>,
+                   Requires<[HasFPPackSingle]>;
+}
+
 //===----------------------------------------------------------------------===//
 // Instructions for Thread Local Storage(TLS).
 //===----------------------------------------------------------------------===//
@@ -1706,10 +2270,25 @@ def : Pat<(extractelt (v2i32 IntPair:$Rn), 1),
 // build_vector
 def : Pat<(build_vector (i32 IntRegs:$a1), (i32 IntRegs:$a2)),
           (INSERT_SUBREG
-	    (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), (i32 IntRegs:$a1), sub_even),
+            (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), (i32 IntRegs:$a1), sub_even),
             (i32 IntRegs:$a2), sub_odd)>;
 
 
+// v2f32 - insert/extract/convert/select v2f32<->f32
+def : Pat<(insertelt (v2f32 PFPSRegs:$a1), (f32 FPRegs:$a2), 0),
+          (INSERT_SUBREG (v2f32 PFPSRegs:$a1), (f32 FPRegs:$a2), sub_even)>;
+def : Pat<(insertelt (v2f32 PFPSRegs:$a1), (f32 FPRegs:$a2), 1),
+          (INSERT_SUBREG (v2f32 PFPSRegs:$a1), (f32 FPRegs:$a2), sub_odd)>;
+
+def : Pat<(extractelt (v2f32 PFPSRegs:$a1), 0),
+          (f32 (EXTRACT_SUBREG PFPSRegs:$a1, sub_even))>;
+def : Pat<(extractelt (v2f32 PFPSRegs:$a1), 1),
+          (f32 (EXTRACT_SUBREG PFPSRegs:$a1, sub_odd))>;
+def : Pat<(build_vector (f32 FPRegs:$a1), (f32 FPRegs:$a2)),
+          (INSERT_SUBREG
+            (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), (f32 FPRegs:$a1), sub_even),
+            (f32 FPRegs:$a2), sub_odd)>;
+
 include "SparcInstr64Bit.td"
 include "SparcInstrVIS.td"
 include "SparcInstrAliases.td"
diff --git a/llvm/lib/Target/Sparc/SparcRegisterInfo.td b/llvm/lib/Target/Sparc/SparcRegisterInfo.td
index 98959d512955..427036f1f5a2 100644
--- a/llvm/lib/Target/Sparc/SparcRegisterInfo.td
+++ b/llvm/lib/Target/Sparc/SparcRegisterInfo.td
@@ -343,11 +343,23 @@ def IntPair : RegisterClass<"SP", [v2i32], 64,
 // spill slot is a stricter constraint than only requiring a 32-bit spill slot.
 def I64Regs : RegisterClass<"SP", [i64], 64, (add IntRegs)>;
 
+// Register class for swar data types - swar uses normal i32 registers
+def SwarRegs : RegisterClass<"SP",
+               [vs1p32, vs2p32, vs3p32, vs4p32, vs8p32, vs16p32], 32,
+                                  (add (sequence "I%u", 0, 7),
+                                      (sequence "G%u", 0, 7),
+                                      (sequence "L%u", 0, 7),
+                                      (sequence "O%u", 0, 7))>;
+
 // Floating point register classes.
+def HFPRegs : RegisterClass<"SP", [f16], 32, (sequence "F%u", 0, 31)>;
 def FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>;
 def DFPRegs : RegisterClass<"SP", [f64], 64, (sequence "D%u", 0, 31)>;
 def QFPRegs : RegisterClass<"SP", [f128], 128, (sequence "Q%u", 0, 15)>;
 
+def PFPHRegs : RegisterClass<"SP", [v2f16], 32, (sequence "F%u", 0, 31)>;
+def PFPSRegs : RegisterClass<"SP", [v2f32], 64, (sequence "D%u", 0, 31)>;
+
 // The Low?FPRegs classes are used only for inline-asm constraints.
 def LowDFPRegs : RegisterClass<"SP", [f64], 64, (sequence "D%u", 0, 15)>;
 def LowQFPRegs : RegisterClass<"SP", [f128], 128, (sequence "Q%u", 0, 7)>;
diff --git a/llvm/lib/Target/Sparc/SparcSchedule.td b/llvm/lib/Target/Sparc/SparcSchedule.td
index 31e43c9bd95d..abf540523f31 100644
--- a/llvm/lib/Target/Sparc/SparcSchedule.td
+++ b/llvm/lib/Target/Sparc/SparcSchedule.td
@@ -22,10 +22,13 @@ def IIC_iu_umul : InstrItinClass;
 def IIC_iu_div : InstrItinClass;
 def IIC_ticc : InstrItinClass;
 def IIC_ldstub : InstrItinClass;
+def IIC_fpu_mulh : InstrItinClass;
 def IIC_fpu_muls : InstrItinClass;
 def IIC_fpu_muld : InstrItinClass;
+def IIC_fpu_divh : InstrItinClass;
 def IIC_fpu_divs : InstrItinClass;
 def IIC_fpu_divd : InstrItinClass;
+def IIC_fpu_sqrth : InstrItinClass;
 def IIC_fpu_sqrts : InstrItinClass;
 def IIC_fpu_sqrtd : InstrItinClass;
 def IIC_fpu_abs : InstrItinClass;
@@ -66,6 +69,38 @@ def LEON2Itineraries : ProcessorItineraries<
   InstrItinData<IIC_fpu_stod, [InstrStage<1, [LEONFPU]>], [2, 1]>
 ]>;
 
+/* based on LEON2Itineraries */
+def L2DAIFPUItineraries : ProcessorItineraries<
+[LEONIU, LEONFPU], [], [
+  InstrItinData<IIC_iu_or_fpu_instr, [InstrStage<1, [LEONIU, LEONFPU]>], [1, 1]>,
+  InstrItinData<IIC_iu_instr, [InstrStage<1, [LEONIU]>], [1, 1]>,
+  InstrItinData<IIC_fpu_normal_instr, [InstrStage<1, [LEONFPU]>], [7, 1]>,
+  InstrItinData<IIC_fpu_fast_instr, [InstrStage<1, [LEONFPU]>], [7, 1]>,
+  InstrItinData<IIC_jmp_or_call, [InstrStage<1, [LEONIU, LEONFPU]>], [2, 1]>,
+  InstrItinData<IIC_ldd, [InstrStage<1, [LEONIU, LEONFPU]>], [2, 1]>,
+  InstrItinData<IIC_st, [InstrStage<1, [LEONIU, LEONFPU]>], [2, 1]>,
+  InstrItinData<IIC_std, [InstrStage<1, [LEONIU, LEONFPU]>], [3, 1]>,
+  InstrItinData<IIC_iu_smul, [InstrStage<1, [LEONIU]>], [5, 1]>,
+  InstrItinData<IIC_iu_umul, [InstrStage<1, [LEONIU]>], [5, 1]>,
+  InstrItinData<IIC_iu_div, [InstrStage<1, [LEONIU]>], [35, 1]>,
+  InstrItinData<IIC_ticc, [InstrStage<1, [LEONIU, LEONFPU]>], [4, 1]>,
+  InstrItinData<IIC_ldstub, [InstrStage<1, [LEONIU, LEONFPU]>], [3, 1]>,
+  InstrItinData<IIC_fpu_muls, [InstrStage<1, [LEONFPU]>], [6, 1]>,
+  InstrItinData<IIC_fpu_muld, [InstrStage<1, [LEONFPU]>], [7, 1]>,
+  InstrItinData<IIC_fpu_divh, [InstrStage<1, [LEONFPU]>], [19, 1]>,
+  InstrItinData<IIC_fpu_divs, [InstrStage<1, [LEONFPU]>], [32, 1]>,
+  InstrItinData<IIC_fpu_divd, [InstrStage<1, [LEONFPU]>], [61, 1]>,
+  InstrItinData<IIC_fpu_sqrth, [InstrStage<1, [LEONFPU]>], [19, 1]>,
+  InstrItinData<IIC_fpu_sqrts, [InstrStage<1, [LEONFPU]>], [32, 1]>,
+  InstrItinData<IIC_fpu_sqrtd, [InstrStage<1, [LEONFPU]>], [61, 1]>,
+  InstrItinData<IIC_fpu_abs, [InstrStage<1, [LEONFPU]>], [6, 1]>,
+  InstrItinData<IIC_fpu_movs, [InstrStage<1, [LEONFPU]>], [2, 1]>,
+  InstrItinData<IIC_fpu_negs, [InstrStage<1, [LEONFPU]>], [2, 1]>,
+  InstrItinData<IIC_fpu_stod, [InstrStage<1, [LEONFPU]>], [1, 1]>
+]>;
+
+
+
 def LEON3Itineraries : ProcessorItineraries<
 [LEONIU, LEONFPU], [], [
   InstrItinData<IIC_iu_or_fpu_instr, [InstrStage<1, [LEONIU, LEONFPU]>], [1, 1]>,
diff --git a/llvm/lib/Target/Sparc/SparcSubtarget.cpp b/llvm/lib/Target/Sparc/SparcSubtarget.cpp
index 075a002a358d..a1714d5d213d 100644
--- a/llvm/lib/Target/Sparc/SparcSubtarget.cpp
+++ b/llvm/lib/Target/Sparc/SparcSubtarget.cpp
@@ -47,8 +47,27 @@ SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU,
   InsertNOPLoad = false;
   FixAllFDIVSQRT = false;
   DetectRoundChange = false;
+  InsertNOPYDIV = false;
   HasLeonCycleCounter = false;
 
+  // daiteq features
+  for (int i=0;i<32;i++) {
+    UseSoftFPopsHalf[i] = false;
+    UseSoftFPopsSingle[i] = false;
+    UseSoftFPopsDouble[i] = false;
+  }
+  UseFPPackedHalf = false;    // must be explicitly enabled
+  UseFPPackedSingle = false;  // must be explicitly enabled
+  AllowUnalignedPackedFP = false; // must be explicitly enabled
+
+  AnySoftFloatHalf = false;
+  AnySoftFloatSingle = false;
+  AnySoftFloatDouble = false;
+
+  AnyHardFloatHalf = true;
+  AnyHardFloatSingle = true;
+  AnyHardFloatDouble = true;
+
   // Determine default and user specified characteristics
   std::string CPUName = CPU;
   if (CPUName.empty())
@@ -57,6 +76,58 @@ SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU,
   // Parse features string.
   ParseSubtargetFeatures(CPUName, FS);
 
+  // Update soft-float flags according parsed features
+  // In this version - flags in UseSoftFPopsXXXX have higher priority (are allways set to all true if 'soft-float' is us
+  // -> should be updated for checking if daiteq-fpu flag is used on cmd line
+  //bool anyhardfp = false;
+  bool allsoftfp = true; // !allsoftfp = anyhardfp;
+  for (int i=0;i<32;i++) {
+    if (i==llvm::SoftFops::SOFTFP_PACK || i>llvm::SoftFops::SOFTFP_NEG) continue;
+    if (UseSoftFPopsHalf[i]) AnySoftFloatHalf = true; else allsoftfp = false;
+  }
+  if (allsoftfp) AnyHardFloatHalf = false;
+
+  allsoftfp = true;
+  for (int i=0;i<32;i++) {
+    if (i==llvm::SoftFops::SOFTFP_PACK || i>llvm::SoftFops::SOFTFP_NEG) continue;
+    if (UseSoftFPopsSingle[i]) AnySoftFloatSingle = true; else allsoftfp = false;
+  }
+  if (allsoftfp) AnyHardFloatSingle = false;
+
+  allsoftfp = true;
+  for (int i=0;i<32;i++) {
+    if (i==llvm::SoftFops::SOFTFP_PACK || i>llvm::SoftFops::SOFTFP_NEG) continue;
+    if (UseSoftFPopsDouble[i]) AnySoftFloatDouble = true; else allsoftfp = false;
+  }
+  if (allsoftfp) AnyHardFloatDouble = false;
+
+  // if -msoft-float is used - all is in soft-float
+  if (UseSoftFloat) {
+    for (int i=0;i<32;i++) {
+      UseSoftFPopsHalf[i] = true;
+      UseSoftFPopsSingle[i] = true;
+      UseSoftFPopsDouble[i] = true;
+    }
+    UseFPPackedHalf = false;
+    UseFPPackedSingle = false;
+    AnySoftFloatHalf = true;
+    AnySoftFloatSingle = true;
+    AnySoftFloatDouble = true;
+    AnyHardFloatHalf = false;
+    AnyHardFloatSingle = false;
+    AnyHardFloatDouble = false;
+  }
+
+  // correct soft-float flag if necessary
+//  if (UseSoftFloat) {
+//    if (!allsoftfp) UseSoftFloat = false; /* disable full soft-float */
+//  } else {
+//    if (AnySoftFloatHalf || AnySoftFloatSingle || AnySoftFloatDouble ||
+//        AnySoftFloatPackedHalf || AnySoftFloatPackedSingle)
+//      UseSoftFloat = true; /* enable soft-float if any soft-float FPop is required */
+//  }
+
+
   // Popc is a v9-only instruction.
   if (!IsV9)
     UsePopc = false;
diff --git a/llvm/lib/Target/Sparc/SparcSubtarget.h b/llvm/lib/Target/Sparc/SparcSubtarget.h
index db19f99e3c9c..466af76163b8 100644
--- a/llvm/lib/Target/Sparc/SparcSubtarget.h
+++ b/llvm/lib/Target/Sparc/SparcSubtarget.h
@@ -39,7 +39,7 @@ class SparcSubtarget : public SparcGenSubtargetInfo {
   bool Is64Bit;
   bool HasHardQuad;
   bool UsePopc;
-  bool UseSoftFloat;
+  bool UseSoftFloat; /* this indicates soft-float for all instructions */
   bool HasNoFSMULD;
   bool HasNoFMULS;
 
@@ -50,8 +50,27 @@ class SparcSubtarget : public SparcGenSubtargetInfo {
   bool InsertNOPLoad;
   bool FixAllFDIVSQRT;
   bool DetectRoundChange;
+  bool InsertNOPYDIV;
   bool HasLeonCycleCounter;
 
+  // daiteq features - soft float FP operations
+  bool UseSoftFPopsHalf[32];
+  bool UseSoftFPopsSingle[32];
+  bool UseSoftFPopsDouble[32];
+
+  bool UseFPPackedHalf;
+  bool UseFPPackedSingle;
+
+  bool AnySoftFloatHalf;          /* if there is at least one half FPop in soft-float */
+  bool AnySoftFloatSingle;        /* if there is at least one single FPop in soft-float */
+  bool AnySoftFloatDouble;        /* if there is at least one double FPop in soft-float */
+
+  bool AnyHardFloatHalf;          /* if there is at least one half FPop in hard-float */
+  bool AnyHardFloatSingle;        /* if there is at least one single FPop in hard-float */
+  bool AnyHardFloatDouble;        /* if there is at least one double FPop in hard-float */
+
+  bool AllowUnalignedPackedFP;
+
   SparcInstrInfo InstrInfo;
   SparcTargetLowering TLInfo;
   SelectionDAGTargetInfo TSInfo;
@@ -97,8 +116,27 @@ public:
   bool insertNOPLoad() const { return InsertNOPLoad; }
   bool fixAllFDIVSQRT() const { return FixAllFDIVSQRT; }
   bool detectRoundChange() const { return DetectRoundChange; }
+  bool insertNOPYDIV() const { return InsertNOPYDIV; }
   bool hasLeonCycleCounter() const { return HasLeonCycleCounter; }
 
+  // daiteq options
+  bool useSoftFopHalf(unsigned softfp) const { return UseSoftFPopsHalf[softfp]; }
+  bool useSoftFopSingle(unsigned softfp) const { return UseSoftFPopsSingle[softfp]; }
+  bool useSoftFopDouble(unsigned softfp) const { return UseSoftFPopsDouble[softfp]; }
+
+  bool useSoftHalf() const { return AnySoftFloatHalf; }
+  bool useSoftSingle() const { return AnySoftFloatSingle; }
+  bool useSoftDouble() const { return AnySoftFloatDouble; }
+
+  bool useHardHalf() const { return AnyHardFloatHalf; }
+  bool useHardSingle() const { return AnyHardFloatSingle; }
+  bool useHardDouble() const { return AnyHardFloatDouble; }
+
+  bool usePackedHalf() const { return UseFPPackedHalf; }
+  bool usePackedSingle() const { return UseFPPackedSingle; }
+  
+  bool isAllowedUnalignedFP() const { return AllowUnalignedPackedFP; }
+
   /// ParseSubtargetFeatures - Parses features string setting specified
   /// subtarget options.  Definition of function is auto generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
index c1e3f8c36982..0315c639bf21 100644
--- a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
+++ b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
@@ -51,6 +51,9 @@ static std::string computeDataLayout(const Triple &T, bool is64Bit) {
   else
     Ret += "-S64";
 
+  if (T.getArch() == Triple::sparc && T.getVendor() == Triple::Daiteq)
+    Ret += "-f16:16";
+
   return Ret;
 }
 
@@ -117,6 +120,93 @@ SparcTargetMachine::getSubtargetImpl(const Function &F) const {
                        ? FSAttr.getValueAsString().str()
                        : TargetFS;
 
+  if (F.hasFnAttribute("soft-fops-half")) {
+    unsigned val = std::stoul(F.getFnAttribute("soft-fops-half").getValueAsString().str(), NULL, 0);
+    if (val>0) {
+      if (val & llvm::SoftFops::FPOP_ADD)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fadd"; }
+      if (val & llvm::SoftFops::FPOP_SUB)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fsub"; }
+      if (val & llvm::SoftFops::FPOP_MUL)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fmul"; }
+      if (val & llvm::SoftFops::FPOP_DIV)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fdiv"; }
+      if (val & llvm::SoftFops::FPOP_MULEX) { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fmulex"; }
+      if (val & llvm::SoftFops::FPOP_SQRT) { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fsqrt"; }
+      if (val & llvm::SoftFops::FPOP_CMP)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fcmp"; }
+      if (val & llvm::SoftFops::FPOP_CI2F) { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fci2f"; }
+      if (val & llvm::SoftFops::FPOP_CF2I) { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fcf2i"; }
+      if (val & llvm::SoftFops::FPOP_CFUP) { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fcfup"; }
+      if (val & llvm::SoftFops::FPOP_CFDN) { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fcfdn"; }
+      if (val & llvm::SoftFops::FPOP_ABS) { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fabs"; }
+      //if (val & llvm::SoftFops::FPOP_PACK) { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-pack"; }
+      if (val & llvm::SoftFops::FPOP_MOV) { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fmov"; }
+      if (val & llvm::SoftFops::FPOP_NEG) { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fneg"; }
+    }
+  }
+  if (F.hasFnAttribute("soft-fops-single")) {
+    unsigned val = std::stoul(F.getFnAttribute("soft-fops-single").getValueAsString().str(), NULL, 0);
+    if (val>0) {
+      if (val & llvm::SoftFops::FPOP_ADD)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fadd"; }
+      if (val & llvm::SoftFops::FPOP_SUB)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fsub"; }
+      if (val & llvm::SoftFops::FPOP_MUL)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fmul"; }
+      if (val & llvm::SoftFops::FPOP_DIV)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fdiv"; }
+      if (val & llvm::SoftFops::FPOP_MULEX) { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fmulex"; }
+      if (val & llvm::SoftFops::FPOP_SQRT) { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fsqrt"; }
+      if (val & llvm::SoftFops::FPOP_CMP)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fcmp"; }
+      if (val & llvm::SoftFops::FPOP_CI2F) { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fci2f"; }
+      if (val & llvm::SoftFops::FPOP_CF2I) { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fcf2i"; }
+      if (val & llvm::SoftFops::FPOP_CFUP) { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fcfup"; }
+      if (val & llvm::SoftFops::FPOP_CFDN) { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fcfdn"; }
+      if (val & llvm::SoftFops::FPOP_ABS) { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fabs"; }
+      //if (val & llvm::SoftFops::FPOP_PACK) { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-pack"; }
+      if (val & llvm::SoftFops::FPOP_MOV) { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fmov"; }
+      if (val & llvm::SoftFops::FPOP_NEG) { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fneg"; }
+    }
+  }
+  if (F.hasFnAttribute("soft-fops-double")) {
+    unsigned val = std::stoul(F.getFnAttribute("soft-fops-double").getValueAsString().str(), NULL, 0);
+    if (val>0) {
+      if (val & llvm::SoftFops::FPOP_ADD)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fadd"; }
+      if (val & llvm::SoftFops::FPOP_SUB)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fsub"; }
+      if (val & llvm::SoftFops::FPOP_MUL)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fmul"; }
+      if (val & llvm::SoftFops::FPOP_DIV)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fdiv"; }
+      if (val & llvm::SoftFops::FPOP_MULEX) { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fmulex"; }
+      if (val & llvm::SoftFops::FPOP_SQRT) { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fsqrt"; }
+      if (val & llvm::SoftFops::FPOP_CMP)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fcmp"; }
+      if (val & llvm::SoftFops::FPOP_CI2F) { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fci2f"; }
+      if (val & llvm::SoftFops::FPOP_CF2I) { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fcf2i"; }
+      if (val & llvm::SoftFops::FPOP_CFUP) { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fcfup"; }
+      if (val & llvm::SoftFops::FPOP_CFDN) { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fcfdn"; }
+      if (val & llvm::SoftFops::FPOP_ABS) { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fabs"; }
+      //if (val & llvm::SoftFops::FPOP_PACK) { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-pack"; }
+      if (val & llvm::SoftFops::FPOP_MOV) { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fmov"; }
+      if (val & llvm::SoftFops::FPOP_NEG) { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fneg"; }
+    }
+  }
+  if (F.hasFnAttribute("soft-fops-packhalf")) {
+    unsigned val = std::stoul(F.getFnAttribute("soft-fops-packhalf").getValueAsString().str(), NULL, 0);
+    if (val>0) {
+      if (val & llvm::SoftFops::FPOP_ADD)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packhalf-fadd"; }
+      if (val & llvm::SoftFops::FPOP_SUB)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packhalf-fsub"; }
+      if (val & llvm::SoftFops::FPOP_MUL)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packhalf-fmul"; }
+      if (val & llvm::SoftFops::FPOP_DIV)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packhalf-fdiv"; }
+      if (val & llvm::SoftFops::FPOP_SQRT) { if (!FS.empty()) FS += ","; FS += "+soft-fops-packhalf-fsqrt"; }
+      if (val & llvm::SoftFops::FPOP_PACK) { if (!FS.empty()) FS += ","; FS += "+soft-fops-packhalf-pack"; }
+      if (val & llvm::SoftFops::FPOP_CMP)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packhalf-fcmp"; }
+      if (val & llvm::SoftFops::FPOP_MOV)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packhalf-fmov"; }  /* FMOVHU, FMOVHL, FSWAPH */
+    }
+  }
+  if (F.hasFnAttribute("soft-fops-packsingle")) {
+    unsigned val = std::stoul(F.getFnAttribute("soft-fops-packsingle").getValueAsString().str(), NULL, 0);
+    if (val>0) {
+      if (val & llvm::SoftFops::FPOP_ADD)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packsingle-fadd"; }
+      if (val & llvm::SoftFops::FPOP_SUB)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packsingle-fsub"; }
+      if (val & llvm::SoftFops::FPOP_MUL)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packsingle-fmul"; }
+      if (val & llvm::SoftFops::FPOP_DIV)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packsingle-fdiv"; }
+      if (val & llvm::SoftFops::FPOP_SQRT) { if (!FS.empty()) FS += ","; FS += "+soft-fops-packsingle-fsqrt"; }
+      if (val & llvm::SoftFops::FPOP_PACK) { if (!FS.empty()) FS += ","; FS += "+soft-fops-packsingle-pack"; }
+      if (val & llvm::SoftFops::FPOP_CMP)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packsingle-fcmp"; }
+    }
+  }
+
+
   // FIXME: This is related to the code below to reset the target options,
   // we need to know whether or not the soft float flag is set on the
   // function, so we can enable it as a subtarget feature.
@@ -185,6 +275,10 @@ void SparcPassConfig::addPreEmitPass(){
   {
     addPass(new FixAllFDIVSQRT());
   }
+  if (this->getSparcTargetMachine().getSubtargetImpl()->insertNOPYDIV())
+  {
+    addPass(new InsertNOPYDIV());
+  }
 }
 
 void SparcV8TargetMachine::anchor() { }
diff --git a/llvm/utils/TableGen/CodeGenTarget.cpp b/llvm/utils/TableGen/CodeGenTarget.cpp
index fcfe6d124a8e..d12a9f777aed 100644
--- a/llvm/utils/TableGen/CodeGenTarget.cpp
+++ b/llvm/utils/TableGen/CodeGenTarget.cpp
@@ -190,6 +190,14 @@ StringRef llvm::getEnumName(MVT::SimpleValueType T) {
   case MVT::nxv2f64:  return "MVT::nxv2f64";
   case MVT::nxv4f64:  return "MVT::nxv4f64";
   case MVT::nxv8f64:  return "MVT::nxv8f64";
+
+  case MVT::vs1p32:   return "MVT::vs1p32";
+  case MVT::vs2p32:   return "MVT::vs2p32";
+  case MVT::vs3p32:   return "MVT::vs3p32";
+  case MVT::vs4p32:   return "MVT::vs4p32";
+  case MVT::vs8p32:   return "MVT::vs8p32";
+  case MVT::vs16p32:   return "MVT::vs16p32";
+
   case MVT::token:    return "MVT::token";
   case MVT::Metadata: return "MVT::Metadata";
   case MVT::iPTR:     return "MVT::iPTR";
-- 
2.20.1