testswar.c

/* -----------------------------------------------------------------------------
 *  Copyright (C) 2019-2021 daiteq s.r.o.                http://www.daiteq.com
 *
 *  This program is distributed WITHOUT ANY WARRANTY; without even
 *  the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
 *  PURPOSE.
 *
 * -----------------------------------------------------------------------------
 *  Filename    : testswar.c
 *  Authors     : Martin Danek, Roman Bartosinski
 *  Description : LEON2 test of SWAR instructions
 *  Release     :
 *  Version     : 2.0
 *  Date        : 27.4.2021
 * -----------------------------------------------------------------------------
 */

#include "../common_sys_header.inc"

#ifndef MAX_ACC
  #define MAX_ACC 4
#endif
#ifndef ACC_BITS
  #define ACC_BITS 22
#endif


// selection of enabled code - TODO: move to makefile
// #define SWAR_DUMMY
//#define SWAR_CORR
//#define SWAR_DEM
//#define SWAR_SINCOS
//#define SWAR_ALU

// #define PRINT_DETAILS

#define SHORT_DATA

#define ACCMSK ((1<<ACC_BITS)-1)

// architecture is defined in 'ise.h'
///* default architecture is 64bit */
//#ifdef RV32
  //typedef uint32_t    REGTYPE;
  //typedef int32_t     SREGTYPE;
  //#define REGBITS     32
  //#define REGFMT      "x%08lX"
//#else
  //typedef uint64_t    REGTYPE;
  //typedef int64_t     SREGTYPE;
  //#define REGBITS     64
  //#define REGFMT      "x%16lX"
//#endif

/* default data type is 32bit */
#ifdef DATA64
  typedef uint64_t    ITYPE;
  #define DATABITS    64
  #define DATAFMT     "x%16lX"
#else
  typedef uint32_t    ITYPE;
  #define DATABITS    32
  #define DATAFMT     "x%08X"
#endif

#include "swar.h"
#include "ise.h"

#define PGMNAME "TESTSWAR"

#ifndef SEL_IMPL
  #define SEL_IMPL  daiteq
#endif


#define YSTR(Y) # Y
#define XSTR(X) YSTR(X)

#define expdem64(X) \
  ((uint64_t)(0x5555000000000000 | (((X) & 0xFFFF0000) << 16) | ((X) & 0xFFFF)))


// TODO: add SWAR for 1U32,2U32,3U32,4U32,8U32,16U32
//                    1S32,2S32,3S32,4S32,8S32,16S32
//                    1U64,2U64,3U64,4U64,8U64,16U64,32U64
//                    1S64,2S64,3S64,4S64,8S64,16S64,32S64

enum swar_addition_codes {
  SWARCTRL   = 0x10000,       /* direct write swar control word */
  SWARSTAT   = 0x20000,       /* read swar status word */
  ACCRST     = 0x30000,       /* ? reset accumulators */
  ACCGET     = 0x40000,       /* read accumulator */
  
};

enum dt_codes {
  DT_1P32  = 0x0001,
  DT_2P32  = 0x0002,
  DT_3P32  = 0x0004,
  DT_4P32  = 0x0008,
  DT_8P32  = 0x0010,
  DT_16P32 = 0x0020,
  DT_1P64  = 0x0100,
  DT_2P64  = 0x0200,
  DT_3P64  = 0x0400,
  DT_4P64  = 0x0800,
  DT_8P64  = 0x1000,
  DT_16P64 = 0x2000,
  DT_32P64 = 0x4000,

  DT_MSK32 = 0x00FF,
  DT_MSK64 = 0xFF00,

  DT_ARRAY = 0x10000,   /* data are in an special array */
  DT_SWREF = 0x20000,   /* use software reference */
};


#ifdef DATA64
  #include "testdata64.inc"
#else
  #include "testdata32.inc"
#endif


#ifdef DESKTOP
  #include "desk_swar.inc"
#else
  #include "asm_swar.inc"
#endif /* DESKTOP */

const char *opname(unsigned opcode) {
  switch(opcode & SW_CTRL_OPMASK) {
    case SW_OP_ADD:      return "ADD";
    case SW_OP_SUB:      return "SUB";
    case SW_OP_MUL:      return "MUL";
    case SW_OP_COR1b:    return "COR1b";
    case SW_OP_COR2b:    return "COR2b";
    case SW_OP_COR3b:    return "COR3b";
    case SW_OP_COR4b:    return "COR4b";
    case SW_OP_DEMR2b:   return "DEMR2b";
    case SW_OP_DEMR3b:   return "DEMR3b";
    case SW_OP_DEMR4b:   return "DEMR4b";
    case SW_OP_DEMC2b:   return "DEMC2b";
    case SW_OP_DEMC3b:   return "DEMC3b";
    case SW_OP_DEMC4b:   return "DEMC4b";
    case SW_OP_DEMC2bG:  return "DEMC2bG";
    case SW_OP_DEMC3bG:  return "DEMC3bG";
    case SW_OP_DEMC4bG:  return "DEMC4bG";
    case SW_OP_SC1b:     return "SC1b";
    case SW_OP_SC2b:     return "SC2b";
    case SW_OP_SC3b:     return "SC3b";
    case SW_OP_SC4b:     return "SC4b";
  }
  return "???";
}

const char *opmod(unsigned opcode) {
  switch(opcode & (SW_CTRL_SATURATE | SW_CTRL_REDUCE | SW_CTRL_SIGNED)) {
    case 0x0:      return "UNSIGNED";
    case SW_CTRL_SATURATE:      return "UNSIGNED SATURATE";
    case SW_CTRL_REDUCE:      return "UNSIGNED REDUCE";
    case SW_CTRL_SATURATE | SW_CTRL_REDUCE:    return "UNSIGNED SATURATE REDUCE";
    case SW_CTRL_SIGNED:    return "SIGNED";
    case SW_CTRL_SIGNED | SW_CTRL_SATURATE:    return "SIGNED SATURATE";
    case SW_CTRL_SIGNED | SW_CTRL_REDUCE:    return "SIGNED REDUCE";
    case SW_CTRL_SIGNED | SW_CTRL_SATURATE | SW_CTRL_REDUCE:    return "SIGNED SATURATE REDUCE";
  }
  return "???";
}



const char *dtname(unsigned dtbit) {
  if (dtbit & DT_1P32)  return "1b in 32b";
  if (dtbit & DT_2P32)  return "2b in 32b";
  if (dtbit & DT_3P32)  return "3b in 32b";
  if (dtbit & DT_4P32)  return "4b in 32b";
  if (dtbit & DT_8P32)  return "8b in 32b";
  if (dtbit & DT_16P32) return "16b in 32b";

  if (dtbit & DT_1P64)  return "1b in 64b";
  if (dtbit & DT_2P64)  return "2b in 64b";
  if (dtbit & DT_3P64)  return "3b in 64b";
  if (dtbit & DT_4P64)  return "4b in 64b";
  if (dtbit & DT_8P64)  return "8b in 64b";
  if (dtbit & DT_16P64) return "16b in 64b";
  if (dtbit & DT_32P64) return "32b in 64b";
  return "UNKNOWN";
}

unsigned dt2bits(unsigned dtbit) {
  //if (dtbit & DT_1P32) return 1;
  //...
  // return (__builtin_ctz(dtbit) + 1);
  if (dtbit & DT_1P32)  return 1;
  if (dtbit & DT_2P32)  return 2;
  if (dtbit & DT_3P32)  return 3;
  if (dtbit & DT_4P32)  return 4;
  if (dtbit & DT_8P32)  return 8;
  if (dtbit & DT_16P32) return 16;

  if (dtbit & DT_1P64)  return 1;
  if (dtbit & DT_2P64)  return 2;
  if (dtbit & DT_3P64)  return 3;
  if (dtbit & DT_4P64)  return 4;
  if (dtbit & DT_8P64)  return 8;
  if (dtbit & DT_16P64) return 16;
  if (dtbit & DT_32P64) return 32;
  return 0;
}

//#define OPCODE(op,conf,dt)  ((op) | (conf) | (dt<<16))


int main(void) {
  unsigned itst;
  unsigned prevop = 0, status;
  //const unsigned *supops;
  REGTYPE opa, opb, reference, result;
  SREGTYPE acc[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
  unsigned iacc = 0;
  unsigned failcnt;

  system_init();

  printf(PGMNAME ": SWAR test for '%s' (ARCH:rv%u,DATA:%u)\n", XSTR(SEL_IMPL), REGBITS, DATABITS);


  printf("\n\nNOEL-V SWAR TEST\n");
  printf("================\n\n");

  printf("CONFIG:\n");
#ifdef SWAR_CORR
  printf("CORR TESTS\n");
#endif
#ifdef SWAR_DEM
  printf("DEM TESTS\n");
#endif
#ifdef SWAR_SINCOS
  printf("SINCOS TESTS\n");
#endif
#ifdef SWAR_ALU
  printf("SWAR ALU TESTS\n");
#endif
  printf("SWAR ACCUMULATOR #   : %d\n", MAX_ACC);
  printf("SWAR ACCUMULATOR bits: %d\n", ACC_BITS);

  printf("------\n\n");

#ifdef SWAR_DUMMY
  /* Issue SWAR instruction before SWAR configuration to validate the other illegal instruction path for SWAREN=false*/
  printf("DUMMY SWAR EXECUTION\n");
  op_swar(opa, opb, result);
#endif

  failcnt = 0;
//  supops = implementations[SEL_IMPL].sup_dt;

  //opal.ul[1] = 0x10000000; // LSW
  //opbl.ul[1] = 0x10000000; // LSW

// over all testdata
  for (itst=0;itst<SIZETESTDATA;++itst) {
    unsigned op = testdata[itst].swop;
    opa = (REGTYPE) testdata[itst].opa;
    opb = (REGTYPE) testdata[itst].opb;
    reference = (REGTYPE) testdata[itst].reference;
    unsigned bits = dt2bits(testdata[itst].dt);

    // skip unsupported operations
    //if (op<FIRST_CTRL &&
        //!(SEL_IMPL.hasdt[op] & testdata[itst].dt)) 
      //continue;
    
    printf("------\n");
    if (op==SWARCTRL) {
//      op_set_ctrl(testdata[itst].conf | op);
    } else if (op==SWARSTAT) {
      printf("GET swar cfg\n");
      op_get_stat(result);
      printf(" Status = " REGFMT "\n", result);
    } else if (op==ACCRST) {
      
    } else if (op==ACCGET) {
      for (iacc=0;iacc<MAX_ACC; iacc++) {
#ifdef PRINT_DETAILS
        printf("GET accum #%d\n", testdata[itst].opa);
#endif
        op_get_acc(iacc<<1,result);
        result &= ACCMSK;
        // check swar accumulators against acc
        reference=acc[iacc] & ACCMSK;
        if (result!=reference) {
          printf(" ERROR - ACC - EXP " REGFMT " ACT " REGFMT "\n", reference, result);
          failcnt++;
        }
      }
      // kontrola s vypoctenym acc v sw
    } else { /* swar operations */
      if (((op&SW_CTRL_OPMASK)==SW_OP_ADD) || ((op&SW_CTRL_OPMASK)==SW_OP_SUB) || ((op&SW_CTRL_OPMASK)==SW_OP_MUL))
        printf("%s %s - %s\n", opname(op), opmod(op), dtname(testdata[itst].dt));
      else
        printf("%s - %s\n", opname(op), dtname(testdata[itst].dt));
      unsigned cop = op | testdata[itst].dt;
      if (cop!=prevop || (testdata[itst].dt & DT_ARRAY)) {
        /* required another operation or configuration -> set swar control word */
        /* TODO: use DT !!! */
        op_set_ctrl(op);
        prevop=cop;
        op_get_stat(status);
        printf("SWAR CONFIG: 0x%08X\n",status);
        if (op!=status) {
          printf("STATUS ERROR: EXP 0x%08X ACT 0x%08X\n",op,status);
          failcnt++;
        }
        // initialize accumulators
        for (iacc=0;iacc<8; iacc++) acc[iacc]=0;
      }

      if (testdata[itst].dt & DT_ARRAY) {
        /* call the current swar operation for all values in an array */
        const ITYPE_RAW *pd = indirdata[opa].pdata;
        unsigned n = indirdata[opa].num;

        for(unsigned iln=0; iln<n; ++iln, pd+=3) {
          REGTYPE aopa = pd[0];
          REGTYPE aopb = pd[1];
          if (testdata[itst].dt & DT_SWREF) {
            switch (op & SW_CTRL_OPMASK) {
              case SW_OP_COR1b: 
                reference = swar_corr(aopa, aopb, REGBITS, 1, op & SW_CTRL_SIGNED, op & SW_CTRL_REDUCE, acc);
                break;
              case SW_OP_COR2b: 
                reference = swar_corr(aopa, aopb, REGBITS/2, 2, op & SW_CTRL_SIGNED, op & SW_CTRL_REDUCE, acc);
                break;
              case SW_OP_COR3b: 
                reference = swar_corr(aopa, aopb, REGBITS/3, 3, op & SW_CTRL_SIGNED, op & SW_CTRL_REDUCE, acc);
                break;
              case SW_OP_COR4b: 
                reference = swar_corr(aopa, aopb, REGBITS/4, 4, op & SW_CTRL_SIGNED, op & SW_CTRL_REDUCE, acc);
                break;

              case SW_OP_DEMC2bG:
                reference = swar_dem(aopa, aopb, REGBITS/2, 2, 0, 1);
                break;
              case SW_OP_DEMC2b:
                reference = swar_dem(aopa, aopb, REGBITS/2, 2, 1, 1);
                break;
              case SW_OP_DEMR2b:
                reference = swar_dem(aopa, aopb, REGBITS/2, 2, 1, 0);
                break;
              case SW_OP_DEMC3bG:
                reference = swar_dem(aopa, aopb, (REGBITS/3/2)*2, 3, 0, 1);
                break;
              case SW_OP_DEMC3b:
                reference = swar_dem(aopa, aopb, (REGBITS/3/2)*2, 3, 1, 1);
                break;
              case SW_OP_DEMR3b:
                reference = swar_dem(aopa, aopb, (REGBITS/3/2)*2, 3, 1, 0);
                break;
              case SW_OP_DEMC4bG:
                reference = swar_dem(aopa, aopb, REGBITS/4, 4, 0, 1);
                break;
              case SW_OP_DEMC4b:
                reference = swar_dem(aopa, aopb, REGBITS/4, 4, 1, 1);
                break;
              case SW_OP_DEMR4b:
                reference = swar_dem(aopa, aopb, REGBITS/4, 4, 1, 0);
                break;

              case SW_OP_SC1b:
                reference = swar_sincos(aopa, 1);
                break;
              case SW_OP_SC2b:
                reference = swar_sincos(aopa, 2);
                break;
              case SW_OP_SC3b:
                reference = swar_sincos(aopa, 3);
                break;
              case SW_OP_SC4b:
                reference = swar_sincos(aopa, 4);
                break;

              case SW_OP_ADD:
              case SW_OP_SUB:
              case SW_OP_MUL:
                reference = swar_alu(aopa, aopb, REGBITS/bits, bits, op & SW_CTRL_OPMASK, ((op & SW_CTRL_SIGNED)!=0), ((op & SW_CTRL_SATURATE)!=0), ((op & SW_CTRL_REDUCE)!=0), acc);
                break;

              default: reference = 0;
            }
          } else {
            switch (op & SW_CTRL_OPMASK) {
              case SW_OP_DEMC2bG:
              case SW_OP_DEMC2b:
              case SW_OP_DEMR2b:
              case SW_OP_DEMC3b:
              case SW_OP_DEMR3b:
              case SW_OP_DEMC4b:
              case SW_OP_DEMR4b:
                reference = expdem64((uint64_t)pd[2]);
                break;
              default:
                reference = (SREGTYPE)((STYPE_RAW)pd[2]);
            }
          }
          op_swar(aopa, aopb, result);
#ifdef PRINT_DETAILS
          printf("a " REGFMT " b " REGFMT " res " REGFMT "\n",aopa,aopb,result);
#endif
          if (result!=reference) {
            printf(" ERROR - EXP " REGFMT " ACT " REGFMT "\n", reference, result);
            failcnt++;
          }
        }
      } else {
        /* call the current swar operation with direct arguments */
        op_swar(opa, opb, result);
        /* TODO: sw reference */
#ifdef PRINT_DETAILS
        printf("a " REGFMT " b " REGFMT " res " REGFMT "\n", opa, opb, result);
#endif
        if (result!=reference) {
          printf(" ERROR - EXP " REGFMT " ACT " REGFMT "\n", reference, result);
          failcnt++;
        }
      }
    }
  }

  if (!failcnt)
    printf("END OF TEST\n");
  else
    printf("TEST COMPLETED WITH ERRORS\n");

  system_done();

  return 0;
}