LLVM framework for IP Core Extensions - RISC-V

This project contains script and patches for downloading and building modified LLVM framework. The LLVM framework is modified to support operations with added FP data types (packed half and packed single FP types). It also supports SWAR data types and operations.

LLVM version

The script builds LLVM version 13.0.0 (git commit 3186b18b998124a6b577f8274a10b7ee8b634c18).

Tools/libraries necessary for building LLVM

• git - is necessary for downloading and patching of the original LLVM (the GIT has to have configured user/email)

A user and an email can be configured in GIT with the following commands

$ git config --global user.name "Your Name"
$ git config --global user.email "youremail@yourdomain.com"

• patch for applying patches on the original LLVM
• make,gcc,binutils,libc - standard make and GCC compiler for compilation

Building

The compiler for RISC-V is built simply with command

./run_riscv.sh all

The script with option 'all' downloads, patches and builts the compiler for RISC-V in subdirectory 'install-riscv'.

Updating

If the repository is already cloned and built and the patches have been changed, the following steps can be performed to build LLVM with changed patches.

cd <repository>
git pull
./run_riscv packclean
./run_riscv patch
./run_riscv build

Using for RISC-V

The compiler is configured to use binutils tools with prefix 'riscv64-daiteq-elf-'. The compiler can used if the output directory 'install-riscv/bin' is added to environment variable PATH.

$ export PATH=<path-to-llvm>/install/bin:${PATH}

llvm/clang - added and affected options for RISC-V target

• added architecture extensions (for using with 'march' option)

  • zfh - enable half FP
  • x-fph - enable packed half FP
  • x-fps - enable packed single FP
  • x-swar - enable support for SWAR data types and operations

  Example: -march=rv64imafdzfh_x-fph_x-fps_x-swar

• msoft-float - set all FP operations in all precisions as soft-float

• msoft_fp_half - set all half FP operations as soft-float

• msoft_fp_single - set all single FP operations as soft-float

• msoft_fp_double - set all double FP operations as soft-float

• mhard_fp_half - set all half FP operations as hard-float

• mhard_fp_single - set all single FP operations as hard-float

• mhard_fp_double - set all double FP operations as hard-float

• msoft_fops_half - set selected half FP operations as soft-float (selected with a set of characters)

• msoft_fops_single - set selected single FP operations as soft-float (selected with a set of characters)

• msoft_fops_double - set selected double FP operations as soft-float (selected with a set of characters)

• mhard_fops_half - set selected half FP operations as soft-float (selected with a set of characters)

• mhard_fops_single - set selected single FP operations as soft-float (selected with a set of characters)

• mhard_fops_double - set selected double FP operations as soft-float (selected with a set of characters)

• menable_packedhalf - for RISC-V is not necessary - packed half FP ops are enabled with extension 'x-fph'

• menable_packedsingle - for RISC-V is not necessary - packed single FP ops are enabled with extension 'x-fps'

• daiteq_fpu_type - select FP precisions which have all operations as hard-float

• msoft-half - set which half FP operations are in soft-float with a numeric code

• msoft-single - set which single FP operations are in soft-float with a numeric code

• msoft-double - set which double FP operations are in soft-float with a numeric code

• daiteq_swar_enable - for RISC-V is not necessary - SWAR extension is enabled with architecture extension 'x-swar'

• daiteq_swar_type - select SWAR type for automatically added SWAR operations

• print_sf_uid - print unique identification string for architecture extensions and selection of soft-float operations