0001-daiteq-support-for-daiFPU-and-SWAR-extensions-of-RIS.txt

From c17c8cf6c1acc33f2445abf21992832736b1e176 Mon Sep 17 00:00:00 2001
From: Roman Bartosinski <roman@daiteq.com>
Date: Mon, 29 Aug 2022 10:29:24 +0200
Subject: [PATCH] daiteq support for daiFPU and SWAR extensions of RISC-V/Sparc
 CPU

Signed-off-by: Roman Bartosinski <roman@daiteq.com>
---
 clang/include/clang/AST/ASTContext.h          |    6 +
 clang/include/clang/AST/DeclBase.h            |   16 +
 clang/include/clang/AST/RecursiveASTVisitor.h |    8 +
 clang/include/clang/AST/Type.h                |   63 +
 clang/include/clang/AST/TypeLoc.h             |    5 +
 clang/include/clang/AST/TypeProperties.td     |   16 +
 clang/include/clang/ASTMatchers/ASTMatchers.h |    8 +
 clang/include/clang/Basic/Attr.td             |    7 +
 clang/include/clang/Basic/Builtins.def        |   20 +
 clang/include/clang/Basic/CodeGenOptions.def  |   10 +
 clang/include/clang/Basic/DiagnosticGroups.td |    2 +
 .../clang/Basic/DiagnosticSemaKinds.td        |   22 +
 clang/include/clang/Basic/LangOptions.def     |    8 +
 clang/include/clang/Basic/LangOptions.h       |    7 +
 clang/include/clang/Basic/TargetInfo.h        |   38 +
 clang/include/clang/Basic/TokenKinds.def      |    1 +
 clang/include/clang/Basic/TypeNodes.td        |    1 +
 clang/include/clang/Driver/Options.td         |   60 +
 .../include/clang/Frontend/FrontendOptions.h  |    3 +
 clang/include/clang/Parse/Parser.h            |    5 +
 clang/include/clang/Sema/Initialization.h     |    5 +-
 clang/include/clang/Sema/Sema.h               |   32 +
 .../clang/Serialization/TypeBitCodes.def      |    1 +
 clang/lib/AST/ASTContext.cpp                  |   57 +
 clang/lib/AST/ASTStructuralEquivalence.cpp    |   12 +
 clang/lib/AST/Expr.cpp                        |    9 +
 clang/lib/AST/ExprConstant.cpp                |  252 +++-
 clang/lib/AST/ItaniumMangle.cpp               |   17 +
 clang/lib/AST/MicrosoftMangle.cpp             |    8 +
 clang/lib/AST/Type.cpp                        |   18 +
 clang/lib/AST/TypePrinter.cpp                 |   14 +
 clang/lib/Basic/TargetInfo.cpp                |   38 +
 clang/lib/Basic/Targets/RISCV.cpp             |   44 +-
 clang/lib/Basic/Targets/RISCV.h               |    3 +
 clang/lib/Basic/Targets/Sparc.cpp             |   19 +
 clang/lib/Basic/Targets/Sparc.h               |   11 +-
 clang/lib/CodeGen/CGBuiltin.cpp               |  170 +++
 clang/lib/CodeGen/CGCall.cpp                  |   12 +
 clang/lib/CodeGen/CGDebugInfo.cpp             |   23 +
 clang/lib/CodeGen/CGDebugInfo.h               |    3 +
 clang/lib/CodeGen/CGExpr.cpp                  |    8 +
 clang/lib/CodeGen/CGExprScalar.cpp            |   54 +
 clang/lib/CodeGen/CGValue.h                   |   12 +
 clang/lib/CodeGen/CodeGenFunction.cpp         |    4 +
 clang/lib/CodeGen/CodeGenTypes.cpp            |   17 +
 clang/lib/CodeGen/ItaniumCXXABI.cpp           |    6 +
 clang/lib/Driver/Driver.cpp                   |    6 +-
 clang/lib/Driver/ToolChains/Arch/RISCV.cpp    |  291 +++-
 clang/lib/Driver/ToolChains/Arch/Sparc.cpp    |    3 +
 clang/lib/Driver/ToolChains/Clang.cpp         |  509 +++++++
 clang/lib/Driver/ToolChains/Clang.h           |    8 +
 clang/lib/Driver/Types.cpp                    |    3 +-
 clang/lib/Format/FormatToken.h                |    2 +
 clang/lib/Format/TokenAnnotator.cpp           |    4 +-
 clang/lib/Frontend/CompilerInvocation.cpp     |  380 +++++
 .../Frontend/Rewrite/RewriteModernObjC.cpp    |    2 -
 clang/lib/Frontend/Rewrite/RewriteObjC.cpp    |    2 -
 clang/lib/Parse/ParseExpr.cpp                 |   22 +-
 clang/lib/Parse/ParseObjc.cpp                 |    1 +
 clang/lib/Parse/ParsePragma.cpp               |  129 ++
 clang/lib/Sema/DeclSpec.cpp                   |    2 +-
 clang/lib/Sema/SemaAttr.cpp                   |   39 +
 clang/lib/Sema/SemaCast.cpp                   |    9 +-
 clang/lib/Sema/SemaChecking.cpp               |   74 +
 clang/lib/Sema/SemaExpr.cpp                   |  303 +++-
 clang/lib/Sema/SemaInit.cpp                   |   66 +
 clang/lib/Sema/SemaLookup.cpp                 |    1 +
 clang/lib/Sema/SemaStmt.cpp                   |  378 ++++-
 clang/lib/Sema/SemaTemplate.cpp               |    4 +
 clang/lib/Sema/SemaTemplateDeduction.cpp      |    7 +
 clang/lib/Sema/SemaType.cpp                   |  104 ++
 clang/lib/Sema/TreeTransform.h                |   39 +
 clang/lib/Serialization/ASTReader.cpp         |    4 +
 clang/lib/Serialization/ASTWriter.cpp         |    7 +
 clang/tools/libclang/CIndex.cpp               |    1 +
 llvm/include/llvm-c/Core.h                    |   19 +-
 llvm/include/llvm/ADT/Triple.h                |    3 +-
 llvm/include/llvm/AsmParser/LLToken.h         |    2 +
 llvm/include/llvm/CodeGen/RuntimeLibcalls.h   |    1 +
 llvm/include/llvm/CodeGen/SelectionDAGNodes.h |    5 +-
 llvm/include/llvm/CodeGen/TargetLowering.h    |    8 +
 llvm/include/llvm/CodeGen/ValueTypes.h        |   46 +-
 llvm/include/llvm/CodeGen/ValueTypes.td       |   30 +-
 llvm/include/llvm/IR/DIBuilder.h              |    8 +
 llvm/include/llvm/IR/DataLayout.h             |    5 +
 llvm/include/llvm/IR/DebugInfoFlags.def       |    3 +-
 llvm/include/llvm/IR/DebugInfoMetadata.h      |    1 +
 llvm/include/llvm/IR/DerivedTypes.h           |  110 +-
 .../llvm/IR/GetElementPtrTypeIterator.h       |    2 +
 llvm/include/llvm/IR/InstrTypes.h             |    7 +
 llvm/include/llvm/IR/Instructions.h           |    8 +-
 llvm/include/llvm/IR/Intrinsics.td            |   17 +
 llvm/include/llvm/IR/RuntimeLibcalls.def      |   66 +
 llvm/include/llvm/IR/Type.h                   |    7 +-
 llvm/include/llvm/Support/MachineValueType.h  |  157 +-
 llvm/include/llvm/TableGen/Record.h           |    2 +
 llvm/include/llvm/Target/Target.td            |    3 +
 llvm/include/llvm/Target/TargetOptions.h      |   51 +
 llvm/lib/Analysis/ValueTracking.cpp           |   14 +-
 llvm/lib/AsmParser/LLLexer.cpp                |    2 +
 llvm/lib/AsmParser/LLParser.cpp               |   57 +-
 llvm/lib/Bitcode/Reader/BitcodeReader.cpp     |   55 +-
 llvm/lib/Bitcode/Writer/BitcodeWriter.cpp     |   16 +-
 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp |   96 +-
 .../SelectionDAG/LegalizeFloatTypes.cpp       |  115 +-
 .../SelectionDAG/LegalizeIntegerTypes.cpp     |   11 +-
 llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h |    1 +
 .../SelectionDAG/LegalizeVectorOps.cpp        |    2 +-
 .../lib/CodeGen/SelectionDAG/SelectionDAG.cpp |  122 +-
 .../SelectionDAG/SelectionDAGBuilder.cpp      |   75 +-
 .../CodeGen/SelectionDAG/TargetLowering.cpp   |   42 +-
 llvm/lib/CodeGen/TargetLoweringBase.cpp       |   17 +-
 llvm/lib/CodeGen/ValueTypes.cpp               |  100 ++
 llvm/lib/ExecutionEngine/ExecutionEngine.cpp  |   12 +
 .../ExecutionEngine/Interpreter/Execution.cpp |   10 +
 llvm/lib/IR/AsmWriter.cpp                     |   22 +-
 llvm/lib/IR/ConstantFold.cpp                  |   12 +-
 llvm/lib/IR/Constants.cpp                     |   41 +-
 llvm/lib/IR/Core.cpp                          |    2 +
 llvm/lib/IR/DIBuilder.cpp                     |   15 +
 llvm/lib/IR/DataLayout.cpp                    |    1 +
 llvm/lib/IR/Instructions.cpp                  |  124 +-
 llvm/lib/IR/Type.cpp                          |   33 +
 llvm/lib/IR/Verifier.cpp                      |   61 +-
 llvm/lib/Linker/IRMover.cpp                   |    1 +
 llvm/lib/Support/Triple.cpp                   |    2 +
 .../Target/RISCV/AsmParser/RISCVAsmParser.cpp |   43 +-
 .../RISCV/Disassembler/RISCVDisassembler.cpp  |   39 +
 .../MCTargetDesc/RISCVTargetStreamer.cpp      |    9 +-
 llvm/lib/Target/RISCV/RISCV.td                |  177 ++-
 llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp     |   13 +-
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp   |  702 ++++++++-
 llvm/lib/Target/RISCV/RISCVISelLowering.h     |   36 +
 llvm/lib/Target/RISCV/RISCVInstrInfo.cpp      |   20 +-
 llvm/lib/Target/RISCV/RISCVInstrInfo.td       |   41 +
 llvm/lib/Target/RISCV/RISCVInstrInfoD.td      |   22 +-
 llvm/lib/Target/RISCV/RISCVInstrInfoF.td      |   76 +-
 llvm/lib/Target/RISCV/RISCVInstrInfoXfph.td   |  535 +++++++
 llvm/lib/Target/RISCV/RISCVInstrInfoXfps.td   |  448 ++++++
 llvm/lib/Target/RISCV/RISCVInstrInfoXswar.td  |  355 +++++
 llvm/lib/Target/RISCV/RISCVRegisterInfo.td    |   72 +
 llvm/lib/Target/RISCV/RISCVSchedDaiteq.td     |  304 ++++
 llvm/lib/Target/RISCV/RISCVSchedRocket.td     |    1 +
 llvm/lib/Target/RISCV/RISCVSchedSiFive7.td    |    1 +
 llvm/lib/Target/RISCV/RISCVSchedule.td        |   57 +-
 llvm/lib/Target/RISCV/RISCVSubtarget.cpp      |    7 +
 llvm/lib/Target/RISCV/RISCVSubtarget.h        |   17 +
 llvm/lib/Target/RISCV/RISCVSystemOperands.td  |    9 +
 llvm/lib/Target/RISCV/RISCVTargetMachine.cpp  |   88 ++
 llvm/lib/Target/Sparc/DelaySlotFiller.cpp     |    4 +-
 .../Sparc/Disassembler/SparcDisassembler.cpp  |  113 ++
 llvm/lib/Target/Sparc/LeonFeatures.td         |    7 +
 llvm/lib/Target/Sparc/LeonPasses.cpp          |   49 +
 llvm/lib/Target/Sparc/LeonPasses.h            |   13 +
 llvm/lib/Target/Sparc/Sparc.td                |  101 +-
 llvm/lib/Target/Sparc/SparcCallingConv.td     |   10 +-
 llvm/lib/Target/Sparc/SparcISelLowering.cpp   | 1304 ++++++++++++++++-
 llvm/lib/Target/Sparc/SparcISelLowering.h     |   47 +-
 llvm/lib/Target/Sparc/SparcInstrInfo.cpp      |   81 +-
 llvm/lib/Target/Sparc/SparcInstrInfo.td       |  516 ++++++-
 llvm/lib/Target/Sparc/SparcRegisterInfo.td    |   11 +
 llvm/lib/Target/Sparc/SparcSchedule.td        |   35 +
 llvm/lib/Target/Sparc/SparcSubtarget.cpp      |   71 +
 llvm/lib/Target/Sparc/SparcSubtarget.h        |   40 +-
 llvm/lib/Target/Sparc/SparcTargetMachine.cpp  |   94 ++
 llvm/lib/Transforms/IPO/GlobalOpt.cpp         |    1 +
 .../InstCombine/InstCombineVectorOps.cpp      |    2 +
 llvm/lib/Transforms/Scalar/BDCE.cpp           |    1 +
 llvm/lib/Transforms/Scalar/SROA.cpp           |    1 +
 .../Transforms/Utils/FunctionComparator.cpp   |   11 +
 llvm/utils/TableGen/AsmMatcherEmitter.cpp     |   29 +
 llvm/utils/TableGen/CodeGenTarget.cpp         |   17 +
 172 files changed, 10344 insertions(+), 463 deletions(-)
 create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoXfph.td
 create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoXfps.td
 create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoXswar.td
 create mode 100644 llvm/lib/Target/RISCV/RISCVSchedDaiteq.td

diff --git a/clang/include/clang/AST/ASTContext.h b/clang/include/clang/AST/ASTContext.h
index 34299581d89d..e0e844ead31c 100644
--- a/clang/include/clang/AST/ASTContext.h
+++ b/clang/include/clang/AST/ASTContext.h
@@ -209,6 +209,7 @@ class ASTContext : public RefCountedBase<ASTContext> {
       DependentAddressSpaceTypes;
   mutable llvm::FoldingSet<VectorType> VectorTypes;
   mutable llvm::FoldingSet<DependentVectorType> DependentVectorTypes;
+  mutable llvm::FoldingSet<SubwordType> SubwordTypes;
   mutable llvm::FoldingSet<ConstantMatrixType> MatrixTypes;
   mutable llvm::FoldingSet<DependentSizedMatrixType> DependentSizedMatrixTypes;
   mutable llvm::FoldingSet<FunctionNoProtoType> FunctionNoProtoTypes;
@@ -1476,6 +1477,11 @@ public:
                                         Expr *AddrSpaceExpr,
                                         SourceLocation AttrLoc) const;
 
+  /// Return the unique reference to sub-word type of the specified type and bit 
+  /// width
+  QualType getSubwordType(QualType T, unsigned BitWidth, 
+                          unsigned Packing) const;
+
   /// Return a K&R style C function type like 'int()'.
   QualType getFunctionNoProtoType(QualType ResultTy,
                                   const FunctionType::ExtInfo &Info) const;
diff --git a/clang/include/clang/AST/DeclBase.h b/clang/include/clang/AST/DeclBase.h
index 482d2889a25a..0a99aba6aff4 100644
--- a/clang/include/clang/AST/DeclBase.h
+++ b/clang/include/clang/AST/DeclBase.h
@@ -1850,6 +1850,22 @@ protected:
 public:
   ~DeclContext();
 
+  // flags for SWAR operations lower 8 bits is the direct mask for swarctrl (asr22) cmd, upper 8 bits are bitmap
+  enum SwarFlags {
+    reduceFlg    = SWAR_CTRL_REDUCE,
+    saturateFlg  = SWAR_CTRL_SATURATE,
+    normalizeFlg = SWAR_CTRL_NORMALIZE,
+    manualFlg    = (1<<16), /* internal information flag which is not used in swar control word */
+    directMask   = 0xffff,
+  };
+  enum SwarIndices {
+    reduceIdx    = 0,
+    saturateIdx  = 1,
+    normalizeIdx = 2,
+    manualIdx    = 3,
+  };
+  SourceLocation swarPragmaLoc[5]; // 0=reduce, 1=saturate, 2=normalize, 3=manual
+
   Decl::Kind getDeclKind() const {
     return static_cast<Decl::Kind>(DeclContextBits.DeclKind);
   }
diff --git a/clang/include/clang/AST/RecursiveASTVisitor.h b/clang/include/clang/AST/RecursiveASTVisitor.h
index 9bfa5b9c2326..24b02b6b8ce3 100644
--- a/clang/include/clang/AST/RecursiveASTVisitor.h
+++ b/clang/include/clang/AST/RecursiveASTVisitor.h
@@ -963,6 +963,10 @@ DEF_TRAVERSE_TYPE(DependentSizedMatrixType, {
   TRY_TO(TraverseType(T->getElementType()));
 })
 
+/* the travesing type can be or element (should be) or basic type 
+   (the native type for the architecture) */
+DEF_TRAVERSE_TYPE(SubwordType, { TRY_TO(TraverseType(T->getBasicType())); })
+
 DEF_TRAVERSE_TYPE(FunctionNoProtoType,
                   { TRY_TO(TraverseType(T->getReturnType())); })
 
@@ -1227,6 +1231,10 @@ DEF_TRAVERSE_TYPELOC(DependentSizedMatrixType, {
   TRY_TO(TraverseType(TL.getTypePtr()->getElementType()));
 })
 
+DEF_TRAVERSE_TYPELOC(SubwordType, {
+  TRY_TO(TraverseType(TL.getTypePtr()->getBasicType()));
+})
+
 DEF_TRAVERSE_TYPELOC(FunctionNoProtoType,
                      { TRY_TO(TraverseTypeLoc(TL.getReturnLoc())); })
 
diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h
index 9f46d5337897..4a0f33043d79 100644
--- a/clang/include/clang/AST/Type.h
+++ b/clang/include/clang/AST/Type.h
@@ -2039,6 +2039,7 @@ public:
   bool isComplexIntegerType() const;            // GCC _Complex integer type.
   bool isVectorType() const;                    // GCC vector type.
   bool isExtVectorType() const;                 // Extended vector type.
+  bool isSubwordType() const;                   // SWAR sub-word type.
   bool isMatrixType() const;                    // Matrix type.
   bool isConstantMatrixType() const;            // Constant matrix type.
   bool isDependentAddressSpaceType() const;     // value-dependent address space qualifier
@@ -3543,6 +3544,64 @@ public:
                       QualType ElementType, Expr *RowExpr, Expr *ColumnExpr);
 };
 
+
+/* -------------------------------------------------------------------------- */
+// subword control word
+#define SWAR_CTRL_SIGNED        (1<<8)
+#define SWAR_CTRL_REDUCE        (1<<9)
+#define SWAR_CTRL_SATURATE      (1<<10)
+#define SWAR_CTRL_NORMALIZE     (1<<11)
+#define SWAR_CTRL_AUDIO         (1<<12)
+#define SWAR_CTRL_VIDEO         (1<<13)
+#define SWAR_CTRL_ALU           (1<<14)
+#define SWAR_CTRL_OP_MASK       (0xFF)
+#define SWAR_CTRL_OP_ADD        (0)
+#define SWAR_CTRL_OP_SUB        (0x08)
+#define SWAR_CTRL_OP_MUL        (0x0C)
+
+/// SubwordType - represents a SWAR sub-word type. This type is created using
+/// __atribute__(__subword__(n,m)) where "n" specifies type width in bits and
+/// "m" specifies number of elements in the array
+class SubwordType : public Type, public llvm::FoldingSetNode {
+protected:
+  friend class ASTContext;
+  /// The basic type of the SWAR sub-word type.
+  QualType BasicType;     /* currently only uint32 for Sparc target, can be uint32 or uint64 for RISCV */
+  unsigned BitWidth;      /* bit width of each element (1/2/3/4/8/16) */
+  unsigned Packing;       /* Number of elements in each BasicType (if =0, use full packing (size(basetype)/bitwidth) */
+
+public:
+  SubwordType(TypeClass tc, QualType canonType, QualType basicType, unsigned bitWidth);
+  SubwordType(TypeClass tc, QualType canonType, QualType basicType, unsigned bitWidth, unsigned packing);
+
+  /// Return basic type.
+  QualType getBasicType() const { return BasicType; } /* packing word (currently we use only u32) */
+  /// Return size of element in bits.
+  unsigned getBitWidth() const { return BitWidth; }   /* item size (1/2/3/4/8/16 bits) */
+  /// Return Number of elements in basic type.
+  unsigned getPacking() const { return Packing; }   /* packwordwidth (32) / bitwidth (1/2/3/4/8/16) = 32/16/10/8/4/2 */
+
+  bool isSugared() const { return false; }
+  QualType desugar() const { return QualType(this, 0); }
+
+  void Profile(llvm::FoldingSetNodeID &ID) {
+    Profile(ID, getBasicType(), getBitWidth(), getPacking(), getTypeClass());
+  }
+
+  static void Profile(llvm::FoldingSetNodeID &ID, QualType BasicType,
+                      unsigned BitWidth, unsigned Packing, TypeClass TypeClass) {
+    ID.AddPointer(BasicType.getAsOpaquePtr());
+    ID.AddInteger(BitWidth);
+    ID.AddInteger(Packing);
+    ID.AddInteger(TypeClass);
+  }
+
+  static bool classof(const Type *T) {
+    return T->getTypeClass() == Subword;
+  }
+};
+
+
 /// FunctionType - C99 6.7.5.3 - Function Declarators.  This is the common base
 /// class of FunctionNoProtoType and FunctionProtoType.
 class FunctionType : public Type {
@@ -6790,6 +6849,10 @@ inline bool Type::isConstantMatrixType() const {
   return isa<ConstantMatrixType>(CanonicalType);
 }
 
+inline bool Type::isSubwordType() const {
+  return isa<SubwordType>(CanonicalType);
+}
+
 inline bool Type::isDependentAddressSpaceType() const {
   return isa<DependentAddressSpaceType>(CanonicalType);
 }
diff --git a/clang/include/clang/AST/TypeLoc.h b/clang/include/clang/AST/TypeLoc.h
index 65e95d52c303..0bde5d8f3023 100644
--- a/clang/include/clang/AST/TypeLoc.h
+++ b/clang/include/clang/AST/TypeLoc.h
@@ -1801,6 +1801,11 @@ class ExtVectorTypeLoc
     : public InheritingConcreteTypeLoc<VectorTypeLoc, ExtVectorTypeLoc,
                                        ExtVectorType> {};
 
+class SubwordTypeLoc : public InheritingConcreteTypeLoc<TypeSpecTypeLoc,
+                                                        SubwordTypeLoc,
+                                                        SubwordType> {
+};
+
 // FIXME: attribute locations.
 // For some reason, this isn't a subtype of VectorType.
 class DependentSizedExtVectorTypeLoc
diff --git a/clang/include/clang/AST/TypeProperties.td b/clang/include/clang/AST/TypeProperties.td
index 438d5af5a2e2..0591ae8a0a8d 100644
--- a/clang/include/clang/AST/TypeProperties.td
+++ b/clang/include/clang/AST/TypeProperties.td
@@ -259,6 +259,22 @@ let Class = DependentSizedMatrixType in {
   }]>;
 }
 
+let Class = SubwordType in {
+  def : Property<"basicType", QualType> {
+    let Read = [{ node->getBasicType() }];
+  }
+  def : Property<"bitWidth", UInt32> {
+    let Read = [{ node->getBitWidth() }];
+  }
+  def : Property<"packing", UInt32> {
+    let Read = [{ node->getPacking() }];
+  }
+
+  def : Creator<[{
+    return ctx.getSubwordType(basicType, bitWidth, packing);
+  }]>;
+}
+
 let Class = FunctionType in {
   def : Property<"returnType", QualType> {
     let Read = [{ node->getReturnType() }];
diff --git a/clang/include/clang/ASTMatchers/ASTMatchers.h b/clang/include/clang/ASTMatchers/ASTMatchers.h
index 8e3ee6cb9e7e..e4365c81d969 100644
--- a/clang/include/clang/ASTMatchers/ASTMatchers.h
+++ b/clang/include/clang/ASTMatchers/ASTMatchers.h
@@ -2969,6 +2969,14 @@ inline internal::BindableMatcher<Stmt> sizeOfExpr(
       allOf(ofKind(UETT_SizeOf), InnerMatcher)));
 }
 
+/// Same as unaryExprOrTypeTraitExpr, but only matching
+/// sizeofswar.
+inline internal::Matcher<Stmt> sizeOfSwarExpr(
+    const internal::Matcher<UnaryExprOrTypeTraitExpr> &InnerMatcher) {
+  return stmt(unaryExprOrTypeTraitExpr(
+      allOf(ofKind(UETT_SizeOfSwar), InnerMatcher)));
+}
+
 /// Matches NamedDecl nodes that have the specified name.
 ///
 /// Supports specifying enclosing namespaces or classes by prefixing the name
diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td
index 12d09181a2ea..6c4e9fc76aa1 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -2769,6 +2769,13 @@ def Uuid : InheritableAttr {
   let Documentation = [Undocumented];
 }
 
+def Subword : TypeAttr {
+  let Spellings = [GCC<"subword">];
+  let Args = [ExprArgument<"BitWidth">, ExprArgument<"Packing", 1>];
+  let Documentation = [Undocumented];
+  let ASTNode = 0;
+}
+
 def VectorSize : TypeAttr {
   let Spellings = [GCC<"vector_size">];
   let Args = [ExprArgument<"NumBytes">];
diff --git a/clang/include/clang/Basic/Builtins.def b/clang/include/clang/Basic/Builtins.def
index 0e3898537bcf..461b46ee7926 100644
--- a/clang/include/clang/Basic/Builtins.def
+++ b/clang/include/clang/Basic/Builtins.def
@@ -47,6 +47,7 @@
 //  K -> ucontext_t
 //  p -> pid_t
 //  . -> "...".  This may only occur at the end of the function list.
+//  # -> type of the return value is the same as a type of the first argument
 //
 // Types may be prefixed with the following modifiers:
 //  L   -> long (e.g. Li for 'long int', Ld for 'long double')
@@ -1661,6 +1662,25 @@ BUILTIN(__builtin_ms_va_copy, "vc*&c*&", "n")
 // Arithmetic Fence: to prevent FP reordering and reassociation optimizations
 LANGBUILTIN(__arithmetic_fence, "v.", "t", ALL_LANGUAGES)
 
+
+// daiteq extensions
+BUILTIN(__builtin_fabsh , "hh"  , "ncF")
+BUILTIN(__builtin_sqrth , "hh"  , "Fne")
+LIBBUILTIN(fabsh, "hh", "fnc", "math.h", C_LANG )
+LIBBUILTIN(sqrth, "hh", "fne", "math.h", C_LANG )
+
+BUILTIN(__builtin_sqrtpf , "V2fV2f"  , "Fne")
+LIBBUILTIN(sqrtpf, "V2fV2f", "fne", "math.h", C_LANG )
+
+BUILTIN(__builtin_swarctrl, "v.", "tT")                /* swar set control ASR register - void swarctrl(immconst); */
+
+BUILTIN(__builtin_swaraccum, "ULi.", "tT")               /* swar get status/accumulator ASR register - uint32_t swarstat(immconst); uint32_t swarstat("uint32_t") */
+
+BUILTIN(__builtin_swar , "#"  , "tT")                 /* call universal swar function (swarctrl must be set manually - "uint32_t" swar("uint32_t","uint32_t")  */
+
+BUILTIN(__builtin_swarcc , "Ui."  , "tT")               /* call universal swar function with conditions (swarctrl must be set manually - "uint32_t" swarcc("uint32_t","uint32_t") */
+
+
 #undef BUILTIN
 #undef LIBBUILTIN
 #undef LANGBUILTIN
diff --git a/clang/include/clang/Basic/CodeGenOptions.def b/clang/include/clang/Basic/CodeGenOptions.def
index e3202cf88756..00345180a99f 100644
--- a/clang/include/clang/Basic/CodeGenOptions.def
+++ b/clang/include/clang/Basic/CodeGenOptions.def
@@ -262,6 +262,16 @@ CODEGENOPT(SanitizeCoverageStackDepth, 1, 0) ///< Enable max stack depth tracing
 CODEGENOPT(SanitizeStats     , 1, 0) ///< Collect statistics for sanitizers.
 CODEGENOPT(SimplifyLibCalls  , 1, 1) ///< Set when -fbuiltin is enabled.
 CODEGENOPT(SoftFloat         , 1, 0) ///< -soft-float.
+
+//CODEGENOPT(daiteqFPUType  , 32, 0) ///< -daiteq-fpu-enable.
+CODEGENOPT(EnabledSWARdaiteq , 1, 0) ///< -daiteq-swar-enable.
+CODEGENOPT(UseSWARUnit, 32, 0) ///< -daiteq-swar-force-config.
+CODEGENOPT(SoftFopsHalf      , 32, -1) /// < -soft-fp-half / -soft-fops-half -> soft-half
+CODEGENOPT(SoftFopsSingle    , 32, -1) /// < -soft-fp-single / -soft-fops-single -> soft-single
+CODEGENOPT(SoftFopsDouble    , 32, -1) /// < -soft-fp-double / -soft-fops-double -> soft-double
+CODEGENOPT(EnabledPackedHalf     , 1, 0) ///< -enable-packedsignle.
+CODEGENOPT(EnabledPackedSingle   , 1, 0) ///< -enable-packedhalf.
+
 CODEGENOPT(SpeculativeLoadHardening, 1, 0) ///< Enable speculative load hardening.
 CODEGENOPT(FineGrainedBitfieldAccesses, 1, 0) ///< Enable fine-grained bitfield accesses.
 CODEGENOPT(StrictEnums       , 1, 0) ///< Optimize based on strict enum definition.
diff --git a/clang/include/clang/Basic/DiagnosticGroups.td b/clang/include/clang/Basic/DiagnosticGroups.td
index 4b4928a7a00e..6ffbda0b2c46 100644
--- a/clang/include/clang/Basic/DiagnosticGroups.td
+++ b/clang/include/clang/Basic/DiagnosticGroups.td
@@ -1303,3 +1303,5 @@ def WebAssemblyExceptionSpec : DiagGroup<"wasm-exception-spec">;
 def RTTI : DiagGroup<"rtti">;
 
 def OpenCLCoreFeaturesDiagGroup : DiagGroup<"pedantic-core-features">;
+
+def SubwordExtension : DiagGroup<"daiteq-subword-extension">;
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index c57b8eca7deb..08f3f809cb3e 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -11350,4 +11350,26 @@ def err_riscv_builtin_requires_extension : Error<
   "builtin requires '%0' extension support to be enabled">;
 def err_riscv_builtin_invalid_lmul : Error<
   "LMUL argument must be in the range [0,3] or [5,7]">;
+
+// daiteq extension
+def err_swar_pragma_outside_declctx : Error<
+  "'#pragma swar <attribute>' is outside of allowed blocks">;
+def err_attribute_subword_disabled : Error<"subword type is not allowed "
+  "it can be enabled with the correct option">;
+def err_attribute_subword_oversized : Error<"too many elements %0 with %1b "
+  "size, basic type has only %2 bits">;
+def err_typecheck_subword_length_not_equal : Error<
+   "subword operands do not have the same number of elements (%0 and %1)">;
+def warn_subword_crossover : Warning<
+  "Too many subword operations in a loop - crossover in using">,
+  InGroup<SubwordExtension>;
+def err_invalid_conversion_between_subwords : Error<
+  "invalid conversion between subword type%diff{ $ and $|}0,1 of different "
+  "size">;
+def err_invalid_conversion_between_subword_and_integer : Error<
+  "invalid conversion between subword type %0 and integer type %1 "
+  "of different size">;
+def err_invalid_conversion_between_subword_and_scalar : Error<
+  "invalid conversion between subword type %0 and scalar type %1">;
+
 } // end of sema component.
diff --git a/clang/include/clang/Basic/LangOptions.def b/clang/include/clang/Basic/LangOptions.def
index 74deba6ef7fb..cc84b4d70434 100644
--- a/clang/include/clang/Basic/LangOptions.def
+++ b/clang/include/clang/Basic/LangOptions.def
@@ -404,6 +404,14 @@ LANGOPT(PaddingOnUnsignedFixedPoint, 1, 0,
 
 LANGOPT(RegisterStaticDestructors, 1, 1, "Register C++ static destructors")
 
+LANGOPT(EnabledSWARdaiteq,    1, 0, "daiteq SWAR extension")
+LANGOPT(UseSWARUnit,          3, SWAR_Unit_ByType, "Use specific SWAR type")
+LANGOPT(SoftFopsHalf,         32, -1, "Selection of soft-float half FP operations") /// < -soft-fp-half / -soft-fops-half -> soft-half
+LANGOPT(SoftFopsSingle,       32, -1, "Selection of soft-float single FP operations") /// < -soft-fp-single / -soft-fops-single -> soft-single
+LANGOPT(SoftFopsDouble,       32, -1, "Selection of soft-float double FP operations") /// < -soft-fp-double / -soft-fops-double -> soft-double
+LANGOPT(EnabledPackedHalf,    1, 0, "Enable packed half FP") ///< -enable-packedsignle.
+LANGOPT(EnabledPackedSingle,  1, 0, "Enable packed single FP") ///< -enable-packedhalf.
+
 LANGOPT(MatrixTypes, 1, 0, "Enable or disable the builtin matrix type")
 
 COMPATIBLE_VALUE_LANGOPT(MaxTokens, 32, 0, "Max number of tokens per TU or 0")
diff --git a/clang/include/clang/Basic/LangOptions.h b/clang/include/clang/Basic/LangOptions.h
index b60b94a1ba08..a5e83c8aa11e 100644
--- a/clang/include/clang/Basic/LangOptions.h
+++ b/clang/include/clang/Basic/LangOptions.h
@@ -286,6 +286,13 @@ public:
     ExtendTo64
   };
 
+  enum SWARUnit {
+    SWAR_Unit_ByType,
+    SWAR_Unit_Audio,
+    SWAR_Unit_Video,
+    SWAR_Unit_ALU,
+  };
+
 public:
   /// The used language standard.
   LangStandard::Kind LangStd;
diff --git a/clang/include/clang/Basic/TargetInfo.h b/clang/include/clang/Basic/TargetInfo.h
index 4f0cbf986b31..0745f31fb0f5 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1580,6 +1580,44 @@ protected:
   // Assert the values for the fractional and integral bits for each fixed point
   // type follow the restrictions given in clause 6.2.6.3 of N1169.
   void CheckFixedPointBits() const;
+
+protected:
+  bool EnabledSWARdaiteq;
+  //unsigned daiteqFPUType; // 0=none,1=dpsp,2=sphp,3=dp,4=sp,5=hp,6=php,7=psp
+  unsigned SoftFopsHalf;
+  unsigned SoftFopsSingle;
+  unsigned SoftFopsDouble;
+  bool EnabledPackedHalf;
+  bool EnabledPackedSingle;
+
+  static const struct SoftFopsTableStruct {
+    unsigned mask;
+    char     flag;
+  } SoftFopsTable[];
+
+  std::string getFopsDesc(unsigned mask);
+  unsigned getFopsMask(const std::string &desc);
+
+};
+
+enum SoftFopsMasks {
+  FPOP_ADD  = 0x00000001, // 'a'
+  FPOP_SUB  = 0x00000002, // 's'
+  FPOP_MUL  = 0x00000004, // 'm'
+  FPOP_DIV  = 0x00000008, // 'd'
+  FPOP_MULEX= 0x00000010, // 'M' expanding multiply (from the specific precision to higher precision)
+  FPOP_SQRT = 0x00000020, // 'S'
+  FPOP_CMP  = 0x00000040, // 'c'
+  FPOP_CI2F = 0x00000080, // 'f' - convert integer into float
+  FPOP_CF2I = 0x00000100, // 'i' - convert float into integer
+  FPOP_CFUP = 0x00000200, // 'h' - convert float into float with higher precision (H->S,S->D,D->Q)
+  FPOP_CFDN = 0x00000400, // 'l' - convert float into float with lower precision (D->S,S->H)
+  FPOP_ABS  = 0x00000800, // 'A'
+  FPOP_PACK = 0x00001000, // 'p'
+  FPOP_MOV  = 0x00002000, // 'C'
+  FPOP_NEG  = 0x00004000, // 'n'
+
+  FPOP_FULL_MASK = 0x00006FFF, // all known and used masks
 };
 
 }  // end namespace clang
diff --git a/clang/include/clang/Basic/TokenKinds.def b/clang/include/clang/Basic/TokenKinds.def
index 48a664e3494e..a9d1eefd26f5 100644
--- a/clang/include/clang/Basic/TokenKinds.def
+++ b/clang/include/clang/Basic/TokenKinds.def
@@ -307,6 +307,7 @@ KEYWORD(return                      , KEYALL)
 KEYWORD(short                       , KEYALL)
 KEYWORD(signed                      , KEYALL)
 UNARY_EXPR_OR_TYPE_TRAIT(sizeof, SizeOf, KEYALL)
+UNARY_EXPR_OR_TYPE_TRAIT(sizeofswar, SizeOfSwar, KEYALL)
 KEYWORD(static                      , KEYALL)
 KEYWORD(struct                      , KEYALL)
 KEYWORD(switch                      , KEYALL)
diff --git a/clang/include/clang/Basic/TypeNodes.td b/clang/include/clang/Basic/TypeNodes.td
index 011394c3ef45..0d9b745423f5 100644
--- a/clang/include/clang/Basic/TypeNodes.td
+++ b/clang/include/clang/Basic/TypeNodes.td
@@ -69,6 +69,7 @@ def DependentAddressSpaceType : TypeNode<Type>, AlwaysDependent;
 def VectorType : TypeNode<Type>;
 def DependentVectorType : TypeNode<Type>, AlwaysDependent;
 def ExtVectorType : TypeNode<VectorType>;
+def SubwordType : TypeNode<Type>;
 def MatrixType : TypeNode<Type, 1>;
 def ConstantMatrixType : TypeNode<MatrixType>;
 def DependentSizedMatrixType : TypeNode<MatrixType>, AlwaysDependent;
diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td
index a0cbcae0bdc3..f51ec64f0067 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -177,6 +177,9 @@ def m_x86_Features_Group : OptionGroup<"<x86 features group>">,
 def m_riscv_Features_Group : OptionGroup<"<riscv features group>">,
                              Group<m_Group>, DocName<"RISCV">;
 
+def m_sparc_Features_Group : OptionGroup<"<sparc features group>">,
+                             Group<m_Group>, DocName<"Sparc">;
+
 def m_libc_Group : OptionGroup<"<m libc group>">, Group<m_mips_Features_Group>,
                    Flags<[HelpHidden]>;
 
@@ -3451,6 +3454,58 @@ def mno_outline_atomics : Flag<["-"], "mno-outline-atomics">, Group<f_clang_Grou
 def mno_implicit_float : Flag<["-"], "mno-implicit-float">, Group<m_Group>,
   HelpText<"Don't generate implicit floating point instructions">;
 def mimplicit_float : Flag<["-"], "mimplicit-float">, Group<m_Group>;
+
+
+def msoft_fp_half : Flag<["-"], "msoft-fp-half">, Group<m_Group>, Flags<[CC1Option,CC1AsOption,NoArgumentUnused]>,
+  HelpText<"Use soft-float for all floating point operations with half precision numbers">;
+def msoft_fp_single : Flag<["-"], "msoft-fp-single">, Group<m_Group>, Flags<[CC1Option,CC1AsOption,NoArgumentUnused]>,
+  HelpText<"Use soft-float for all floating point operations with single precision numbers">;
+def msoft_fp_double : Flag<["-"], "msoft-fp-double">, Group<m_Group>, Flags<[CC1Option,CC1AsOption,NoArgumentUnused]>,
+  HelpText<"Use soft-float for all floating point operations with double precision numbers">;
+
+def mhard_fp_half : Flag<["-"], "mhard-fp-half">, Group<m_Group>, Flags<[CC1Option,CC1AsOption,NoArgumentUnused]>,
+  HelpText<"Use hard-float for all floating point operations with half precision numbers">;
+def mhard_fp_single : Flag<["-"], "mhard-fp-single">, Group<m_Group>, Flags<[CC1Option,CC1AsOption,NoArgumentUnused]>,
+  HelpText<"Use hard-float for all floating point operations with single precision numbers">;
+def mhard_fp_double : Flag<["-"], "mhard-fp-double">, Group<m_Group>, Flags<[CC1Option,CC1AsOption,NoArgumentUnused]>,
+  HelpText<"Use hard-float for all floating point operations with double precision numbers">;
+
+def msoft_fops_half : Joined<["-"], "msoft-fops-half=">, Group<m_Group>, Flags<[CC1Option,CC1AsOption,NoArgumentUnused]>,
+  HelpText<"Use soft-float for selected FP operations with half precision numbers">;
+def msoft_fops_single : Joined<["-"], "msoft-fops-single=">, Group<m_Group>, Flags<[CC1Option,CC1AsOption,NoArgumentUnused]>,
+  HelpText<"Use soft-float for selected FP operations with single precision numbers">;
+def msoft_fops_double : Joined<["-"], "msoft-fops-double=">, Group<m_Group>, Flags<[CC1Option,CC1AsOption,NoArgumentUnused]>,
+  HelpText<"Use soft-float for selected FP operations with double precision numbers">;
+
+def mhard_fops_half : Joined<["-"], "mhard-fops-half=">, Group<m_Group>, Flags<[CC1Option,CC1AsOption,NoArgumentUnused]>,
+  HelpText<"Use hard-float for selected FP operations with half precision numbers">;
+def mhard_fops_single : Joined<["-"], "mhard-fops-single=">, Group<m_Group>, Flags<[CC1Option,CC1AsOption,NoArgumentUnused]>,
+  HelpText<"Use hard-float for selected FP operations with single precision numbers">;
+def mhard_fops_double : Joined<["-"], "mhard-fops-double=">, Group<m_Group>, Flags<[CC1Option,CC1AsOption,NoArgumentUnused]>,
+  HelpText<"Use hard-float for selected FP operations with double precision numbers">;
+
+def menable_packedhalf : Flag<["-"], "menable-packedhalf">, Group<m_Group>, Flags<[CC1Option,CC1AsOption,NoArgumentUnused]>,
+  HelpText<"Enable packed type for hardware floating point half precision">;
+def menable_packedsingle : Flag<["-"], "menable-packedsingle">, Group<m_Group>, Flags<[CC1Option,CC1AsOption,NoArgumentUnused]>,
+  HelpText<"Enable packed type for hardware floating point single precision">;
+
+def daiteq_fpu_type : Joined<["-"], "daiteq-fpu-type=">, Group<m_Group>, Flags<[CC1Option,CC1AsOption,NoArgumentUnused]>,
+  HelpText<"Select which daiFPU is used (none/dpsp/sphp/dp/sp/hp/php/psp)">;
+def daiteq_swar_enable : Flag<["-"], "daiteq-swar-enable">, Group<m_Group>, Flags<[CC1Option,CC1AsOption,NoArgumentUnused]>,
+  HelpText<"Enable extension for the SWAR instruction extensions">;
+def daiteq_swar_type : Joined<["-"], "daiteq-swar-force-config=">, Group<m_Group>, Flags<[CC1Option,CC1AsOption,NoArgumentUnused]>,
+  Values<"infer,audio,video,alu">,HelpText<"Use specific kind of SWAR unit (infer/audio/video/alu)">;
+def munaligned_packed_fp : Flag<["-"], "munaligned-packed-fp">, Group<m_Group>, Flags<[CC1Option,CC1AsOption,NoArgumentUnused]>,
+  HelpText<"Allow unaligned packed FP variables">;
+
+def msoft_double : Joined<["-"], "msoft-double=">, Group<m_Group>, Flags<[CC1Option]>,
+  HelpText<"Bitmap of selected double FP operations which are processed in soft-float">;
+def msoft_single : Joined<["-"], "msoft-single=">, Group<m_Group>, Flags<[CC1Option]>,
+  HelpText<"Bitmap of selected single FP operations which are processed in soft-float">;
+def msoft_half : Joined<["-"], "msoft-half=">, Group<m_Group>, Flags<[CC1Option]>,
+  HelpText<"Bitmap of selected half FP operations which are processed in soft-float">;
+
+
 def mrecip : Flag<["-"], "mrecip">, Group<m_Group>;
 def mrecip_EQ : CommaJoined<["-"], "mrecip=">, Group<m_Group>, Flags<[CC1Option]>,
   MarshallingInfoStringVector<CodeGenOpts<"Reciprocals">>;
@@ -3701,6 +3756,11 @@ def print_target_triple : Flag<["-", "--"], "print-target-triple">,
   HelpText<"Print the normalized target triple">;
 def print_effective_triple : Flag<["-", "--"], "print-effective-triple">,
   HelpText<"Print the effective target triple">;
+
+def print_sf_uid : Flag<["-", "--"], "print-sf-uid">,
+  Group<CompileOnly_Group>, Flags<[CC1Option, CoreOption]>,
+  HelpText<"Print the unique identification of soft-float configuration">;
+
 def print_multiarch : Flag<["-", "--"], "print-multiarch">,
   HelpText<"Print the multiarch target triple">;
 def print_prog_name_EQ : Joined<["-", "--"], "print-prog-name=">,
diff --git a/clang/include/clang/Frontend/FrontendOptions.h b/clang/include/clang/Frontend/FrontendOptions.h
index 15c905d712a3..01ad40312af7 100644
--- a/clang/include/clang/Frontend/FrontendOptions.h
+++ b/clang/include/clang/Frontend/FrontendOptions.h
@@ -243,6 +243,9 @@ public:
   /// print the supported cpus for the current target
   unsigned PrintSupportedCPUs : 1;
 
+  /// print the unique identification of target FP configuration (soft-float settings)
+  unsigned PrintSFuid : 1;
+
   /// Output time trace profile.
   unsigned TimeTrace : 1;
 
diff --git a/clang/include/clang/Parse/Parser.h b/clang/include/clang/Parse/Parser.h
index 8eb3f9029d9d..27d5273c4c32 100644
--- a/clang/include/clang/Parse/Parser.h
+++ b/clang/include/clang/Parse/Parser.h
@@ -212,6 +212,11 @@ class Parser : public CodeCompletionHandler {
   std::unique_ptr<PragmaHandler> MaxTokensHerePragmaHandler;
   std::unique_ptr<PragmaHandler> MaxTokensTotalPragmaHandler;
 
+  std::unique_ptr<PragmaHandler> SwarSaturateHandler;
+  std::unique_ptr<PragmaHandler> SwarReductionHandler;
+  std::unique_ptr<PragmaHandler> SwarNormalizeHandler;
+  std::unique_ptr<PragmaHandler> SwarManualHandler;
+
   std::unique_ptr<CommentHandler> CommentSemaHandler;
 
   /// Whether the '>' token acts as an operator or not. This will be
diff --git a/clang/include/clang/Sema/Initialization.h b/clang/include/clang/Sema/Initialization.h
index 8feb66995f95..51e1eea17fc7 100644
--- a/clang/include/clang/Sema/Initialization.h
+++ b/clang/include/clang/Sema/Initialization.h
@@ -92,6 +92,9 @@ public:
     /// or vector.
     EK_VectorElement,
 
+    /// The entity being initialized is an element of a subword.
+    EK_SubWordElement,
+
     /// The entity being initialized is a field of block descriptor for
     /// the copied-in c++ object.
     EK_BlockElement,
@@ -523,7 +526,7 @@ public:
   /// element, sets the element index.
   void setElementIndex(unsigned Index) {
     assert(getKind() == EK_ArrayElement || getKind() == EK_VectorElement ||
-           getKind() == EK_ComplexElement);
+           getKind() == EK_ComplexElement || getKind() == EK_SubWordElement);
     this->Index = Index;
   }
 
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index d8b2546b81a3..b9b1ab239925 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -388,6 +388,9 @@ class Sema final {
                                       QualType ResultTy,
                                       ArrayRef<QualType> Args);
 
+  int theLastSubwordOperation = 0;
+  bool inForLoopSubwordChecking = false;
+
 public:
   /// The maximum alignment, same as in llvm::Value. We duplicate them here
   /// because that allows us not to duplicate the constants in clang code,
@@ -1960,6 +1963,9 @@ public:
   QualType BuildAddressSpaceAttr(QualType &T, Expr *AddrSpace,
                                  SourceLocation AttrLoc);
 
+  QualType BuildSubwordType(QualType BasicType, unsigned BitWidth,
+                            unsigned Packing, SourceLocation AttrLoc);
+
   bool CheckQualifiedFunctionForTypeId(QualType T, SourceLocation Loc);
 
   bool CheckFunctionReturnType(QualType T, SourceLocation Loc);
@@ -11722,6 +11728,9 @@ public:
                                     Expr::NullPointerConstantKind NullType,
                                     bool IsEqual, SourceRange Range);
 
+  /// type checking for subword binary operators
+  QualType CheckSubwordCompareOperands(ExprResult &LHS, ExprResult &RHS, SourceLocation Loc, BinaryOperatorKind Opc);
+
   /// type checking for vector binary operators.
   QualType CheckVectorOperands(ExprResult &LHS, ExprResult &RHS,
                                SourceLocation Loc, bool IsCompAssign,
@@ -11748,6 +11757,9 @@ public:
   bool areLaxCompatibleVectorTypes(QualType srcType, QualType destType);
   bool isLaxVectorConversion(QualType srcType, QualType destType);
 
+  QualType CheckSubwordOperands(ExprResult &LHS, ExprResult &RHS,
+                                SourceLocation Loc, bool IsCompAssign);
+
   /// type checking declaration initializers (C99 6.7.8)
   bool CheckForConstantInitializer(Expr *e, QualType t);
 
@@ -11829,6 +11841,11 @@ public:
   ExprResult CheckExtVectorCast(SourceRange R, QualType DestTy, Expr *CastExpr,
                                 CastKind &Kind);
 
+  bool areCompatibleSubwordTypes(QualType srcTy, QualType destTy);
+  bool CheckSubwordCast(SourceRange R, QualType SubwordTy, QualType Ty,
+                       CastKind &Kind);
+  ExprResult prepareSubwordSplat(QualType SubwordTy, Expr *SplattedExpr);
+
   ExprResult BuildCXXFunctionalCastExpr(TypeSourceInfo *TInfo, QualType Type,
                                         SourceLocation LParenLoc,
                                         Expr *CastExpr,
@@ -12720,6 +12737,21 @@ private:
   /// statement that produces control flow different from GCC.
   void CheckBreakContinueBinding(Expr *E);
 
+
+  // check and return type of swar operand or result - =0 no subword type, =1 subword, =2 array of subwords
+  int CheckSwarOperandType(Stmt *SubStmt, int *outBitWidth, bool *isSigned);
+public:
+  void ActOnPragmaSwarSaturate(SourceLocation PragmaLoc, Scope *curScope, bool enbl);
+  void ActOnPragmaSwarReduce(SourceLocation PragmaLoc, Scope *curScope, bool enbl);
+  void ActOnPragmaSwarNormalize(SourceLocation PragmaLoc, Scope *curScope, bool enbl);
+  void ActOnPragmaSwarManual(SourceLocation PragmaLoc, Scope *curScope, bool enbl);
+private:
+  Stmt *BuildSwarCtrlComp(Stmt *SubStmt, SourceLocation pos, int swop);
+  Stmt *CheckAndAddSwarCtrlOp(const BinaryOperator *BO, Stmt *SubStmt, bool *already, int *swop);
+  int CheckSwarArrayOperation(Stmt *block);
+  int CheckSwarOperation(Stmt *sop);
+
+
   /// Check whether receiver is mutable ObjC container which
   /// attempts to add itself into the container
   void CheckObjCCircularContainer(ObjCMessageExpr *Message);
diff --git a/clang/include/clang/Serialization/TypeBitCodes.def b/clang/include/clang/Serialization/TypeBitCodes.def
index e92e05810648..aa6ab83eecb8 100644
--- a/clang/include/clang/Serialization/TypeBitCodes.def
+++ b/clang/include/clang/Serialization/TypeBitCodes.def
@@ -62,5 +62,6 @@ TYPE_BIT_CODE(ExtInt, EXT_INT, 50)
 TYPE_BIT_CODE(DependentExtInt, DEPENDENT_EXT_INT, 51)
 TYPE_BIT_CODE(ConstantMatrix, CONSTANT_MATRIX, 52)
 TYPE_BIT_CODE(DependentSizedMatrix, DEPENDENT_SIZE_MATRIX, 53)
+TYPE_BIT_CODE(Subword, SUBWORD, 54)
 
 #undef TYPE_BIT_CODE
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 0e163f3161a3..6d3da8c25a03 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -2006,6 +2006,14 @@ TypeInfo ASTContext::getTypeInfoImpl(const Type *T) const {
     break;
   }
 
+  case Type::Subword: {
+    const auto *VT = cast<SubwordType>(T);
+    TypeInfo BasInfo = getTypeInfo(VT->getBasicType());
+    Width = VT->getPacking()*VT->getBitWidth();
+    Align = BasInfo.Align;
+    break;
+  }
+
   case Type::Builtin:
     switch (cast<BuiltinType>(T)->getKind()) {
     default: llvm_unreachable("Unknown builtin type!");
@@ -3501,6 +3509,7 @@ QualType ASTContext::getVariableArrayDecayedType(QualType type) const {
   case Type::Vector:
   case Type::DependentVector:
   case Type::ExtVector:
+  case Type::Subword:
   case Type::DependentSizedExtVector:
   case Type::ConstantMatrix:
   case Type::DependentSizedMatrix:
@@ -4134,6 +4143,44 @@ QualType ASTContext::getDependentSizedMatrixType(QualType ElementTy,
   return QualType(New, 0);
 }
 
+/// getSubwordType - Return the unique reference to a subword type of the
+/// specified type and bit width. Basic type must be a build-in type.
+QualType
+ASTContext::getSubwordType(QualType T, unsigned BitWidth,
+                           unsigned Packing) const {
+  assert(T->isBuiltinType());
+
+  // Check if we've already instantiated a vector of this type.
+  llvm::FoldingSetNodeID ID;
+  SubwordType::Profile(ID, T, BitWidth, Packing, Type::Subword);
+
+  void *InsertPos = nullptr;
+  if (SubwordType *SWTP = SubwordTypes.FindNodeOrInsertPos(ID, InsertPos)) {
+    return QualType(SWTP, 0);
+  }
+
+  // If the basic type isn't canonical, this won't be a canonical type either,
+  // so fill in the canonical type field.
+  QualType Canonical;
+  if (!T.isCanonical()) {
+    /* TODO: ArrLen can be different if the canonical type has different size */
+    Canonical = getSubwordType(getCanonicalType(T), BitWidth, Packing);
+
+    // Get the new insert position for the node we care about.
+    SubwordType *NewIP = SubwordTypes.FindNodeOrInsertPos(ID, InsertPos);
+    assert(!NewIP && "Shouldn't be in the map!");
+    (void)NewIP;
+  }
+  auto *New = new(*this, TypeAlignment)
+                SubwordType(Type::Subword, Canonical, T, BitWidth, Packing);
+//  if (New) {
+//    New->setArrLength(ArrLen);
+//  }
+  SubwordTypes.InsertNode(New, InsertPos);
+  Types.push_back(New);
+  return QualType(New, 0);
+}
+
 QualType ASTContext::getDependentAddressSpaceType(QualType PointeeType,
                                                   Expr *AddrSpaceExpr,
                                                   SourceLocation AttrLoc) const {
@@ -7744,6 +7791,7 @@ void ASTContext::getObjCEncodingForTypeImpl(QualType T, std::string &S,
   //FIXME. We should do a better job than gcc.
   case Type::Vector:
   case Type::ExtVector:
+  case Type::Subword:
   // Until we have a coherent encoding of these three types, issue warning.
     if (NotEncodedT)
       *NotEncodedT = T;
@@ -9956,6 +10004,11 @@ QualType ASTContext::mergeTypes(QualType LHS, QualType RHS,
                              RHSCan->castAs<ConstantMatrixType>()))
       return LHS;
     return {};
+
+  case Type::Subword:
+    // SubwordType MergeTypes ... eliminated above
+    return {};
+
   case Type::ObjCObject: {
     // Check if the types are assignment compatible.
     // FIXME: This should be type compatibility, e.g. whether
@@ -10397,6 +10450,10 @@ static QualType DecodeTypeFromStr(const char *&Str, const ASTContext &Context,
   // Read the base type.
   switch (*Str++) {
   default: llvm_unreachable("Unknown builtin type letter!");
+  case '#':
+//    fprintf(stderr,"SWAR type ...\n");
+    Type = Context.UnknownAnyTy;
+    break;
   case 'x':
     assert(HowLong == 0 && !Signed && !Unsigned &&
            "Bad modifiers used with 'x'!");
diff --git a/clang/lib/AST/ASTStructuralEquivalence.cpp b/clang/lib/AST/ASTStructuralEquivalence.cpp
index c4ff05ba9325..d0c80c7e76fe 100644
--- a/clang/lib/AST/ASTStructuralEquivalence.cpp
+++ b/clang/lib/AST/ASTStructuralEquivalence.cpp
@@ -873,6 +873,18 @@ static bool IsStructurallyEquivalent(StructuralEquivalenceContext &Context,
     break;
   }
 
+  case Type::Subword: {
+    const auto Sw1 = cast<SubwordType>(T1);
+    const auto Sw2 = cast<SubwordType>(T2);
+    if (!IsStructurallyEquivalent(Context, Sw1->getBasicType(), Sw2->getBasicType()))
+      return false;
+    if (Sw1->getBitWidth()!=Sw2->getBitWidth())
+      return false;
+    if (Sw1->getPacking()!=Sw2->getPacking())
+      return false;
+    break;
+  }
+
   case Type::FunctionProto: {
     const auto *Proto1 = cast<FunctionProtoType>(T1);
     const auto *Proto2 = cast<FunctionProtoType>(T2);
diff --git a/clang/lib/AST/Expr.cpp b/clang/lib/AST/Expr.cpp
index 11f10d4695fc..df4b0900b094 100644
--- a/clang/lib/AST/Expr.cpp
+++ b/clang/lib/AST/Expr.cpp
@@ -3230,6 +3230,15 @@ bool Expr::isConstantInitializer(ASTContext &Ctx, bool IsForRef,
       return true;
     }
 
+    if (ILE->getType()->isSubwordType()) {
+      unsigned numInits = ILE->getNumInits();
+      for (unsigned i = 0; i < numInits; i++) {
+        if (!ILE->getInit(i)->isConstantInitializer(Ctx, false, Culprit))
+          return false;
+      }
+      return true;
+    }
+
     if (ILE->getType()->isRecordType()) {
       unsigned ElementNo = 0;
       RecordDecl *RD = ILE->getType()->castAs<RecordType>()->getDecl();
diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp
index 01c0168d61a4..b2a86a09a94e 100644
--- a/clang/lib/AST/ExprConstant.cpp
+++ b/clang/lib/AST/ExprConstant.cpp
@@ -2246,7 +2246,7 @@ static bool CheckLValueConstantExpression(EvalInfo &Info, SourceLocation Loc,
       }
 
       APValue *V = MTE->getOrCreateValue(false);
-      assert(V && "evasluation result refers to uninitialised temporary");
+      assert(V && "evaluation result refers to uninitialised temporary");
       if (!CheckEvaluationResult(CheckEvaluationResultKind::ConstantExpression,
                                  Info, MTE->getExprLoc(), TempType, *V,
                                  Kind, SourceLocation(), CheckedTemps))
@@ -3164,10 +3164,40 @@ static bool HandleSizeof(EvalInfo &Info, SourceLocation Loc,
     return false;
   }
 
+  if (Type->isSubwordType()) {
+    auto tp = Type->castAs<SubwordType>()->getBasicType();
+    Size = Info.Ctx.getTypeSizeInChars(tp);
+    return true;
+  }
+
   Size = Info.Ctx.getTypeSizeInChars(Type);
   return true;
 }
 
+
+/// Get the size of the swar type in bits. (It returns All other types
+static bool HandleSizeofSwar(EvalInfo &Info, SourceLocation Loc,
+                         QualType Type, unsigned &Size) {
+  if (!Type->isSubwordType()) {
+    Size = 0;
+    return true;
+  }
+
+  if (Type->isDependentType()) {
+    Info.FFDiag(Loc);
+    return false;
+  }
+
+  if (!Type->isConstantSizeType()) {
+    // sizeof(vla) is not a constantexpr: C99 6.5.3.4p2.
+    // FIXME: Better diagnostic.
+    Info.FFDiag(Loc);
+    return false;
+  }
+  Size = Type->castAs<SubwordType>()->getBitWidth();
+  return true;
+}
+
 /// Update a pointer value to model pointer arithmetic.
 /// \param Info - Information about the ongoing evaluation.
 /// \param E - The expression being evaluated, for diagnostic purposes.
@@ -8354,7 +8384,8 @@ bool LValueExprEvaluator::VisitMemberExpr(const MemberExpr *E) {
 
 bool LValueExprEvaluator::VisitArraySubscriptExpr(const ArraySubscriptExpr *E) {
   // FIXME: Deal with vectors as array subscript bases.
-  if (E->getBase()->getType()->isVectorType())
+  if (E->getBase()->getType()->isVectorType() ||
+      E->getBase()->getType()->isSubwordType())
     return Error(E);
 
   APSInt Index;
@@ -10351,6 +10382,177 @@ bool VectorExprEvaluator::VisitBinaryOperator(const BinaryOperator *E) {
   return Success(LHSValue, E);
 }
 
+//===----------------------------------------------------------------------===//
+// Subword Evaluation
+//===----------------------------------------------------------------------===//
+
+namespace {
+  class SubwordExprEvaluator
+  : public ExprEvaluatorBase<SubwordExprEvaluator> {
+    APValue &Result;
+  public:
+
+    SubwordExprEvaluator(EvalInfo &info, APValue &Result)
+      : ExprEvaluatorBaseTy(info), Result(Result) {}
+
+/* the evaluator should interpret its value as one value of the basic type or an array of elements of the element type */
+    bool Success(APValue V, const Expr *E) {
+      assert(V.isInt());
+      // FIXME: remove this APValue copy.
+      Result = V;
+      return true;
+    }
+
+    bool ZeroInitialization(const Expr *E);
+
+    bool VisitIntegerLiteral(const IntegerLiteral *E) {
+      APValue Val = APValue(APSInt(E->getValue()));
+      return Success(Val, E);
+    }
+
+    bool VisitCastExpr(const CastExpr* E);
+    bool VisitInitListExpr(const InitListExpr *E);
+    bool VisitUnaryImag(const UnaryOperator *E);
+  };
+} // end anonymous namespace
+
+static bool EvaluateSubword(const Expr* E, APValue& Result, EvalInfo &Info) {
+  assert(E->isPRValue() && E->getType()->isSubwordType() && "not a subword rvalue");
+  return SubwordExprEvaluator(Info, Result).Visit(E);
+}
+
+bool SubwordExprEvaluator::VisitCastExpr(const CastExpr *E) {
+  const SubwordType *VTy = E->getType()->castAs<SubwordType>();
+  unsigned NElts = VTy->getPacking();
+
+  const Expr *SE = E->getSubExpr();
+  QualType SETy = SE->getType();
+
+  switch (E->getCastKind()) {
+  case CK_VectorSplat: {        // as for vector; fill all elements with a value: __attribute__((ext_vector_type(4))) int v = 5;
+    APValue Val = APValue();
+    if (SETy->isIntegerType()) {
+      APSInt IntResult;
+      if (!EvaluateInteger(SE, IntResult, Info))
+        return false;
+
+      Val = APValue(std::move(IntResult));
+    } else {
+      return Error(E);
+    }
+
+    // Splat and create APValue. NElts x Val
+    APValue Elt(Val);
+    return Success(Elt, E);
+  }
+  case CK_BitCast: {
+    // Evaluate the operand into an APInt we can extract from.
+    llvm::APInt SValInt;
+    if (!EvalAndBitcastToAPInt(Info, SE, SValInt))
+      return false;
+    // Extract the elements
+    unsigned EltSize = VTy->getBitWidth();
+/* TODO: get size of basictype from ASTContext.getTypeSize(BasTy) */
+    unsigned BasTyWidth = ((NElts*EltSize)>32) ? 64 : 32;
+    bool BigEndian = Info.Ctx.getTargetInfo().isBigEndian();
+    llvm::APInt Elts = llvm::APInt(BasTyWidth, 0, false); /* TODO: change fixed width to bitwidth of subword basicType */
+    for (unsigned i = 0; i < NElts; i++) {
+      if (BigEndian)
+        Elts += SValInt.rotl(i*EltSize+EltSize).zextOrTrunc(EltSize);
+      else
+        Elts += SValInt.rotr(i*EltSize).zextOrTrunc(EltSize);
+    }
+    APValue Val = APValue(APSInt(Elts));
+    return Success(Val, E);
+  }
+  default:
+    return ExprEvaluatorBaseTy::VisitCastExpr(E);
+  }
+}
+
+bool SubwordExprEvaluator::VisitInitListExpr(const InitListExpr *E) {
+  const SubwordType *VT = E->getType()->castAs<SubwordType>();
+  unsigned NumInits = E->getNumInits();
+
+  unsigned NumElements = VT->getPacking();
+//std::raise(SIGINT);
+  QualType BasTy = VT->getBasicType();
+  unsigned ElmBW = VT->getBitWidth();
+  // SW basic type sign ???
+  bool BasTpIsSigned = false;
+  const Type *BTT = BasTy.getTypePtrOrNull();
+  if (BTT && BTT->isSignedIntegerOrEnumerationType()) BasTpIsSigned = true;
+  // element limits
+  int ernglow, ernghi;
+  bool BigEndian = Info.Ctx.getTargetInfo().isBigEndian();
+
+  if (BasTpIsSigned) {
+    ernglow = -(1<<(ElmBW-1));
+    ernghi = (1<<(ElmBW-1))-1;
+  } else {
+    ernglow = 0;
+    ernghi = (1<<ElmBW)-1;
+  }
+
+  APValue Val = APValue();
+
+  // The number of initializers can be less than the number of subword
+  // elements. Missing trailing elements should be initialized with zeroes.
+  unsigned CountInits = 0, CountElts = 0;
+/* TODO: get size of basictype from ASTContext.getTypeSize(BasTy) */
+  unsigned BasTyWidth = ((NumElements*ElmBW)>32) ? 64 : 32;
+  llvm::APInt sInt(BasTyWidth, true);
+  uint64_t swval = 0;
+  while (CountElts < NumElements) {
+    // Handle nested vector initialization.
+    //if (CountInits < NumInits
+        //&& E->getInit(CountInits)->getType()->isVectorType()) {
+      //APValue v;
+      //if (!EvaluateVector(E->getInit(CountInits), v, Info))
+        //return Error(E);
+      //unsigned vlen = v.getVectorLength();
+      //for (unsigned j = 0; j < vlen; j++)
+        //Elements.push_back(v.getVectorElt(j));
+      //CountElts += vlen;
+    //} else
+    if (BasTy->isIntegerType()) {
+      if (CountInits < NumInits) {
+        if (!EvalAndBitcastToAPInt(Info, E->getInit(CountInits), sInt))
+          return false;
+        int64_t ev = sInt.getSExtValue();
+        if (ev<ernglow || ev>ernghi)
+          return false;
+        uint64_t v = ((uint64_t)(ev & ((1<<ElmBW)-1)))<<(CountElts*ElmBW);
+/* TODO: respect BigEndian */
+        swval += v;
+      }
+      //} else // trailing integer zero.
+        //sInt = Info.Ctx.MakeIntValue(0, BasTy);
+      CountElts++;
+    }
+    CountInits++;
+  }
+  llvm::APInt swarVal(BasTyWidth, swval, false);
+  Val = APValue(APSInt(swarVal));
+  return Success(Val, E);
+}
+
+bool SubwordExprEvaluator::ZeroInitialization(const Expr *E) {
+  const auto *VT = E->getType()->castAs<SubwordType>();
+  QualType BasTy = VT->getBasicType();
+  APValue ZeroVal;
+  if (BasTy->isIntegerType())
+    ZeroVal = APValue(Info.Ctx.MakeIntValue(0, BasTy));
+  else
+    return Error(E);
+  return Success(ZeroVal, E);
+}
+
+bool SubwordExprEvaluator::VisitUnaryImag(const UnaryOperator *E) {
+  VisitIgnoredValue(E->getSubExpr());
+  return ZeroInitialization(E);
+}
+
 //===----------------------------------------------------------------------===//
 // Array Evaluation
 //===----------------------------------------------------------------------===//
@@ -11065,6 +11267,9 @@ EvaluateBuiltinClassifyType(QualType T, const LangOptions &LangOpts) {
     // other types that don't fit into the regular classification the same way.
     return GCCTypeClass::None;
 
+  case Type::Subword:
+    return GCCTypeClass::None;
+
   case Type::LValueReference:
   case Type::RValueReference:
     llvm_unreachable("invalid type for expression");
@@ -11657,6 +11862,30 @@ bool IntExprEvaluator::VisitBuiltinCallExpr(const CallExpr *E,
     return Success(Val.countLeadingZeros(), E);
   }
 
+  case Builtin::BI__builtin_swarctrl: {
+    APSInt Val;
+    if (!EvaluateInteger(E->getArg(0), Val, Info))
+      return false;
+    if (!Val)
+      return Error(E);
+    if (Val.isNegative()) /* cannot be a negative value */
+      return Error(E);
+    return Success(Val, E);
+  }
+
+  case Builtin::BI__builtin_swaraccum: {
+    APSInt Val;
+    if (!EvaluateInteger(E->getArg(0), Val, Info)) {
+      return false;
+    }
+    if (!Val)
+      return Error(E);
+    if (Val.isNegative()) /* cannot be a negative value */
+      return Error(E);
+    return true;
+  }
+
+
   case Builtin::BI__builtin_constant_p: {
     const Expr *Arg = E->getArg(0);
     if (EvaluateBuiltinConstantP(Info, Arg))
@@ -13040,6 +13269,17 @@ bool IntExprEvaluator::VisitUnaryExprOrTypeTraitExpr(
       return false;
     return Success(Sizeof, E);
   }
+  case UETT_SizeOfSwar:
+  {
+    QualType SrcTy = E->getTypeOfArgument();
+    if (const ReferenceType *Ref = SrcTy->getAs<ReferenceType>())
+      SrcTy = Ref->getPointeeType();
+
+    unsigned SoS;
+    if (!HandleSizeofSwar(Info, E->getExprLoc(), SrcTy, SoS))
+      return false;
+    return Success(SoS, E);
+  }
   case UETT_OpenMPRequiredSimdAlign:
     assert(E->isArgumentType());
     return Success(
@@ -13677,6 +13917,7 @@ bool FloatExprEvaluator::VisitCallExpr(const CallExpr *E) {
     return true;
 
   case Builtin::BI__builtin_fabs:
+  case Builtin::BI__builtin_fabsh:
   case Builtin::BI__builtin_fabsf:
   case Builtin::BI__builtin_fabsl:
   case Builtin::BI__builtin_fabsf128:
@@ -14525,6 +14766,9 @@ static bool Evaluate(APValue &Result, EvalInfo &Info, const Expr *E) {
   } else if (T->isVectorType()) {
     if (!EvaluateVector(E, Result, Info))
       return false;
+  } else if (T->isSubwordType()) {
+    if (!EvaluateSubword(E, Result, Info))
+      return false;
   } else if (T->isIntegralOrEnumerationType()) {
     if (!IntExprEvaluator(Info, Result).Visit(E))
       return false;
@@ -14610,6 +14854,10 @@ static bool EvaluateInPlace(APValue &Result, EvalInfo &Info, const LValue &This,
     QualType T = E->getType();
     if (T->isArrayType())
       return EvaluateArray(E, This, Result, Info);
+    else if (T->isSubwordType())
+    {
+      return EvaluateSubword(E, Result, Info);
+    }
     else if (T->isRecordType())
       return EvaluateRecord(E, This, Result, Info);
     else if (T->isAtomicType()) {
diff --git a/clang/lib/AST/ItaniumMangle.cpp b/clang/lib/AST/ItaniumMangle.cpp
index 8cbac66fcf00..c54a66776791 100644
--- a/clang/lib/AST/ItaniumMangle.cpp
+++ b/clang/lib/AST/ItaniumMangle.cpp
@@ -2242,6 +2242,7 @@ bool CXXNameMangler::mangleUnresolvedTypeOrSimpleId(QualType Ty,
   case Type::ExtVector:
   case Type::ConstantMatrix:
   case Type::DependentSizedMatrix:
+  case Type::Subword:
   case Type::FunctionProto:
   case Type::FunctionNoProto:
   case Type::Paren:
@@ -3739,6 +3740,15 @@ void CXXNameMangler::mangleType(const DependentSizedMatrixType *T) {
   Out << "E";
 }
 
+void CXXNameMangler::mangleType(const SubwordType *T) {
+  Out << "Sw";
+  mangleNumber(T->getBitWidth());
+  Out << '_';
+  mangleNumber(T->getPacking());
+  Out << '_';
+  mangleType(T->getBasicType());
+}
+
 void CXXNameMangler::mangleType(const DependentAddressSpaceType *T) {
   SplitQualType split = T->getPointeeType().split();
   mangleQualifiers(split.Quals, T);
@@ -4621,6 +4631,13 @@ recurse:
       Diags.Report(DiagID);
       return;
     }
+    case UETT_SizeOfSwar: {
+      DiagnosticsEngine &Diags = Context.getDiags();
+      unsigned DiagID = Diags.getCustomDiagID(
+          DiagnosticsEngine::Error,
+          "cannot yet mangle sizeofswar");
+      Diags.Report(DiagID);
+    }
     }
     break;
   }
diff --git a/clang/lib/AST/MicrosoftMangle.cpp b/clang/lib/AST/MicrosoftMangle.cpp
index d89cddd2adda..67682fe5ac41 100644
--- a/clang/lib/AST/MicrosoftMangle.cpp
+++ b/clang/lib/AST/MicrosoftMangle.cpp
@@ -3112,6 +3112,14 @@ void MicrosoftCXXNameMangler::mangleType(const DependentSizedMatrixType *T,
   Diags.Report(Range.getBegin(), DiagID) << Range;
 }
 
+void MicrosoftCXXNameMangler::mangleType(const SubwordType *T, Qualifiers,
+                                        SourceRange Range) {
+  DiagnosticsEngine &Diags = Context.getDiags();
+  unsigned DiagID = Diags.getCustomDiagID(DiagnosticsEngine::Error,
+                              "cannot mangle this special sub-word type yes");
+  Diags.Report(Range.getBegin(), DiagID) << Range;
+}
+
 void MicrosoftCXXNameMangler::mangleType(const DependentAddressSpaceType *T,
                                          Qualifiers, SourceRange Range) {
   DiagnosticsEngine &Diags = Context.getDiags();
diff --git a/clang/lib/AST/Type.cpp b/clang/lib/AST/Type.cpp
index 4a2fc5219ef0..f739ff73c30e 100644
--- a/clang/lib/AST/Type.cpp
+++ b/clang/lib/AST/Type.cpp
@@ -363,6 +363,15 @@ void DependentExtIntType::Profile(llvm::FoldingSetNodeID &ID,
   NumBitsExpr->Profile(ID, Context, true);
 }
 
+SubwordType::SubwordType(TypeClass tc, QualType canonType, QualType basicType,
+                          unsigned bitWidth, unsigned packing)
+    : Type(tc, canonType, basicType->getDependence()), BasicType(basicType), BitWidth(bitWidth), Packing(packing) {
+//  unsigned btsz = getASTContext()->getTypeInfo(basicType).Width;
+//  unsigned maxPack =  32 / BitWidth;
+//  assert(Packing<=maxPack && "number of elements in the basic type is too high");
+//  if (Packing==0) Packing = maxPack; /* we don't know target for register size */
+}
+
 /// getArrayElementTypeNoTypeQual - If this is an array type, return the
 /// element type of the array, potentially with type qualifiers missing.
 /// This method should never be used when type qualifiers are meaningful.
@@ -2600,6 +2609,10 @@ bool Type::isLiteralType(const ASTContext &Ctx) const {
   if (isa<AutoType>(BaseTy->getCanonicalTypeInternal()))
     return true;
 
+  if (isSubwordType()) { /* is it safe ? */
+    return true;
+  }
+
   return false;
 }
 
@@ -3889,6 +3902,8 @@ static CachedProperties computeCachedProperties(const Type *T) {
     return Cache::get(cast<VectorType>(T)->getElementType());
   case Type::ConstantMatrix:
     return Cache::get(cast<ConstantMatrixType>(T)->getElementType());
+  case Type::Subword:
+    return Cache::get(cast<SubwordType>(T)->getBasicType());
   case Type::FunctionNoProto:
     return Cache::get(cast<FunctionType>(T)->getReturnType());
   case Type::FunctionProto: {
@@ -3978,6 +3993,8 @@ LinkageInfo LinkageComputer::computeTypeLinkageInfo(const Type *T) {
   case Type::ConstantMatrix:
     return computeTypeLinkageInfo(
         cast<ConstantMatrixType>(T)->getElementType());
+  case Type::Subword:
+    return computeTypeLinkageInfo(cast<SubwordType>(T)->getBasicType());
   case Type::FunctionNoProto:
     return computeTypeLinkageInfo(cast<FunctionType>(T)->getReturnType());
   case Type::FunctionProto: {
@@ -4149,6 +4166,7 @@ bool Type::canHaveNullability(bool ResultIfUnknown) const {
   case Type::ExtVector:
   case Type::ConstantMatrix:
   case Type::DependentSizedMatrix:
+  case Type::Subword:
   case Type::DependentAddressSpace:
   case Type::FunctionProto:
   case Type::FunctionNoProto:
diff --git a/clang/lib/AST/TypePrinter.cpp b/clang/lib/AST/TypePrinter.cpp
index 5de22f76f458..6fd951c8e32a 100644
--- a/clang/lib/AST/TypePrinter.cpp
+++ b/clang/lib/AST/TypePrinter.cpp
@@ -262,6 +262,7 @@ bool TypePrinter::canPrefixQualifiers(const Type *T,
     case Type::ExtVector:
     case Type::ConstantMatrix:
     case Type::DependentSizedMatrix:
+    case Type::Subword:
     case Type::FunctionProto:
     case Type::FunctionNoProto:
     case Type::Paren:
@@ -794,6 +795,19 @@ void TypePrinter::printDependentSizedMatrixAfter(
   printAfter(T->getElementType(), OS);
 }
 
+void TypePrinter::printSubwordBefore(const SubwordType *T, raw_ostream &OS) {
+  unsigned pck = T->getPacking();
+  if (pck)
+    OS << "__attribute__((subword " << pck << "x" << T->getBitWidth() << "b) in ";
+  else
+    OS << "__attribute__((subword " << T->getBitWidth() << "b) in ";
+  printBefore(T->getBasicType(), OS);
+  OS <<" )";
+}
+void TypePrinter::printSubwordAfter(const SubwordType *T, raw_ostream &OS) {
+  printAfter(T->getBasicType(), OS);
+}
+
 void
 FunctionProtoType::printExceptionSpecification(raw_ostream &OS,
                                                const PrintingPolicy &Policy)
diff --git a/clang/lib/Basic/TargetInfo.cpp b/clang/lib/Basic/TargetInfo.cpp
index 5f8e04c2bd6c..df37d7dba8be 100644
--- a/clang/lib/Basic/TargetInfo.cpp
+++ b/clang/lib/Basic/TargetInfo.cpp
@@ -145,6 +145,13 @@ TargetInfo::TargetInfo(const llvm::Triple &T) : TargetOpts(), Triple(T) {
   PlatformMinVersion = VersionTuple();
 
   MaxOpenCLWorkGroupSize = 1024;
+
+//  daiteqFPUType = 0;
+  SoftFopsHalf = 0;
+  SoftFopsSingle = 0;
+  SoftFopsDouble = 0;
+  EnabledPackedHalf = false;
+  EnabledPackedSingle = false;
 }
 
 // Out of line virtual dtor for TargetInfo.
@@ -874,3 +881,34 @@ void TargetInfo::copyAuxTarget(const TargetInfo *Aux) {
   auto *Src = static_cast<const TransferrableTargetInfo*>(Aux);
   *Target = *Src;
 }
+
+
+
+const struct TargetInfo::SoftFopsTableStruct TargetInfo::SoftFopsTable[] = {
+    {FPOP_ADD,'a'},{FPOP_SUB,'s'},{FPOP_MUL,'m'},{FPOP_DIV,'d'},
+    {FPOP_MULEX,'M'},{FPOP_SQRT,'S'},{FPOP_CMP,'c'},
+    {FPOP_CI2F,'f'},{FPOP_CF2I,'i'},{FPOP_CFUP,'h'},{FPOP_CFDN,'l'},
+    {FPOP_ABS,'A'},{FPOP_PACK,'p'},{FPOP_MOV,'C'},{FPOP_NEG,'n'},
+    {0,0}
+  };
+
+std::string TargetInfo::getFopsDesc(unsigned mask) {
+  std::string out="";
+  int i =0;
+  while (SoftFopsTable[i].mask) {
+    if (mask & SoftFopsTable[i].mask) out.push_back(SoftFopsTable[i].flag);
+    i++;
+  }
+  return out;
+}
+
+unsigned TargetInfo::getFopsMask(const std::string &desc) {
+  unsigned mask = 0;
+  int i =0;
+  while (SoftFopsTable[i].mask) {
+    if (desc.find(SoftFopsTable[i].flag)!=std::string::npos)
+      mask |= SoftFopsTable[i].mask;
+    i++;
+  }
+  return mask;
+}
diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp
index 9705129b39d8..12ac2b688903 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -161,9 +161,15 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
   }
 
+  if (HasD || HasXfps)
+    Builder.defineMacro("__riscv_flen", "64");
+  else if (HasF || HasXfph)
+    Builder.defineMacro("__riscv_flen", "32");
+  else if (HasZfh)
+    Builder.defineMacro("__riscv_flen", "16");
+
   if (HasF || HasD) {
     Builder.defineMacro("__riscv_f", "2000000");
-    Builder.defineMacro("__riscv_flen", HasD ? "64" : "32");
     Builder.defineMacro("__riscv_fdiv");
     Builder.defineMacro("__riscv_fsqrt");
   }
@@ -220,13 +226,34 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
     Builder.defineMacro("__riscv_zbt", "93000");
 
   if (HasZfh)
-    Builder.defineMacro("__riscv_zfh", "1000");
+    Builder.defineMacro("__riscv_zfh", "10000");
 
   if (HasZvamo)
     Builder.defineMacro("__riscv_zvamo", "10000");
 
   if (HasZvlsseg)
     Builder.defineMacro("__riscv_zvlsseg", "10000");
+
+  if (HasXfph)
+    Builder.defineMacro("__riscv_xfph", "10000");
+
+  if (HasXfps)
+    Builder.defineMacro("__riscv_xfps", "10000");
+
+  if (HasXswar)
+    Builder.defineMacro("__riscv_xswar", "10000");
+
+  Builder.defineMacro("SOFT_FOPS_HALF", Twine(Opts.SoftFopsHalf));
+  Builder.defineMacro("SOFT_FOPS_SINGLE", Twine(Opts.SoftFopsSingle));
+  Builder.defineMacro("SOFT_FOPS_DOUBLE", Twine(Opts.SoftFopsDouble));
+  if (Opts.EnabledPackedHalf)
+    Builder.defineMacro("FP_PACKEDHALF_ENABLED", Twine(1));
+  else
+    Builder.defineMacro("FP_PACKEDHALF_ENABLED", Twine(0));
+  if (Opts.EnabledPackedSingle)
+    Builder.defineMacro("FP_PACKEDSINGLE_ENABLED", Twine(1));
+  else
+    Builder.defineMacro("FP_PACKEDSINGLE_ENABLED", Twine(0));
 }
 
 const Builtin::Info RISCVTargetInfo::BuiltinInfo[] = {
@@ -278,9 +305,12 @@ bool RISCVTargetInfo::hasFeature(StringRef Feature) const {
       .Case("experimental-zbr", HasZbr)
       .Case("experimental-zbs", HasZbs)
       .Case("experimental-zbt", HasZbt)
-      .Case("experimental-zfh", HasZfh)
       .Case("experimental-zvamo", HasZvamo)
       .Case("experimental-zvlsseg", HasZvlsseg)
+      .Case("zfh", HasZfh)
+      .Case("x-fph", HasXfph)
+      .Case("x-fps", HasXfps)
+      .Case("x-swar", HasXswar)
       .Default(false);
 }
 
@@ -324,8 +354,14 @@ bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
       HasZbs = true;
     else if (Feature == "+experimental-zbt")
       HasZbt = true;
-    else if (Feature == "+experimental-zfh")
+    else if (Feature == "+zfh")
       HasZfh = true;
+    else if (Feature == "+x-fph")
+      HasXfph = true;
+    else if (Feature == "+x-fps")
+      HasXfps = true;
+    else if (Feature == "+x-swar")
+      HasXswar = true;
     else if (Feature == "+experimental-zvamo")
       HasZvamo = true;
     else if (Feature == "+experimental-zvlsseg")
diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index 7e0846581ca1..024b47f8dca1 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -46,6 +46,9 @@ protected:
   bool HasZfh = false;
   bool HasZvamo = false;
   bool HasZvlsseg = false;
+  bool HasXfph = false;
+  bool HasXfps = false;
+  bool HasXswar = false;
 
   static const Builtin::Info BuiltinInfo[];
 
diff --git a/clang/lib/Basic/Targets/Sparc.cpp b/clang/lib/Basic/Targets/Sparc.cpp
index 5eeb77406c34..ce6cb9d8f946 100644
--- a/clang/lib/Basic/Targets/Sparc.cpp
+++ b/clang/lib/Basic/Targets/Sparc.cpp
@@ -54,6 +54,13 @@ ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const {
 bool SparcTargetInfo::hasFeature(StringRef Feature) const {
   return llvm::StringSwitch<bool>(Feature)
       .Case("softfloat", SoftFloat)
+
+      //.Case("softfphalf", SoftFopsHalf)
+      //.Case("softfpsingle", SoftFopsSingle)
+      //.Case("softfpdouble", SoftFopsDouble)
+      //.Case("enablepackedhalf", EnabledPackedHalf)
+      //.Case("enablepackedsingle", EnabledPackedSingle)
+
       .Case("sparc", true)
       .Default(false);
 }
@@ -142,6 +149,18 @@ void SparcTargetInfo::getTargetDefines(const LangOptions &Opts,
 
   if (SoftFloat)
     Builder.defineMacro("SOFT_FLOAT", "1");
+
+  Builder.defineMacro("SOFT_FOPS_HALF", Twine(SoftFopsHalf));
+  Builder.defineMacro("SOFT_FOPS_SINGLE", Twine(SoftFopsSingle));
+  Builder.defineMacro("SOFT_FOPS_DOUBLE", Twine(SoftFopsDouble));
+  if (EnabledPackedHalf)
+    Builder.defineMacro("FP_PACKEDHALF_ENABLED", Twine(1));
+  else
+    Builder.defineMacro("FP_PACKEDHALF_ENABLED", Twine(0));
+  if (EnabledPackedSingle)
+    Builder.defineMacro("FP_PACKEDSINGLE_ENABLED", Twine(1));
+  else
+    Builder.defineMacro("FP_PACKEDSINGLE_ENABLED", Twine(0));
 }
 
 void SparcV8TargetInfo::getTargetDefines(const LangOptions &Opts,
diff --git a/clang/lib/Basic/Targets/Sparc.h b/clang/lib/Basic/Targets/Sparc.h
index 07844abafe11..abdd8278b98f 100644
--- a/clang/lib/Basic/Targets/Sparc.h
+++ b/clang/lib/Basic/Targets/Sparc.h
@@ -26,7 +26,8 @@ class LLVM_LIBRARY_VISIBILITY SparcTargetInfo : public TargetInfo {
 
 public:
   SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
-      : TargetInfo(Triple), SoftFloat(false) {}
+      : TargetInfo(Triple), SoftFloat(false)/* , EnabledSWARdaiteq(false), daiteqFPUType(0),
+        SoftFopsHalf(0), SoftFopsSingle(0), SoftFopsDouble(0), EnabledPackedHalf(false), EnabledPackedSingle(false) */ {}
 
   int getEHDataRegisterNumber(unsigned RegNo) const override {
     if (RegNo == 0)
@@ -36,6 +37,9 @@ public:
     return -1;
   }
 
+  static std::string getFopsDesc(unsigned mask);
+  static unsigned getFopsMask(const std::string &desc);
+
   bool handleTargetFeatures(std::vector<std::string> &Features,
                             DiagnosticsEngine &Diags) override {
     // Check if software floating point is enabled
@@ -151,7 +155,10 @@ class LLVM_LIBRARY_VISIBILITY SparcV8TargetInfo : public SparcTargetInfo {
 public:
   SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
       : SparcTargetInfo(Triple, Opts) {
-    resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64");
+    if (Triple.getVendor()==llvm::Triple::Daiteq)
+      resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64-f16:16");
+    else
+      resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64");
     // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int.
     switch (getTriple().getOS()) {
     default:
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 1a02965b223e..43257c4ec523 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -2319,9 +2319,11 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID,
                                    Intrinsic::exp2,
                                    Intrinsic::experimental_constrained_exp2));
 
+    case Builtin::BIfabsh:
     case Builtin::BIfabs:
     case Builtin::BIfabsf:
     case Builtin::BIfabsl:
+    case Builtin::BI__builtin_fabsh:
     case Builtin::BI__builtin_fabs:
     case Builtin::BI__builtin_fabsf:
     case Builtin::BI__builtin_fabsf16:
@@ -2488,9 +2490,11 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID,
                                    Intrinsic::sin,
                                    Intrinsic::experimental_constrained_sin));
 
+    case Builtin::BIsqrth:
     case Builtin::BIsqrt:
     case Builtin::BIsqrtf:
     case Builtin::BIsqrtl:
+    case Builtin::BI__builtin_sqrth:
     case Builtin::BI__builtin_sqrt:
     case Builtin::BI__builtin_sqrtf:
     case Builtin::BI__builtin_sqrtf16:
@@ -2500,6 +2504,10 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID,
                                    Intrinsic::sqrt,
                                    Intrinsic::experimental_constrained_sqrt));
 
+    case Builtin::BI__builtin_sqrtpf:
+    case Builtin::BIsqrtpf:
+      return RValue::get(emitUnaryBuiltin(*this, E, Intrinsic::sqrt));
+
     case Builtin::BItrunc:
     case Builtin::BItruncf:
     case Builtin::BItruncl:
@@ -5151,6 +5159,168 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID,
                                                      Str.getPointer(), Zeros);
     return RValue::get(Ptr);
   }
+
+/* support for inserting an instruction for setting the swar control word */
+/* if 'swarctrl' is used the bitwidth is used according to a target machine */
+  case Builtin::BI__builtin_swarctrl:
+  {
+    llvm::Triple::ArchType arch = CGM.getTriple().getArch();
+    bool use64b = (((BuiltinIDIfNoAsmLabel==Builtin::BI__builtin_swarctrl) && 
+                      (arch==llvm::Triple::riscv64)) );
+    /* use constant as the configuration */
+    if (E->getArg(0)->isIntegerConstantExpr(getContext(), nullptr)) {
+      unsigned cfg = E->getArg(0)->EvaluateKnownConstInt(getContext()).getZExtValue();
+      if (arch==llvm::Triple::sparc) {
+        if (cfg<0x2000) { /* can be an immediate value */
+          llvm::FunctionType *FTy = llvm::FunctionType::get(VoidTy, false);
+          llvm::InlineAsm *Emit = InlineAsm::get(FTy, "wr %g0, 0x" + utohexstr(cfg) + ", %asr22    ! swarctrl(0x" + utohexstr(cfg) + ")", "", true);
+          return RValue::get(Builder.CreateCall(Emit));
+        } else {
+          llvm::FunctionType *FTySet = llvm::FunctionType::get(Int32Ty, false);
+          llvm::FunctionType *FTyGet = llvm::FunctionType::get(VoidTy, {Int32Ty}, false);
+
+          llvm::InlineAsm *EmitSet = InlineAsm::get(FTySet, "set 0x" + utohexstr(cfg) + ",$0", "=r", true);
+          Value *TmpVal = Builder.CreateCall(EmitSet);
+
+          llvm::InlineAsm *EmitGet = InlineAsm::get(FTyGet, "wr $0, 0, %asr22  ! swarctrl = 0x" + utohexstr(cfg), "r", true);
+          return RValue::get(Builder.CreateCall(EmitGet, {TmpVal}));
+        }
+      } else if (arch==llvm::Triple::riscv32 || arch==llvm::Triple::riscv64) {
+        if (use64b) { // riscv64 and requested i64
+          llvm::FunctionType *FTySet = llvm::FunctionType::get(Int64Ty, false);
+          llvm::FunctionType *FTyGet = llvm::FunctionType::get(VoidTy, {Int64Ty}, false);
+        llvm::InlineAsm *EmitSet = InlineAsm::get(FTySet, "li $0, 0x" + utohexstr(cfg), "=r", true);
+        Value *TmpVal = Builder.CreateCall(EmitSet);
+        llvm::InlineAsm *EmitGet = InlineAsm::get(FTyGet, "csrw swarctrlstat, $0", "r", true);
+        return RValue::get(Builder.CreateCall(EmitGet, {TmpVal}));
+        } else { // riscv32 or riscv64 and requested i32
+        llvm::FunctionType *FTySet = llvm::FunctionType::get(Int32Ty, false);
+        llvm::FunctionType *FTyGet = llvm::FunctionType::get(VoidTy, {Int32Ty}, false);
+        llvm::InlineAsm *EmitSet = InlineAsm::get(FTySet, "li $0, 0x" + utohexstr(cfg), "=r", true);
+        Value *TmpVal = Builder.CreateCall(EmitSet);
+        llvm::InlineAsm *EmitGet = InlineAsm::get(FTyGet, "csrw swarctrlstat, $0", "r", true);
+        return RValue::get(Builder.CreateCall(EmitGet, {TmpVal}));
+      }
+      }
+    /* variable as the configuration */
+    } else {
+      if (arch==llvm::Triple::sparc) {
+        llvm::FunctionType *FTy = llvm::FunctionType::get(VoidTy, {Int32Ty}, false);
+        llvm::Value *R = EmitScalarExpr(E->getArg(0));
+        llvm::InlineAsm *Emit = InlineAsm::get(FTy, "wr $0, %asr22  ! swarctrl(var)", "r", true);
+        return RValue::get(Builder.CreateCall(Emit, {R}));
+      } else if (arch==llvm::Triple::riscv32 || arch==llvm::Triple::riscv64) {
+        if (use64b) {
+          llvm::FunctionType *FTy = llvm::FunctionType::get(VoidTy, {Int64Ty}, false);
+        llvm::Value *R = EmitScalarExpr(E->getArg(0));
+        llvm::InlineAsm *Emit = InlineAsm::get(FTy, "csrw swarctrlstat, $0    # swarctrl(var)", "r", true);
+        return RValue::get(Builder.CreateCall(Emit, {R}));
+        } else {
+        llvm::FunctionType *FTy = llvm::FunctionType::get(VoidTy, {Int32Ty}, false);
+        llvm::Value *R = EmitScalarExpr(E->getArg(0));
+        llvm::InlineAsm *Emit = InlineAsm::get(FTy, "csrw swarctrlstat, $0    # swarctrl(var)", "r", true);
+        return RValue::get(Builder.CreateCall(Emit, {R}));
+        }
+      }
+    }
+    return RValue::get(nullptr);
+  }
+  
+  case Builtin::BI__builtin_swaraccum:
+  {
+    llvm::Triple::ArchType arch = CGM.getTriple().getArch();
+    bool use64b = (((BuiltinIDIfNoAsmLabel==Builtin::BI__builtin_swaraccum) && 
+                    (arch==llvm::Triple::riscv64)) );
+    if (E->getArg(0)->isIntegerConstantExpr(getContext(), nullptr)) {
+      llvm::FunctionType *FTy = llvm::FunctionType::get(
+                                  ConvertType(E->getType()), false);
+      if (arch==llvm::Triple::sparc) {
+        unsigned cfg = E->getArg(0)->EvaluateKnownConstInt(getContext()).getZExtValue();
+        llvm::InlineAsm *Emit = InlineAsm::get(FTy, "wr %g0, 0x" + utohexstr(cfg) + ", %asr23; nop; rd %asr23, $0", "=r", true);
+        return RValue::get(Builder.CreateCall(Emit));
+      } else if (arch==llvm::Triple::riscv32 || arch==llvm::Triple::riscv64) {
+        if (use64b) {   /* 64bit version */
+        unsigned cfg = E->getArg(0)->EvaluateKnownConstInt(getContext()).getZExtValue();
+        llvm::InlineAsm *Emit = InlineAsm::get(FTy, "csrwi swaracc, 0x" + utohexstr(cfg) + "; nop; csrr $0, swaracc", "=r", true);
+        return RValue::get(Builder.CreateCall(Emit));
+        } else {        /* 32bit version */
+        unsigned cfg = E->getArg(0)->EvaluateKnownConstInt(getContext()).getZExtValue();
+        llvm::InlineAsm *Emit = InlineAsm::get(FTy, "csrwi swaracc, 0x" + utohexstr(cfg) + "; nop; csrr $0, swaracc", "=r", true);
+        return RValue::get(Builder.CreateCall(Emit));
+        }
+      }
+    } else {
+      llvm::FunctionType *FTy = llvm::FunctionType::get( ConvertType(E->getType()), 
+                                        {ConvertType(E->getArg(0)->getType())}, false);
+      if (arch==llvm::Triple::sparc) {
+        llvm::Value *R = EmitScalarExpr(E->getArg(0));
+        llvm::InlineAsm *Emit = InlineAsm::get(FTy, "wr $1, %asr23; nop; rd %asr23, $0", "=r,r", true);
+        return RValue::get(Builder.CreateCall(Emit, {R}));
+      } else if (arch==llvm::Triple::riscv32 || arch==llvm::Triple::riscv64) {
+        if (use64b) {   /* 64bit version */
+        llvm::Value *R = EmitScalarExpr(E->getArg(0));
+        llvm::InlineAsm *Emit = InlineAsm::get(FTy, "csrw swaracc, $1; nop; csrr $0, swaracc", "=r,r", true);
+        return RValue::get(Builder.CreateCall(Emit, {R}));
+        } else {        /* 32bit version */
+        llvm::Value *R = EmitScalarExpr(E->getArg(0));
+        llvm::InlineAsm *Emit = InlineAsm::get(FTy, "csrw swaracc, $1; nop; csrr $0, swaracc", "=r,r", true);
+        return RValue::get(Builder.CreateCall(Emit, {R}));
+        }
+      }
+    }
+    return RValue::get(nullptr);
+  }
+  case Builtin::BI__builtin_swar:
+  {
+    llvm::FunctionType *FTy = llvm::FunctionType::get(
+                            ConvertType(E->getType()), 
+                            { ConvertType(E->getArg(0)->getType()), 
+                              ConvertType(E->getArg(1)->getType())}, false);
+    llvm::Triple::ArchType arch = CGM.getTriple().getArch();
+    bool use64b = (((BuiltinIDIfNoAsmLabel==Builtin::BI__builtin_swar) && 
+                    (arch==llvm::Triple::riscv64)) );
+    if (arch==llvm::Triple::sparc) {
+      llvm::Value *X = EmitScalarExpr(E->getArg(0));
+      llvm::Value *Y = EmitScalarExpr(E->getArg(1));
+      llvm::InlineAsm *Emit = InlineAsm::get(FTy, "swar $1,$2,$0", "=r,r,r", true); /* hasSideEffect =false */
+      return RValue::get(Builder.CreateCall(Emit,{X,Y}));
+    } else if (arch==llvm::Triple::riscv32 || arch==llvm::Triple::riscv64) {
+      if (use64b) {   /* 64bit version */
+        int widthArg0 = CGM.getContext().getTypeInfo(E->getArg(0)->getType()).Width;
+        int widthArg1 = CGM.getContext().getTypeInfo(E->getArg(1)->getType()).Width;
+        if (widthArg0!=widthArg1) { /* BitWidth of both arguments shuld be the same */
+          fprintf(stderr,"E: SWAR op for arguments with incompatible basic types is not allowed.");
+          return RValue::get(nullptr);
+        }
+      llvm::Value *X = EmitScalarExpr(E->getArg(0));
+      llvm::Value *Y = EmitScalarExpr(E->getArg(1));
+      llvm::InlineAsm *Emit = InlineAsm::get(FTy, "swar $0,$1,$2", "=r,r,r", true); /* hasSideEffect =false */
+      return RValue::get(Builder.CreateCall(Emit,{X,Y}));
+      } else {      /* 32bit version */
+      llvm::Value *X = EmitScalarExpr(E->getArg(0));
+      llvm::Value *Y = EmitScalarExpr(E->getArg(1));
+      llvm::InlineAsm *Emit = InlineAsm::get(FTy, "swar $0,$1,$2", "=r,r,r", true); /* hasSideEffect =false */
+      return RValue::get(Builder.CreateCall(Emit,{X,Y}));
+      }
+    }
+    return RValue::get(nullptr);
+  }
+  case Builtin::BI__builtin_swarcc:
+  {
+    llvm::Triple::ArchType arch = CGM.getTriple().getArch();
+    if (arch==llvm::Triple::sparc) {
+      llvm::FunctionType *FTy = llvm::FunctionType::get(
+                            ConvertType(E->getType()), 
+                            { ConvertType(E->getArg(0)->getType()), 
+                              ConvertType(E->getArg(1)->getType())}, false);
+      llvm::Value *X = EmitScalarExpr(E->getArg(0));
+      llvm::Value *Y = EmitScalarExpr(E->getArg(1));
+      llvm::InlineAsm *Emit = InlineAsm::get(FTy, "swarcc $1,$2,$0", "=r,r,r", true); /* hasSideEffect =false */
+      return RValue::get(Builder.CreateCall(Emit,{X,Y}));
+    }
+    return RValue::get(nullptr);
+  }
+
   }
 
   // If this is an alias for a lib function (e.g. __builtin_sin), emit
diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp
index 47a4ed35be85..17d59c6a8c28 100644
--- a/clang/lib/CodeGen/CGCall.cpp
+++ b/clang/lib/CodeGen/CGCall.cpp
@@ -1818,6 +1818,18 @@ void CodeGenModule::getDefaultFunctionAttributes(StringRef Name,
       FuncAttrs.addAttribute("unsafe-fp-math", "true");
     if (CodeGenOpts.SoftFloat)
       FuncAttrs.addAttribute("use-soft-float", "true");
+
+    FuncAttrs.addAttribute("soft-fops-half",
+                           llvm::utostr(CodeGenOpts.SoftFopsHalf));
+    FuncAttrs.addAttribute("soft-fops-single",
+                           llvm::utostr(CodeGenOpts.SoftFopsSingle));
+    FuncAttrs.addAttribute("soft-fops-double",
+                           llvm::utostr(CodeGenOpts.SoftFopsDouble));
+    FuncAttrs.addAttribute("enable-packedhalf",
+                           llvm::toStringRef(CodeGenOpts.EnabledPackedHalf));
+    FuncAttrs.addAttribute("enable-packedsingle",
+                           llvm::toStringRef(CodeGenOpts.EnabledPackedSingle));
+
     FuncAttrs.addAttribute("stack-protector-buffer-size",
                            llvm::utostr(CodeGenOpts.SSPBufferSize));
     if (LangOpts.NoSignedZero)
diff --git a/clang/lib/CodeGen/CGDebugInfo.cpp b/clang/lib/CodeGen/CGDebugInfo.cpp
index 81c910f40bf8..8b81fb89712f 100644
--- a/clang/lib/CodeGen/CGDebugInfo.cpp
+++ b/clang/lib/CodeGen/CGDebugInfo.cpp
@@ -3029,6 +3029,26 @@ llvm::DIType *CGDebugInfo::CreateType(const PipeType *Ty, llvm::DIFile *U) {
   return getOrCreateType(Ty->getElementType(), U);
 }
 
+llvm::DIType *CGDebugInfo::CreateType(const SubwordType *Ty, llvm::DIFile *Unit) {
+  llvm::DIType *BasicTy = getOrCreateType(Ty->getBasicType(), Unit);
+  int64_t ECount = Ty->getPacking();
+  int64_t ESize = Ty->getBitWidth();
+
+  llvm::Metadata *Subscript;
+  QualType QTy(Ty, 0);
+  auto SizeExpr = SizeExprCache.find(QTy);
+  if (SizeExpr != SizeExprCache.end())
+    Subscript = DBuilder.getOrCreateSubrange(0, SizeExpr->getSecond());
+  else
+    Subscript = DBuilder.getOrCreateSubrange(0, ECount);
+  llvm::DINodeArray SubscriptArray = DBuilder.getOrCreateArray(Subscript);
+
+  uint64_t Size = CGM.getContext().getTypeSize(Ty);
+  auto Align = getTypeAlignIfRequired(Ty, CGM.getContext());
+
+  return DBuilder.createSubwordType(ESize, ECount, BasicTy, SubscriptArray);
+}
+
 llvm::DIType *CGDebugInfo::CreateEnumType(const EnumType *Ty) {
   const EnumDecl *ED = Ty->getDecl();
 
@@ -3339,6 +3359,9 @@ llvm::DIType *CGDebugInfo::CreateTypeNode(QualType Ty, llvm::DIFile *Unit) {
   case Type::TemplateSpecialization:
     return CreateType(cast<TemplateSpecializationType>(Ty), Unit);
 
+  case Type::Subword:
+    return CreateType(cast<SubwordType>(Ty), Unit);
+
   case Type::Auto:
   case Type::Attributed:
   case Type::Adjusted:
diff --git a/clang/lib/CodeGen/CGDebugInfo.h b/clang/lib/CodeGen/CGDebugInfo.h
index b01165f85a6c..20eba4cec7f4 100644
--- a/clang/lib/CodeGen/CGDebugInfo.h
+++ b/clang/lib/CodeGen/CGDebugInfo.h
@@ -208,6 +208,9 @@ class CGDebugInfo {
   llvm::DIType *CreateType(const MemberPointerType *Ty, llvm::DIFile *F);
   llvm::DIType *CreateType(const AtomicType *Ty, llvm::DIFile *F);
   llvm::DIType *CreateType(const PipeType *Ty, llvm::DIFile *F);
+
+  llvm::DIType *CreateType(const SubwordType *Ty, llvm::DIFile *F);
+
   /// Get enumeration type.
   llvm::DIType *CreateEnumType(const EnumType *Ty);
   llvm::DIType *CreateTypeDefinition(const EnumType *Ty);
diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp
index bf514aab8851..6e571049b248 100644
--- a/clang/lib/CodeGen/CGExpr.cpp
+++ b/clang/lib/CodeGen/CGExpr.cpp
@@ -3760,6 +3760,14 @@ LValue CodeGenFunction::EmitArraySubscriptExpr(const ArraySubscriptExpr *E,
                           CGM.getTBAAInfoForSubobject(LV, EltType));
   }
 
+  if (E->getBase()->getType()->isSubwordType()) {
+    LValue LHS = EmitLValue(E->getBase());
+    auto *Idx = EmitIdxAfterBase(false); /* ??? Promote */
+    assert(LHS.isSimple() && "Can only subscript lvalue subword here!");
+    return LValue::MakeSubwordElt(LHS.getAddress(*this), Idx, E->getBase()->getType(),
+                                 LHS.getBaseInfo(), TBAAAccessInfo());
+  }
+
   LValueBaseInfo EltBaseInfo;
   TBAAAccessInfo EltTBAAInfo;
   Address Addr = Address::invalid();
diff --git a/clang/lib/CodeGen/CGExprScalar.cpp b/clang/lib/CodeGen/CGExprScalar.cpp
index 418f23bd1a97..c62a15885f89 100644
--- a/clang/lib/CodeGen/CGExprScalar.cpp
+++ b/clang/lib/CodeGen/CGExprScalar.cpp
@@ -1359,6 +1359,21 @@ Value *ScalarExprEmitter::EmitScalarConversion(Value *Src, QualType SrcType,
     return Builder.CreatePtrToInt(Src, DstTy, "conv");
   }
 
+  if (DstType->isSubwordType() && SrcType->isIntegerType()) {
+    ASTContext &Ctx = CGF.getContext();
+    unsigned src_sz = Ctx.getTypeSize(SrcType);
+    unsigned dst_sz = Ctx.getTypeSize(DstType->castAs<SubwordType>()->getBasicType());
+    //if (src_sz!=dst_sz) fprintf(stderr,"ConvertIntToSubword: different sizes between integer constant and the output subword type.\n");
+    llvm::Type *basTy = CGF.CGM.getTypes().ConvertType(DstType->castAs<SubwordType>()->getBasicType());
+    if (dst_sz<src_sz) {
+      Src = Builder.CreateTrunc(Src, basTy);
+    } else if (dst_sz>src_sz) {
+      Src = Builder.CreateZExtOrBitCast(Src, basTy);
+    }
+      
+    return Builder.CreateBitCast(Src, DstTy, "conv");
+  }
+
   // A scalar can be splatted to an extended vector of the same element type
   if (DstType->isExtVectorType() && !SrcType->isVectorType()) {
     // Sema should add casts to make sure that the source expression's type is
@@ -1819,6 +1834,12 @@ Value *ScalarExprEmitter::VisitInitListExpr(InitListExpr *E) {
     return Visit(E->getInit(0));
   }
 
+  if (isa<llvm::SubwordVectorType>(VType)) { /* initialize subword from list of element values */
+    unsigned ResElts = cast<llvm::SubwordVectorType>(VType)->getNumElements();
+    /* TODO: !!! use all parts of the list */
+    return Visit(E->getInit(0));
+  }
+
   unsigned ResElts = cast<llvm::FixedVectorType>(VType)->getNumElements();
 
   // Loop over initializers collecting the Value for each, and remembering
@@ -2929,6 +2950,28 @@ ScalarExprEmitter::VisitUnaryExprOrTypeTraitExpr(
 
       return size;
     }
+  } else if (E->getKind() == UETT_SizeOfSwar) { /* TODO: change to sizeofswar */
+    if (const VariableArrayType *VAT =
+          CGF.getContext().getAsVariableArrayType(TypeToSize)) {
+      if (E->isArgumentType()) {
+        // sizeof(type) - make sure to emit the VLA size.
+        CGF.EmitVariablyModifiedType(TypeToSize);
+      } else {
+        // C99 6.5.3.4p2: If the argument is an expression of type
+        // VLA, it is evaluated.
+        CGF.EmitIgnoredExpr(E->getArgumentExpr());
+      }
+
+      auto VlaSize = CGF.getVLASize(VAT);
+      llvm::Value *size = VlaSize.NumElts;
+
+      // Scale the number of non-VLA elements by the non-VLA element size.
+      CharUnits eltSize = CGF.getContext().getTypeSizeInChars(VlaSize.Type);
+      if (!eltSize.isOne())
+        size = CGF.Builder.CreateNUWMul(CGF.CGM.getSize(eltSize), size);
+
+      return size;
+    }
   } else if (E->getKind() == UETT_OpenMPRequiredSimdAlign) {
     auto Alignment =
         CGF.getContext()
@@ -4022,6 +4065,13 @@ Value *ScalarExprEmitter::EmitCompare(const BinaryOperator *E,
     Value *RHS = CGF.EmitScalarExpr(E->getRHS());
     Result = CGF.CGM.getCXXABI().EmitMemberPointerComparison(
                    CGF, LHS, RHS, MPT, E->getOpcode() == BO_NE);
+  } else if (LHSTy->isSubwordType() && RHSTy->isSubwordType()) {
+    BinOpInfo BOInfo = EmitBinOps(E);
+    Value *LHS = BOInfo.LHS;
+    Value *RHS = BOInfo.RHS;
+    //Result =
+    return Builder.CreateICmp(UICmpOpc, LHS, RHS, "cmp");
+
   } else if (!LHSTy->isAnyComplexType() && !RHSTy->isAnyComplexType()) {
     BinOpInfo BOInfo = EmitBinOps(E);
     Value *LHS = BOInfo.LHS;
@@ -4030,6 +4080,10 @@ Value *ScalarExprEmitter::EmitCompare(const BinaryOperator *E,
     // If AltiVec, the comparison results in a numeric type, so we use
     // intrinsics comparing vectors and giving 0 or 1 as a result
     if (LHSTy->isVectorType() && !E->getType()->isVectorType()) {
+      if (LHS->getType()->isFPOrFPVectorTy() && E->getType()->isIntegerType()) {
+        return Builder.CreateFCmp(FCmpOpc, LHS, RHS, "cmp");
+      }
+
       // constants for mapping CR6 register bits to predicate result
       enum { CR6_EQ=0, CR6_EQ_REV, CR6_LT, CR6_LT_REV } CR6;
 
diff --git a/clang/lib/CodeGen/CGValue.h b/clang/lib/CodeGen/CGValue.h
index 4b39a0520833..6120be1928d1 100644
--- a/clang/lib/CodeGen/CGValue.h
+++ b/clang/lib/CodeGen/CGValue.h
@@ -423,6 +423,18 @@ public:
     return R;
   }
 
+  static LValue MakeSubwordElt(Address swAddress, llvm::Value *Idx,
+                                QualType type, LValueBaseInfo BaseInfo,
+                                TBAAAccessInfo TBAAInfo) {
+    LValue R;
+    R.LVType = VectorElt;
+    R.V = swAddress.getPointer();
+    R.VectorIdx = Idx;
+    R.Initialize(type, type.getQualifiers(), swAddress.getAlignment(),
+                  BaseInfo, TBAAInfo);
+    return R;
+  }
+
   /// Create a new object to represent a bit-field access.
   ///
   /// \param Addr - The base address of the bit-field sequence this
diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp b/clang/lib/CodeGen/CodeGenFunction.cpp
index a2384456ea94..7d65f499ee7f 100644
--- a/clang/lib/CodeGen/CodeGenFunction.cpp
+++ b/clang/lib/CodeGen/CodeGenFunction.cpp
@@ -254,6 +254,7 @@ TypeEvaluationKind CodeGenFunction::getEvaluationKind(QualType type) {
     case Type::Enum:
     case Type::ObjCObjectPointer:
     case Type::Pipe:
+    case Type::Subword:
     case Type::ExtInt:
       return TEK_Scalar;
 
@@ -2162,6 +2163,9 @@ void CodeGenFunction::EmitVariablyModifiedType(QualType type) {
     case Type::ExtInt:
       llvm_unreachable("type class is never variably-modified!");
 
+    case Type::Subword:
+      llvm_unreachable("CodeGenFunction::EmitVariablyModifiedType - Subword type class is never variably-modified!");
+
     case Type::Adjusted:
       type = cast<AdjustedType>(ty)->getAdjustedType();
       break;
diff --git a/clang/lib/CodeGen/CodeGenTypes.cpp b/clang/lib/CodeGen/CodeGenTypes.cpp
index 9cb42941cb96..e66bdae222b4 100644
--- a/clang/lib/CodeGen/CodeGenTypes.cpp
+++ b/clang/lib/CodeGen/CodeGenTypes.cpp
@@ -702,6 +702,23 @@ llvm::Type *CodeGenTypes::ConvertType(QualType T) {
                                    MT->getNumRows() * MT->getNumColumns());
     break;
   }
+
+  // convert clang Subword type to llvm::VectorType (with enabled subword flag)
+  case Type::Subword: {
+    const SubwordType *SWT = cast<SubwordType>(Ty);
+    if (!SWT->getBasicType()->isIntegerType()) {
+      llvm_unreachable("Unsupported basic type of subword type!");
+    }
+    unsigned pck = SWT->getPacking();
+    bool sign = SWT->getBasicType()->isSignedIntegerType();
+    llvm::Type *bt = llvm::IntegerType::get(getLLVMContext(), 
+                        getContext().getIntWidth(SWT->getBasicType()));
+    llvm::Type *et = llvm::IntegerType::get(getLLVMContext(),
+                      static_cast<unsigned>(SWT->getBitWidth()));
+    ResultType = llvm::SubwordVectorType::get(et, pck, bt, pck, sign); /* TODO: set correctly NumElms */
+    break;
+  }
+
   case Type::FunctionNoProto:
   case Type::FunctionProto:
     ResultType = ConvertFunctionTypeInternal(T);
diff --git a/clang/lib/CodeGen/ItaniumCXXABI.cpp b/clang/lib/CodeGen/ItaniumCXXABI.cpp
index d3dc0e6212b8..b469059dc9a4 100644
--- a/clang/lib/CodeGen/ItaniumCXXABI.cpp
+++ b/clang/lib/CodeGen/ItaniumCXXABI.cpp
@@ -3533,6 +3533,9 @@ void ItaniumRTTIBuilder::BuildVTablePointer(const Type *Ty) {
     VTableName = "_ZTVN10__cxxabiv123__fundamental_type_infoE";
     break;
 
+  case Type::Subword:
+    llvm_unreachable("Subword type is not supported in the ItaniumCXXABI");
+
   case Type::ConstantArray:
   case Type::IncompleteArray:
   case Type::VariableArray:
@@ -3803,6 +3806,9 @@ llvm::Constant *ItaniumRTTIBuilder::BuildTypeInfo(
     // abi::__array_type_info adds no data members to std::type_info.
     break;
 
+  case Type::Subword:
+    llvm_unreachable("Subword type shouldn't get here (ItaniumCXXABI)");
+
   case Type::FunctionNoProto:
   case Type::FunctionProto:
     // Itanium C++ ABI 2.9.5p5:
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 5c323cb6ea23..4603b6a497b0 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -293,7 +293,8 @@ phases::ID Driver::getFinalPhase(const DerivedArgList &DAL,
              (PhaseArg = DAL.getLastArg(options::OPT_rewrite_legacy_objc)) ||
              (PhaseArg = DAL.getLastArg(options::OPT__migrate)) ||
              (PhaseArg = DAL.getLastArg(options::OPT__analyze)) ||
-             (PhaseArg = DAL.getLastArg(options::OPT_emit_ast))) {
+             (PhaseArg = DAL.getLastArg(options::OPT_emit_ast)) ||
+             (PhaseArg = DAL.getLastArg(options::OPT_print_sf_uid))) {
     FinalPhase = phases::Compile;
 
   // -S only runs up to the backend.
@@ -1783,7 +1784,8 @@ bool Driver::HandleImmediateArgs(const Compilation &C) {
 
   if (C.getArgs().hasArg(options::OPT_v) ||
       C.getArgs().hasArg(options::OPT__HASH_HASH_HASH) ||
-      C.getArgs().hasArg(options::OPT_print_supported_cpus)) {
+      C.getArgs().hasArg(options::OPT_print_supported_cpus) ||
+      C.getArgs().hasArg(options::OPT_print_sf_uid)) {
     PrintVersion(C, llvm::errs());
     SuppressMissingInputWarning = true;
   }
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index ade93d6881a7..df07a3ea370b 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -64,16 +64,28 @@ isExperimentalExtension(StringRef Ext) {
     return RISCVExtensionVersion{"0", "93"};
   if (Ext == "v" || Ext == "zvamo" || Ext == "zvlsseg")
     return RISCVExtensionVersion{"0", "10"};
-  if (Ext == "zfh")
-    return RISCVExtensionVersion{"0", "1"};
+// zfh should be a regular extension now
+  //if (Ext == "zfh")
+    //return RISCVExtensionVersion{"0", "1"};
+  return None;
+}
+
+// If the extension is supported with daiteq extensions, return the version of that
+// extension that the compiler currently supports.
+static Optional<RISCVExtensionVersion>
+isDaiteqExtension(StringRef Ext) {
+  if (Ext == "zfh" || Ext == "x-fph" || Ext == "x-fps" || Ext == "x-swar")
+    return RISCVExtensionVersion{"0", "10"};
   return None;
 }
 
 static bool isSupportedExtension(StringRef Ext) {
+  // LLVM supports daiteq extensions
+  if (isDaiteqExtension(Ext))
+    return true;
   // LLVM supports "z" extensions which are marked as experimental.
   if (isExperimentalExtension(Ext))
     return true;
-
   // LLVM does not support "sx", "s" nor "x" extensions.
   return false;
 }
@@ -113,6 +125,12 @@ static bool getExtensionVersion(const Driver &D, const ArgList &Args,
     return false;
   }
 
+  // If daiteq extension
+  if (auto DaiteqExtension = isDaiteqExtension(Ext)) {
+    // do not check version
+    return true;
+  }
+
   // If experimental extension, require use of current version number number
   if (auto ExperimentalExtension = isExperimentalExtension(Ext)) {
     if (!Args.hasArg(options::OPT_menable_experimental_extensions)) {
@@ -159,6 +177,16 @@ static bool getExtensionVersion(const Driver &D, const ArgList &Args,
   return false;
 }
 
+
+enum daiteq_fpu_extension_corrections {
+  FPU_EXT_F     = (1<<0),
+  FPU_EXT_D     = (1<<1),
+  FPU_EXT_ZFH   = (1<<2),
+  FPU_EXT_XFPS  = (1<<3),
+  FPU_EXT_XFPH  = (1<<4),
+  FPU_EXT_DAITEQ = FPU_EXT_F | FPU_EXT_D | FPU_EXT_ZFH | FPU_EXT_XFPS | FPU_EXT_XFPH,
+};
+
 // Handle other types of extensions other than the standard
 // general purpose and standard user-level extensions.
 // Parse the ISA string containing non-standard user-level
@@ -171,7 +199,8 @@ static bool getExtensionVersion(const Driver &D, const ArgList &Args,
 static void getExtensionFeatures(const Driver &D,
                                  const ArgList &Args,
                                  std::vector<StringRef> &Features,
-                                 StringRef &MArch, StringRef &Exts) {
+                                 StringRef &MArch, StringRef &Exts,
+                                 int *fpu_added) {
   if (Exts.empty())
     return;
 
@@ -267,7 +296,20 @@ static void getExtensionFeatures(const Driver &D,
       Features.push_back("+experimental-zvamo");
     } else if (isExperimentalExtension(Ext))
       Features.push_back(Args.MakeArgString("+experimental-" + Ext));
-    else
+    else if (isDaiteqExtension(Ext)) {
+      // check if extension is allowed or disabled with OPT_daiteq_fpu_type
+      if (Ext=="zfh") {
+        Features.push_back(Args.MakeArgString("+" + Ext));
+        *fpu_added |= FPU_EXT_ZFH;
+      } else if (Ext=="x-fph") {
+        Features.push_back(Args.MakeArgString("+" + Ext));
+        *fpu_added |= FPU_EXT_XFPH;
+      } else if (Ext=="x-fps") {
+        Features.push_back(Args.MakeArgString("+" + Ext));
+        *fpu_added |= FPU_EXT_XFPS;
+      } else
+        Features.push_back(Args.MakeArgString("+" + Ext));
+    } else
       Features.push_back(Args.MakeArgString("+" + Ext));
   }
 }
@@ -276,6 +318,39 @@ static void getExtensionFeatures(const Driver &D,
 static bool getArchFeatures(const Driver &D, StringRef MArch,
                             std::vector<StringRef> &Features,
                             const ArgList &Args) {
+  /* check enabled features if daiteq-fpu-type is used */
+  int fpu_add = -1;
+  int fpu_added = 0;
+  if (Arg *A = Args.getLastArg(options::OPT_daiteq_fpu_type)) {
+    if (A->getNumValues()==1) {
+      StringRef fpu = A->getValue(0);
+      if (fpu=="daifpu_divsqrt" ||  fpu=="daifpu_divonly" || fpu=="daifpu_none" ||
+          fpu=="daifpu_dual_dpsp_divsqrt" || fpu=="daifpu_dual_dpsp_divonly" ||
+          fpu=="daifpu_dual_dpsp_none" || fpu=="daifpu_dp_divsqrt" ||
+          fpu=="daifpu_dp_divonly" || fpu=="daifpu_dp_none") {
+        fpu_add = FPU_EXT_F | FPU_EXT_D;
+      } else if (fpu=="daifpu_dual_sphp_divsqrt" || 
+                 fpu=="daifpu_dual_sphp_divonly" ||
+                 fpu=="daifpu_dual_sphp_none") {
+        fpu_add = FPU_EXT_F | FPU_EXT_ZFH;
+      } else if (fpu=="daifpu_sp_divsqrt" || fpu=="daifpu_sp_divonly" ||
+                 fpu=="daifpu_sp_none") {
+        fpu_add = FPU_EXT_F;
+      } else if (fpu=="daifpu_hp_divsqrt" || fpu=="daifpu_hp_divonly" ||
+                 fpu=="daifpu_hp_none") {
+        fpu_add = FPU_EXT_ZFH;
+      } else if (fpu=="daifpu_psp_divsqrt" || fpu=="daifpu_psp_divonly" ||
+                 fpu=="daifpu_psp_none") {
+        fpu_add = FPU_EXT_F | FPU_EXT_XFPS;
+      } else if (fpu=="daifpu_php_divsqrt" || fpu=="daifpu_php_divonly" || 
+                 fpu=="daifpu_php_none") {
+        fpu_add = FPU_EXT_ZFH | FPU_EXT_XFPH;
+      } else if (fpu == "none") {
+        fpu_add = 0;
+      }
+    }
+  }
+
   // RISC-V ISA strings must be lowercase.
   if (llvm::any_of(MArch, [](char c) { return isupper(c); })) {
     D.Diag(diag::err_drv_invalid_riscv_arch_name)
@@ -327,6 +402,7 @@ static bool getArchFeatures(const Driver &D, StringRef MArch,
     Features.push_back("+d");
     HasF = true;
     HasD = true;
+    fpu_added |= FPU_EXT_F | FPU_EXT_D;
     break;
   }
 
@@ -409,10 +485,12 @@ static bool getArchFeatures(const Driver &D, StringRef MArch,
     case 'f':
       Features.push_back("+f");
       HasF = true;
+      fpu_added |= FPU_EXT_F;
       break;
     case 'd':
       Features.push_back("+d");
       HasD = true;
+      fpu_added |= FPU_EXT_D;
       break;
     case 'c':
       Features.push_back("+c");
@@ -434,6 +512,8 @@ static bool getArchFeatures(const Driver &D, StringRef MArch,
       Features.push_back("+experimental-v");
       Features.push_back("+experimental-zvlsseg");
       break;
+    case 'z':
+      break;
     }
 
     // Consume full extension name and version, including any optional '_'
@@ -461,8 +541,24 @@ static bool getArchFeatures(const Driver &D, StringRef MArch,
   // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'.
 
   // Handle all other types of extensions.
-  getExtensionFeatures(D, Args, Features, MArch, OtherExts);
-
+  getExtensionFeatures(D, Args, Features, MArch, OtherExts, &fpu_added);
+
+  // check if all necessary FPU extensions are enabled for daiteq-fpu-type
+  if (fpu_add>=0) {
+    // in fpu_add are required extensions and in fpu_added are really used extensions
+    int missing = (fpu_add & ~fpu_added) & FPU_EXT_DAITEQ;
+    if (missing) {
+      std::string mext("used 'daiteq-fpu-type' requires also extension:");
+      if (missing & FPU_EXT_F) mext += " f";
+      if (missing & FPU_EXT_D) mext += " d";
+      if (missing & FPU_EXT_ZFH) mext += " zfh";
+      if (missing & FPU_EXT_XFPH) mext += " x-fph";
+      if (missing & FPU_EXT_XFPS) mext += " x-fps";
+      D.Diag(diag::err_drv_invalid_riscv_arch_name)
+        << MArch << mext;
+      return false;
+    }
+  }
   return true;
 }
 
@@ -574,10 +670,17 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
   handleTargetFeaturesGroup(Args, Features, options::OPT_m_riscv_Features_Group);
 }
 
+enum daiteq_fpu_abi {
+  FPU_ABI_INT   = 1,
+  FPU_ABI_FLT   = 2,
+  FPU_ABI_DBL   = 4,
+};
+
 StringRef riscv::getRISCVABI(const ArgList &Args, const llvm::Triple &Triple) {
   assert((Triple.getArch() == llvm::Triple::riscv32 ||
           Triple.getArch() == llvm::Triple::riscv64) &&
          "Unexpected triple");
+  const char *abiname;
 
   // GCC's logic around choosing a default `-mabi=` is complex. If GCC is not
   // configured using `--with-abi=`, then the logic for the default choice is
@@ -599,53 +702,141 @@ StringRef riscv::getRISCVABI(const ArgList &Args, const llvm::Triple &Triple) {
   // 2. A default based on the architecture as determined by getRISCVArch
   // 3. Choose a default based on the triple
 
-  // 1. If `-mabi=` is specified, use it.
-  if (const Arg *A = Args.getLastArg(options::OPT_mabi_EQ))
-    return A->getValue();
+  do {
+    // 1. If `-mabi=` is specified, use it.
+    if (const Arg *A = Args.getLastArg(options::OPT_mabi_EQ)) {
+      abiname = A->getValue();
+      break;
+    }
 
-  // 2. Choose a default based on the target architecture.
-  //
-  // rv32g | rv32*d -> ilp32d
-  // rv32e -> ilp32e
-  // rv32* -> ilp32
-  // rv64g | rv64*d -> lp64d
-  // rv64* -> lp64
-  StringRef MArch = getRISCVArch(Args, Triple);
+    // 2. Choose a default based on the target architecture.
+    //
+    // rv32g | rv32*d -> ilp32d
+    // rv32e -> ilp32e
+    // rv32* -> ilp32
+    // rv64g | rv64*d -> lp64d
+    // rv64* -> lp64
+    StringRef MArch = getRISCVArch(Args, Triple);
+
+    if (MArch.startswith_insensitive("rv32")) {
+      // FIXME: parse `March` to find `D` extension properly
+      if (MArch.substr(4).contains_insensitive("d") ||
+          MArch.startswith_insensitive("rv32g")) {
+        abiname = "ilp32d";
+        break;
+      } else if (MArch.startswith_insensitive("rv32e")) {
+        abiname = "ilp32e";
+        break;
+      } else {
+        abiname = "ilp32";
+        break;
+      }
+    } else if (MArch.startswith_insensitive("rv64")) {
+      // FIXME: parse `March` to find `D` extension properly
+      if (MArch.substr(4).contains_insensitive("d") ||
+          MArch.startswith_insensitive("rv64g")) {
+        abiname = "lp64d";
+        break;
+      } else {
+        abiname = "lp64";
+        break;
+      }
+    }
 
-  if (MArch.startswith_insensitive("rv32")) {
-    // FIXME: parse `March` to find `D` extension properly
-    if (MArch.substr(4).contains_insensitive("d") ||
-        MArch.startswith_insensitive("rv32g"))
-      return "ilp32d";
-    else if (MArch.startswith_insensitive("rv32e"))
-      return "ilp32e";
-    else
-      return "ilp32";
-  } else if (MArch.startswith_insensitive("rv64")) {
-    // FIXME: parse `March` to find `D` extension properly
-    if (MArch.substr(4).contains_insensitive("d") ||
-        MArch.startswith_insensitive("rv64g"))
-      return "lp64d";
-    else
-      return "lp64";
+    // 3. Choose a default based on the triple
+    //
+    // We deviate from GCC's defaults here:
+    // - On `riscv{XLEN}-unknown-elf` we use the integer calling convention only.
+    // - On all other OSs we use the double floating point calling convention.
+    if (Triple.getArch() == llvm::Triple::riscv32) {
+      if (Triple.getOS() == llvm::Triple::UnknownOS) {
+        abiname = "ilp32";
+        break;
+      } else {
+        abiname = "ilp32d";
+        break;
+      }
+    } else {
+      if (Triple.getOS() == llvm::Triple::UnknownOS) {
+        abiname = "lp64";
+        break;
+      } else {
+        abiname = "lp64d";
+        break;
+      }
+    }
+  } while(0);
+
+// check if ABI is compliant with daiteq-fpu-type ... TODO: move it to a better place
+  if (Arg *A =Args.getLastArg(options::OPT_daiteq_fpu_type)) {
+    if (A->getNumValues()==1) {
+      int fpu_abi = 0;
+      StringRef fpu = A->getValue(0);
+      if (fpu=="daifpu_divsqrt" ||  fpu=="daifpu_divonly" || fpu=="daifpu_none" ||
+          fpu=="daifpu_dual_dpsp_divsqrt" || fpu=="daifpu_dual_dpsp_divonly" ||
+          fpu=="daifpu_dual_dpsp_none") {
+        fpu_abi = FPU_ABI_INT | FPU_ABI_FLT | FPU_ABI_DBL;
+      } else if (fpu=="daifpu_dp_divsqrt" || 
+                 fpu=="daifpu_dp_divonly" || 
+                 fpu=="daifpu_dp_none") {
+        fpu_abi = FPU_ABI_INT | FPU_ABI_DBL;
+      } else if (fpu=="daifpu_dual_sphp_divsqrt" || 
+                 fpu=="daifpu_dual_sphp_divonly" ||
+                 fpu=="daifpu_dual_sphp_none") {
+        fpu_abi = FPU_ABI_INT | FPU_ABI_FLT;
+      } else if (fpu=="daifpu_sp_divsqrt" || 
+                 fpu=="daifpu_sp_divonly" ||
+                 fpu=="daifpu_sp_none") {
+        fpu_abi = FPU_ABI_INT | FPU_ABI_FLT;
+      } else if (fpu=="daifpu_hp_divsqrt" || 
+                 fpu=="daifpu_hp_divonly" ||
+                 fpu=="daifpu_hp_none") {
+        fpu_abi = FPU_ABI_INT;
+      } else if (fpu=="daifpu_psp_divsqrt" || fpu=="daifpu_psp_divonly" ||
+                 fpu=="daifpu_psp_none") {
+        fpu_abi = FPU_ABI_INT | FPU_ABI_FLT;
+      } else if (fpu=="daifpu_php_divsqrt" || fpu=="daifpu_php_divonly" || 
+                 fpu=="daifpu_php_none") {
+        fpu_abi = FPU_ABI_INT;
+      } else if (fpu == "none") {
+        fpu_abi = FPU_ABI_INT;
+      }
+      char abifp = abiname[strlen(abiname)-1];
+      const char *useabi, *newabi;
+      if (abifp=='d' && !(fpu_abi & FPU_ABI_DBL)) {
+        if (fpu_abi & FPU_ABI_FLT) {
+          useabi = "single";
+          if (Triple.getArch() == llvm::Triple::riscv32) {
+            newabi = "ilp32f";
+          } else {
+            newabi = "lp64f";
+          }
+        } else {
+          useabi = "integer";
+          if (Triple.getArch() == llvm::Triple::riscv32) {
+            newabi = "ilp32";
+          } else {
+            newabi = "lp64";
+          }
+        }
+        fprintf(stderr, "Error: Required daiteq-fpu-type cannot use double float ABI (%s), ABI is changed to %s.\n", abiname, newabi);
+        //D.Diag(diag::err_drv_invalid_mfloat_abi) << "required daiteq-fpu-type cannot use double float ABI, ABI is changed to " << useabi;
+        abiname = newabi;
+      }
+      if (abifp=='f' && !(fpu_abi & FPU_ABI_FLT)) {
+        if (Triple.getArch() == llvm::Triple::riscv32) {
+          newabi = "ilp32";
+        } else {
+          newabi = "lp64";
+        }
+        fprintf(stderr, "Error: Required daiteq-fpu-type cannot use float float ABI (%s), ABI is changed to %s.\n", abiname, newabi);
+        //D.Diag(diag::err_drv_invalid_mfloat_abi) << "required daiteq-fpu-type cannot use single float ABI, ABI is changed to integer";
+        abiname = newabi;
+      }
+    }
   }
 
-  // 3. Choose a default based on the triple
-  //
-  // We deviate from GCC's defaults here:
-  // - On `riscv{XLEN}-unknown-elf` we use the integer calling convention only.
-  // - On all other OSs we use the double floating point calling convention.
-  if (Triple.getArch() == llvm::Triple::riscv32) {
-    if (Triple.getOS() == llvm::Triple::UnknownOS)
-      return "ilp32";
-    else
-      return "ilp32d";
-  } else {
-    if (Triple.getOS() == llvm::Triple::UnknownOS)
-      return "lp64";
-    else
-      return "lp64d";
-  }
+  return abiname;
 }
 
 StringRef riscv::getRISCVArch(const llvm::opt::ArgList &Args,
diff --git a/clang/lib/Driver/ToolChains/Arch/Sparc.cpp b/clang/lib/Driver/ToolChains/Arch/Sparc.cpp
index 70ba8eb2a7d0..8aec244d27cd 100644
--- a/clang/lib/Driver/ToolChains/Arch/Sparc.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/Sparc.cpp
@@ -7,6 +7,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "Sparc.h"
+#include "ToolChains/CommonArgs.h"
 #include "clang/Driver/Driver.h"
 #include "clang/Driver/DriverDiagnostic.h"
 #include "clang/Driver/Options.h"
@@ -115,6 +116,8 @@ sparc::FloatABI sparc::getSparcFloatABI(const Driver &D,
 
 void sparc::getSparcTargetFeatures(const Driver &D, const ArgList &Args,
                                    std::vector<StringRef> &Features) {
+  handleTargetFeaturesGroup(Args, Features, options::OPT_m_sparc_Features_Group);
+
   sparc::FloatABI FloatABI = sparc::getSparcFloatABI(D, Args);
   if (FloatABI == sparc::FloatABI::Soft)
     Features.push_back("+soft-float");
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp
index 58ae08a3879c..58f2d2de68ea 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -2071,6 +2071,355 @@ static void SetRISCVSmallDataLimit(const ToolChain &TC, const ArgList &Args,
   CmdArgs.push_back(SmallDataLimit);
 }
 
+/** daiteq FPU extension - convertion from set of all arguments which influence FPU selection **/
+// Selection for partial soft-float
+static const struct SoftFopsTableStruct {
+  unsigned mask;
+  char     flag;
+} SoftFopsTable[] = {
+  {llvm::SoftFops::FPOP_ADD,'a'},{llvm::SoftFops::FPOP_SUB,'s'},{llvm::SoftFops::FPOP_MUL,'m'},{llvm::SoftFops::FPOP_DIV,'d'},
+  {llvm::SoftFops::FPOP_MULEX,'M'},{llvm::SoftFops::FPOP_SQRT,'S'},{llvm::SoftFops::FPOP_CMP,'c'},
+  {llvm::SoftFops::FPOP_CI2F,'f'},{llvm::SoftFops::FPOP_CF2I,'i'},{llvm::SoftFops::FPOP_CFUP,'h'},{llvm::SoftFops::FPOP_CFDN,'l'},
+  {llvm::SoftFops::FPOP_ABS,'A'},{llvm::SoftFops::FPOP_PACK,'p'},{llvm::SoftFops::FPOP_MOV,'C'},{llvm::SoftFops::FPOP_NEG,'n'},
+  {0,0}
+};
+unsigned getFopsMask(const std::string &desc)
+{
+  unsigned mask = 0;
+  int i =0;
+  while (SoftFopsTable[i].mask) {
+    if (desc.find(SoftFopsTable[i].flag)!=std::string::npos)
+      mask |= SoftFopsTable[i].mask;
+    i++;
+  }
+  return mask;
+}
+
+unsigned Clang::SelectFPUForDoubleFP(const ArgList &Args,
+                                     llvm::opt::ArgStringList &CmdArgs) const {
+  /* selection of double FP operations is set to all in soft-float (can be changed with RISCV architecture 'd' extension */
+  /* default: all dblFP ops are in software */
+  unsigned dblsf = -1;
+  // first try to find '+d' extension (in prepared CmdArgs) to select all dblFP ops as hard
+  // TODO: change it to searching in Args
+  unsigned echk = 0;
+  for (const auto *C : CmdArgs) {
+    if (echk==1) {
+      if (!strcmp(C,"+d")) {
+        dblsf = 0; // dblFP are in hardware
+        echk = 0;
+      }
+    } else if (!strcmp(C,"-target-feature")) {
+      echk=1;
+    } else {
+      echk = 0;
+    }
+  }
+
+  // then check each argument
+  for (const auto &A : Args) {
+    unsigned val;
+    unsigned argid = A->getOption().getID();
+    switch (argid) {
+/* double FP */
+      case options::OPT_msoft_float: // try to find 'soft-float' option
+        dblsf = -1; /* all in soft-float */
+        break;
+      case options::OPT_mhard_fp_double:
+        dblsf = 0; // all double FP ops are in a hardware
+        break;
+      case options::OPT_msoft_fp_double:
+        dblsf = -1; // all double FP ops are in software
+        break;
+      case options::OPT_msoft_fops_double:
+        val = getFopsMask(A->getValue()); // -msoft-fops-double=
+        dblsf |= val;
+        break;
+      case options::OPT_mhard_fops_double:
+        val = getFopsMask(A->getValue()); // -mhard-fops-double=
+        dblsf &= ~val;
+        break;
+
+      case options::OPT_daiteq_fpu_type:
+      { // the same selection is in clang/lib/Driver/ToolChains/Arch/Sparc.cpp
+        StringRef fpu = A->getValue();
+        if (fpu == "daifpu_divsqrt") {
+          dblsf = 0; // DP all in HW
+        } else if (fpu == "daifpu_divonly") { // DP,SP - SQRT in softfloat
+          dblsf = llvm::SoftFops::FPOP_SQRT; // DP all in HW, except sqrt
+        } else if (fpu == "daifpu_none") {
+          dblsf = llvm::SoftFops::FPOP_DIV | llvm::SoftFops::FPOP_SQRT; // DP all in HW, except div/sqrt
+        } else if (fpu == "daifpu_dual_dpsp_divsqrt") {
+          dblsf = 0; // DP all in HW
+        } else if (fpu == "daifpu_dual_dpsp_divonly") {
+          dblsf = llvm::SoftFops::FPOP_SQRT; // DP all in HW, except sqrt
+        } else if (fpu == "daifpu_dual_dpsp_none") {
+          dblsf = llvm::SoftFops::FPOP_DIV | llvm::SoftFops::FPOP_SQRT; // DP all in HW, except div/sqrt
+        } else if (fpu == "daifpu_dual_sphp_divsqrt") {
+          dblsf = -1; // DP all in softfloat
+        } else if (fpu == "daifpu_dual_sphp_divonly") {
+          dblsf = -1; // DP all in softfloat
+        } else if (fpu == "daifpu_dual_sphp_none") {
+          dblsf = -1; // DP all in softfloat
+        } else if (fpu == "daifpu_dp_divsqrt") {
+          dblsf = 0; // DP all in HW
+        } else if (fpu == "daifpu_dp_divonly") {
+          dblsf = llvm::SoftFops::FPOP_SQRT;  // DP all in HW, except sqrt
+        } else if (fpu == "daifpu_dp_none") {
+          dblsf = llvm::SoftFops::FPOP_DIV | llvm::SoftFops::FPOP_SQRT;  // DP all in HW, except div/sqrt
+        } else if (fpu == "daifpu_sp_divsqrt") {
+          dblsf = -1; // DP all in softfloat
+        } else if (fpu == "daifpu_sp_divonly") {
+          dblsf = -1; // DP all in softfloat
+        } else if (fpu == "daifpu_sp_none") {
+          dblsf = -1; // DP all in softfloat
+        } else if (fpu == "daifpu_hp_divsqrt") {
+          dblsf = -1; // DP all in softfloat
+        } else if (fpu == "daifpu_hp_divonly") {
+          dblsf = -1; // DP all in softfloat
+        } else if (fpu == "daifpu_hp_none") {
+          dblsf = -1; // DP all in softfloat
+        } else if (fpu == "daifpu_psp_divsqrt") {
+          dblsf = -1; // DP all in softfloat
+        } else if (fpu == "daifpu_psp_divonly") {
+          dblsf = -1; // DP all in softfloat
+        } else if (fpu == "daifpu_psp_none") {
+          dblsf = -1; // DP all in softfloat
+        } else if (fpu == "daifpu_php_divsqrt") {
+          dblsf = -1; // DP all in softfloat
+        } else if (fpu == "daifpu_php_divonly") {
+          dblsf = -1; // DP all in softfloat
+        } else if (fpu == "daifpu_php_none") {
+          dblsf = -1; // DP all in softfloat
+        } else if (fpu == "none") {
+          dblsf = -1;  // DP all in softfloat
+        } else {
+          const Driver &D = getToolChain().getDriver();
+          D.Diag(diag::err_drv_invalid_value) << A->getAsString(Args) << fpu;
+        }
+      }
+      break;
+    }
+  }
+  return dblsf;
+}
+
+unsigned Clang::SelectFPUForSingleFP(const ArgList &Args,
+                                     llvm::opt::ArgStringList &CmdArgs) const {
+  /* selection of single FP operations is set to all in soft-float (can be changed with RISCV architecture 'f' extension */
+  unsigned fltsf = -1;
+  // first try to find '+f' extension (in prepared CmdArgs) to select all singleFP ops as hard
+  // TODO: change it to searching in Args
+  unsigned echk = 0;
+  for (const auto *C : CmdArgs) {
+    if (echk==1) {
+      if (!strcmp(C,"+f")) {
+        fltsf = 0; // singleFP are in hardware
+        echk = 0;
+      }
+    } else if (!strcmp(C,"-target-feature")) {
+      echk=1;
+    } else {
+      echk = 0;
+    }
+  }
+
+  // all other arguments can be re-written with newer (order is relevant)
+  for (const auto &A : Args) {
+    unsigned val;
+    unsigned argid = A->getOption().getID();
+    switch (argid) {
+/* float FP */
+      case options::OPT_msoft_float: // try find 'soft-float' option
+        fltsf = -1; /* all in soft-float */
+        break;
+      case options::OPT_mhard_fp_single:
+        fltsf = 0; // all single FP ops are in a hardware
+        break;
+      case options::OPT_msoft_fp_single:
+        fltsf = -1; // all single FP ops are in software
+        break;
+      case options::OPT_msoft_fops_single:
+        val = getFopsMask(A->getValue()); // -msoft-fops-single=
+        fltsf |= val;
+        break;
+      case options::OPT_mhard_fops_single:
+        val = getFopsMask(A->getValue()); // -mhard-fops-single=
+        fltsf &= ~val;
+        break;
+
+      case options::OPT_daiteq_fpu_type:
+      { // the same selection is in clang/lib/Driver/ToolChains/Arch/Sparc.cpp
+        StringRef fpu = A->getValue();
+        if (fpu == "daifpu_divsqrt") {
+          fltsf = 0; // FP all in HW
+        } else if (fpu == "daifpu_divonly") { // DP,SP - SQRT in softfloat
+          fltsf = llvm::SoftFops::FPOP_SQRT; // SP all in HW, except sqrt
+        } else if (fpu == "daifpu_none") {
+          fltsf = llvm::SoftFops::FPOP_DIV | llvm::SoftFops::FPOP_SQRT; // SP all in HW, except div/sqrt
+        } else if (fpu == "daifpu_dual_dpsp_divsqrt") {
+          fltsf = 0; // SP all in HW
+        } else if (fpu == "daifpu_dual_dpsp_divonly") {
+          fltsf = llvm::SoftFops::FPOP_SQRT; // SP all in HW, except sqrt
+        } else if (fpu == "daifpu_dual_dpsp_none") {
+          fltsf = llvm::SoftFops::FPOP_DIV | llvm::SoftFops::FPOP_SQRT; // SP all in HW, except div/sqrt
+        } else if (fpu == "daifpu_dual_sphp_divsqrt") {
+          fltsf = 0; // SP all in HW
+        } else if (fpu == "daifpu_dual_sphp_divonly") {
+          fltsf = llvm::SoftFops::FPOP_SQRT;  // SP all in HW, except sqrt
+        } else if (fpu == "daifpu_dual_sphp_none") {
+          fltsf = llvm::SoftFops::FPOP_DIV | llvm::SoftFops::FPOP_SQRT;  // SP all in HW, except div/sqrt
+        } else if (fpu == "daifpu_dp_divsqrt") {
+          fltsf = -1; // SP all in softfloat
+        } else if (fpu == "daifpu_dp_divonly") {
+          fltsf = -1; // SP all in softfloat
+        } else if (fpu == "daifpu_dp_none") {
+          fltsf = -1; // SP all in softfloat
+        } else if (fpu == "daifpu_sp_divsqrt") {
+          fltsf = 0;  // SP all in HW
+        } else if (fpu == "daifpu_sp_divonly") {
+          fltsf = llvm::SoftFops::FPOP_SQRT;  // SP all in HW, except sqrt
+        } else if (fpu == "daifpu_sp_none") {
+          fltsf = llvm::SoftFops::FPOP_DIV | llvm::SoftFops::FPOP_SQRT;  // SP all in HW, except div/sqrt
+        } else if (fpu == "daifpu_hp_divsqrt") {
+          fltsf = -1;  // SP all in softfloat
+        } else if (fpu == "daifpu_hp_divonly") {
+          fltsf = -1;  // SP all in softfloat
+        } else if (fpu == "daifpu_hp_none") {
+          fltsf = -1;  // SP all in softfloat
+        } else if (fpu == "daifpu_psp_divsqrt") {
+          fltsf = 0;  // SP all in HW
+        } else if (fpu == "daifpu_psp_divonly") {
+          fltsf = llvm::SoftFops::FPOP_SQRT;  // SP all in HW, except sqrt
+        } else if (fpu == "daifpu_psp_none") {
+          fltsf = llvm::SoftFops::FPOP_DIV | llvm::SoftFops::FPOP_SQRT;  // SP all in HW, except div/sqrt
+        } else if (fpu == "daifpu_php_divsqrt") {
+          fltsf = -1;  // SP all in softfloat
+        } else if (fpu == "daifpu_php_divonly") {
+          fltsf = -1;  // SP all in softfloat
+        } else if (fpu == "daifpu_php_none") {
+          fltsf = -1;  // SP all in softfloat
+        } else if (fpu == "none") {
+          fltsf = -1;  // SP all in softfloat
+        } else {
+          const Driver &D = getToolChain().getDriver();
+          D.Diag(diag::err_drv_invalid_value) << A->getAsString(Args) << fpu;
+        }
+      }
+      break;
+    }
+  }
+  return fltsf;
+}
+
+unsigned Clang::SelectFPUForHalfFP(const ArgList &Args,
+                                   llvm::opt::ArgStringList &CmdArgs) const {
+  /* selection of half FP operations is set to all in soft-float (can be changed with RISCV architecture 'zhf' extension */
+  unsigned hlfsf = -1;
+  // first try to find '+zfh' extension (in prepared CmdArgs) to select all halfFP ops as hard
+  // TODO: change it to searching in Args
+  unsigned echk = 0;
+  for (const auto *C : CmdArgs) {
+    if (echk==1) {
+      if (!strcmp(C,"+zfh")) {
+        hlfsf = 0; // halfFP are in hardware
+        echk = 0;
+      }
+    } else if (!strcmp(C,"-target-feature")) {
+      echk=1;
+    } else {
+      echk = 0;
+    }
+  }
+
+  // all other arguments can be re-written with newer (order is relevant)
+  for (const auto &A : Args) {
+    unsigned val;
+    unsigned argid = A->getOption().getID();
+    switch (argid) {
+/* half FP */
+      case options::OPT_msoft_float:  // try find 'soft-float' option
+        hlfsf = -1; /* all in soft-float */
+        break;
+      case options::OPT_mhard_fp_half:
+        hlfsf = 0; // all half FP ops disabled
+        break;
+      case options::OPT_msoft_fp_half:
+        hlfsf = -1; // all half FP ops enabled
+        break;
+      case options::OPT_msoft_fops_half:
+        val = getFopsMask(A->getValue());
+        hlfsf |= val;
+        break;
+      case options::OPT_mhard_fops_half:
+        val = getFopsMask(A->getValue());
+        hlfsf &= ~val;
+        break;
+
+      case options::OPT_daiteq_fpu_type:
+        { // the same selection is in clang/lib/Driver/ToolChains/Arch/Sparc.cpp
+          StringRef fpu = A->getValue();
+          if (fpu == "daifpu_divsqrt") {
+            hlfsf = -1; // HP all in softfloat
+          } else if (fpu == "daifpu_divonly") { // DP,SP - SQRT in softfloat
+            hlfsf = -1; // HP all in softfloat
+          } else if (fpu == "daifpu_none") {
+            hlfsf = -1; // HP all in softfloat
+          } else if (fpu == "daifpu_dual_dpsp_divsqrt") {
+            hlfsf = -1; // HP all in softfloat
+          } else if (fpu == "daifpu_dual_dpsp_divonly") {
+            hlfsf = -1; // HP all in softfloat
+          } else if (fpu == "daifpu_dual_dpsp_none") {
+            hlfsf = -1; // HP all in softfloat
+          } else if (fpu == "daifpu_dual_sphp_divsqrt") {
+            hlfsf = 0;    // HP all in HW
+          } else if (fpu == "daifpu_dual_sphp_divonly") {
+            hlfsf = llvm::SoftFops::FPOP_SQRT;    // HP all in HW, except sqrt
+          } else if (fpu == "daifpu_dual_sphp_none") {
+            hlfsf = llvm::SoftFops::FPOP_DIV | llvm::SoftFops::FPOP_SQRT;    // HP all in HW, except div/sqrt
+          } else if (fpu == "daifpu_dp_divsqrt") {
+            hlfsf = -1; // HP all in softfloat
+          } else if (fpu == "daifpu_dp_divonly") {
+            hlfsf = -1; // HP all in softfloat
+          } else if (fpu == "daifpu_dp_none") {
+            hlfsf = -1; // HP all in softfloat
+          } else if (fpu == "daifpu_sp_divsqrt") {
+            hlfsf = -1;    // HP all in softfloat
+          } else if (fpu == "daifpu_sp_divonly") {
+            hlfsf = -1;    // HP all in softfloat
+          } else if (fpu == "daifpu_sp_none") {
+            hlfsf = -1;    // HP all in softfloat
+          } else if (fpu == "daifpu_hp_divsqrt") {
+            hlfsf = 0;    // HP all in HW
+          } else if (fpu == "daifpu_hp_divonly") {
+            hlfsf = llvm::SoftFops::FPOP_SQRT;    // HP all in HW, except sqrt
+          } else if (fpu == "daifpu_hp_none") {
+            hlfsf = llvm::SoftFops::FPOP_DIV | llvm::SoftFops::FPOP_SQRT;    // HP all in HW, except div/sqrt
+          } else if (fpu == "daifpu_psp_divsqrt") {
+            hlfsf = -1;    // HP all in softfloat
+          } else if (fpu == "daifpu_psp_divonly") {
+            hlfsf = -1;    // HP all in softfloat
+          } else if (fpu == "daifpu_psp_none") {
+            hlfsf = -1;    // HP all in softfloat
+          } else if (fpu == "daifpu_php_divsqrt") {
+            hlfsf = 0;    // HP all in HW
+          } else if (fpu == "daifpu_php_divonly") {
+            hlfsf = llvm::SoftFops::FPOP_SQRT;    // HP all in HW, except sqrt
+          } else if (fpu == "daifpu_php_none") {
+            hlfsf = llvm::SoftFops::FPOP_DIV | llvm::SoftFops::FPOP_SQRT;    // HP all in HW, except div/sqrt
+          } else if (fpu == "none") {
+            hlfsf = -1;    // HP all in softfloat
+          } else {
+            const Driver &D = getToolChain().getDriver();
+            D.Diag(diag::err_drv_invalid_value) << A->getAsString(Args) << fpu;
+          }
+        }
+        break;
+    }
+  }
+  return hlfsf;
+}
+
 void Clang::AddRISCVTargetArgs(const ArgList &Args,
                                ArgStringList &CmdArgs) const {
   const llvm::Triple &Triple = getToolChain().getTriple();
@@ -2094,6 +2443,27 @@ void Clang::AddRISCVTargetArgs(const ArgList &Args,
     CmdArgs.push_back("-tune-cpu");
     CmdArgs.push_back(Args.MakeArgString(TuneCPU));
   }
+  // analyse all options around selection of double FP operations
+  unsigned sfops = SelectFPUForDoubleFP(Args, CmdArgs);
+  CmdArgs.push_back(Args.MakeArgString("-msoft-double=" + StringRef(std::to_string(sfops))));
+  sfops = SelectFPUForSingleFP(Args, CmdArgs);
+  CmdArgs.push_back(Args.MakeArgString("-msoft-single=" + StringRef(std::to_string(sfops))));
+  sfops = SelectFPUForHalfFP(Args, CmdArgs);
+  CmdArgs.push_back(Args.MakeArgString("-msoft-half=" + StringRef(std::to_string(sfops))));
+
+  if (Args.hasArg(options::OPT_print_sf_uid)) {
+    CmdArgs.push_back("-print-sf-uid");
+  }
+
+  if (Args.hasArg(options::OPT_daiteq_swar_enable)) {
+    CmdArgs.push_back("-daiteq-swar-enable");
+  }
+
+  if (Args.hasArg(options::OPT_daiteq_swar_type)) {
+    StringRef dswar = Args.getLastArgValue(options::OPT_daiteq_swar_type);
+    CmdArgs.push_back(Args.MakeArgString("-daiteq-swar-force-config=" + dswar));
+  }
+
 }
 
 void Clang::AddSparcTargetArgs(const ArgList &Args,
@@ -2112,6 +2482,77 @@ void Clang::AddSparcTargetArgs(const ArgList &Args,
     CmdArgs.push_back("-mfloat-abi");
     CmdArgs.push_back("hard");
   }
+
+  if (Args.hasArg(options::OPT_msoft_fp_half)) {
+    CmdArgs.push_back("-msoft-fp-half");
+  }
+  if (Args.hasArg(options::OPT_msoft_fp_single)) {
+    CmdArgs.push_back("-msoft-fp-single");
+  }
+  if (Args.hasArg(options::OPT_msoft_fp_double)) {
+    CmdArgs.push_back("-msoft-fp-double");
+  }
+
+  if (Args.hasArg(options::OPT_mhard_fp_half)) {
+    CmdArgs.push_back("-mhard-fp-half");
+  }
+  if (Args.hasArg(options::OPT_mhard_fp_single)) {
+    CmdArgs.push_back("-mhard-fp-single");
+  }
+  if (Args.hasArg(options::OPT_mhard_fp_double)) {
+    CmdArgs.push_back("-mhard-fp-double");
+  }
+  // TODO: push soft-fops-half / soft-fops-single / soft-fops-double
+  if (Args.hasArg(options::OPT_msoft_fops_half)) {
+    StringRef fops = Args.getLastArgValue(options::OPT_msoft_fops_half);
+    CmdArgs.push_back(Args.MakeArgString("-msoft-fops-half=" + fops));
+  }
+  if (Args.hasArg(options::OPT_mhard_fops_half)) {
+    StringRef fops = Args.getLastArgValue(options::OPT_mhard_fops_half);
+    CmdArgs.push_back(Args.MakeArgString("-mhard-fops-half=" + fops));
+  }
+  if (Args.hasArg(options::OPT_msoft_fops_single)) {
+    StringRef fops = Args.getLastArgValue(options::OPT_msoft_fops_single);
+    CmdArgs.push_back(Args.MakeArgString("-msoft-fops-single=" + fops));
+  }
+  if (Args.hasArg(options::OPT_mhard_fops_single)) {
+    StringRef fops = Args.getLastArgValue(options::OPT_mhard_fops_single);
+    CmdArgs.push_back(Args.MakeArgString("-mhard-fops-single=" + fops));
+  }
+  if (Args.hasArg(options::OPT_msoft_fops_double)) {
+    StringRef fops = Args.getLastArgValue(options::OPT_msoft_fops_double);
+    CmdArgs.push_back(Args.MakeArgString("-msoft-fops-double=" + fops));
+  }
+  if (Args.hasArg(options::OPT_mhard_fops_double)) {
+    StringRef fops = Args.getLastArgValue(options::OPT_mhard_fops_double);
+    CmdArgs.push_back(Args.MakeArgString("-mhard-fops-double=" + fops));
+  }
+
+  if (Args.hasArg(options::OPT_menable_packedhalf)) {
+    CmdArgs.push_back("-menable-packedhalf");
+  }
+  if (Args.hasArg(options::OPT_menable_packedsingle)) {
+    CmdArgs.push_back("-menable-packedsingle");
+  }
+
+  if (Args.hasArg(options::OPT_daiteq_fpu_type)) {
+    StringRef dfpu = Args.getLastArgValue(options::OPT_daiteq_fpu_type);
+    CmdArgs.push_back(Args.MakeArgString("-daiteq-fpu-type=" + dfpu));
+  }
+
+  if (Args.hasArg(options::OPT_daiteq_swar_enable)) {
+    CmdArgs.push_back("-daiteq-swar-enable");
+  }
+
+  if (Args.hasArg(options::OPT_daiteq_swar_type)) {
+    StringRef dswar = Args.getLastArgValue(options::OPT_daiteq_swar_type);
+    CmdArgs.push_back(Args.MakeArgString("-daiteq-swar-force-config=" + dswar));
+  }
+
+  if (Args.hasArg(options::OPT_munaligned_packed_fp)) {
+    CmdArgs.push_back("-munaligned-packed-fp");
+  }
+
 }
 
 void Clang::AddSystemZTargetArgs(const ArgList &Args,
@@ -7380,6 +7821,74 @@ void ClangAs::AddRISCVTargetArgs(const ArgList &Args,
 
   CmdArgs.push_back("-target-abi");
   CmdArgs.push_back(ABIName.data());
+
+  if (Args.hasArg(options::OPT_msoft_fp_half)) {
+    CmdArgs.push_back("-msoft-fp-half");
+  }
+  if (Args.hasArg(options::OPT_msoft_fp_single)) {
+    CmdArgs.push_back("-msoft-fp-single");
+  }
+  if (Args.hasArg(options::OPT_msoft_fp_double)) {
+    CmdArgs.push_back("-msoft-fp-double");
+  }
+
+  if (Args.hasArg(options::OPT_mhard_fp_half)) {
+    CmdArgs.push_back("-mhard-fp-half");
+  }
+  if (Args.hasArg(options::OPT_mhard_fp_single)) {
+    CmdArgs.push_back("-mhard-fp-single");
+  }
+  if (Args.hasArg(options::OPT_mhard_fp_double)) {
+    CmdArgs.push_back("-mhard-fp-double");
+  }
+  // TODO: push soft-fops-half / soft-fops-single / soft-fops-double
+  if (Args.hasArg(options::OPT_msoft_fops_half)) {
+    StringRef fops = Args.getLastArgValue(options::OPT_msoft_fops_half);
+    CmdArgs.push_back(Args.MakeArgString("-msoft-fops-half=" + fops));
+  }
+  if (Args.hasArg(options::OPT_mhard_fops_half)) {
+    StringRef fops = Args.getLastArgValue(options::OPT_mhard_fops_half);
+    CmdArgs.push_back(Args.MakeArgString("-mhard-fops-half=" + fops));
+  }
+  if (Args.hasArg(options::OPT_msoft_fops_single)) {
+    StringRef fops = Args.getLastArgValue(options::OPT_msoft_fops_single);
+    CmdArgs.push_back(Args.MakeArgString("-msoft-fops-single=" + fops));
+  }
+  if (Args.hasArg(options::OPT_mhard_fops_single)) {
+    StringRef fops = Args.getLastArgValue(options::OPT_mhard_fops_single);
+    CmdArgs.push_back(Args.MakeArgString("-mhard-fops-single=" + fops));
+  }
+  if (Args.hasArg(options::OPT_msoft_fops_double)) {
+    StringRef fops = Args.getLastArgValue(options::OPT_msoft_fops_double);
+    CmdArgs.push_back(Args.MakeArgString("-msoft-fops-double=" + fops));
+  }
+  if (Args.hasArg(options::OPT_mhard_fops_double)) {
+    StringRef fops = Args.getLastArgValue(options::OPT_mhard_fops_double);
+    CmdArgs.push_back(Args.MakeArgString("-mhard-fops-double=" + fops));
+  }
+
+  if (Args.hasArg(options::OPT_daiteq_fpu_type)) {
+    StringRef dfpu = Args.getLastArgValue(options::OPT_daiteq_fpu_type);
+    CmdArgs.push_back(Args.MakeArgString("-daiteq-fpu-type=" + dfpu));
+  }
+
+/* TODO: swar nebo packed can be enabled with CPU extensions */
+  for (const auto *A : Args.filtered(options::OPT_target_feature)) {
+    StringRef SFeat = A->getValue();
+    //if (SFeat=="+x-fph") Opts.EnabledPackedHalf = true;
+    //else if (SFeat=="+x-fps") Opts.EnabledPackedSingle = true;
+    //else if (SFeat=="+x-swar") Opts.EnabledSWARdaiteq = true;
+  }
+
+  if (Args.hasArg(options::OPT_daiteq_swar_enable)) {
+    CmdArgs.push_back("-daiteq-swar-enable");
+  }
+
+  if (Args.hasArg(options::OPT_daiteq_swar_type)) {
+    StringRef dswar = Args.getLastArgValue(options::OPT_daiteq_swar_type);
+    CmdArgs.push_back(Args.MakeArgString("-daiteq-swar-force-config=" + dswar));
+  }
+
 }
 
 void ClangAs::ConstructJob(Compilation &C, const JobAction &JA,
diff --git a/clang/lib/Driver/ToolChains/Clang.h b/clang/lib/Driver/ToolChains/Clang.h
index d4b4988b4a8c..7bd535448ed1 100644
--- a/clang/lib/Driver/ToolChains/Clang.h
+++ b/clang/lib/Driver/ToolChains/Clang.h
@@ -59,6 +59,14 @@ private:
                         llvm::opt::ArgStringList &CmdArgs) const;
   void AddR600TargetArgs(const llvm::opt::ArgList &Args,
                          llvm::opt::ArgStringList &CmdArgs) const;
+
+  unsigned SelectFPUForDoubleFP(const llvm::opt::ArgList &Args,
+                                llvm::opt::ArgStringList &CmdArgs) const;
+  unsigned SelectFPUForSingleFP(const llvm::opt::ArgList &Args,
+                                llvm::opt::ArgStringList &CmdArgs) const;
+  unsigned SelectFPUForHalfFP(const llvm::opt::ArgList &Args,
+                              llvm::opt::ArgStringList &CmdArgs) const;
+
   void AddRISCVTargetArgs(const llvm::opt::ArgList &Args,
                           llvm::opt::ArgStringList &CmdArgs) const;
   void AddSparcTargetArgs(const llvm::opt::ArgList &Args,
diff --git a/clang/lib/Driver/Types.cpp b/clang/lib/Driver/Types.cpp
index b7ccdf23cbaa..8a4cdcaa9f55 100644
--- a/clang/lib/Driver/Types.cpp
+++ b/clang/lib/Driver/Types.cpp
@@ -355,7 +355,8 @@ types::getCompilationPhases(const clang::driver::Driver &Driver,
            DAL.getLastArg(options::OPT_emit_llvm))
     LastPhase = phases::Backend;
 
-  else if (DAL.getLastArg(options::OPT_c))
+  else if (DAL.getLastArg(options::OPT_c) ||
+           DAL.getLastArg(options::OPT_print_sf_uid))
     LastPhase = phases::Assemble;
 
   // Generally means, do every phase until Link.
diff --git a/clang/lib/Format/FormatToken.h b/clang/lib/Format/FormatToken.h
index 0506cd554bcb..28dfb7893b5a 100644
--- a/clang/lib/Format/FormatToken.h
+++ b/clang/lib/Format/FormatToken.h
@@ -567,6 +567,7 @@ public:
     case tok::exclaim:
     case tok::tilde:
     case tok::kw_sizeof:
+    case tok::kw_sizeofswar:
     case tok::kw_alignof:
       return true;
     default:
@@ -592,6 +593,7 @@ public:
     case tok::kw_typeid:
     case tok::kw_return:
     case tok::kw_sizeof:
+    case tok::kw_sizeofswar:
     case tok::kw_alignof:
     case tok::kw_alignas:
     case tok::kw_decltype:
diff --git a/clang/lib/Format/TokenAnnotator.cpp b/clang/lib/Format/TokenAnnotator.cpp
index 54e6c7d38e7d..232fce0d4617 100644
--- a/clang/lib/Format/TokenAnnotator.cpp
+++ b/clang/lib/Format/TokenAnnotator.cpp
@@ -1904,7 +1904,7 @@ private:
     // If a (non-string) literal follows, this is likely a cast.
     if (Tok.Next->isNot(tok::string_literal) &&
         (Tok.Next->Tok.isLiteral() ||
-         Tok.Next->isOneOf(tok::kw_sizeof, tok::kw_alignof)))
+         Tok.Next->isOneOf(tok::kw_sizeof, tok::kw_sizeofswar, tok::kw_alignof)))
       return true;
 
     // Heuristically try to determine whether the parentheses contain a type.
@@ -2021,7 +2021,7 @@ private:
                            tok::comma, tok::semi, tok::kw_return, tok::colon,
                            tok::kw_co_return, tok::kw_co_await,
                            tok::kw_co_yield, tok::equal, tok::kw_delete,
-                           tok::kw_sizeof, tok::kw_throw) ||
+                           tok::kw_sizeof, tok::kw_sizeofswar, tok::kw_throw) ||
         PrevToken->isOneOf(TT_BinaryOperator, TT_ConditionalExpr,
                            TT_UnaryOperator, TT_CastRParen))
       return TT_UnaryOperator;
diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp
index 7025028bc94a..04e363fdb561 100644
--- a/clang/lib/Frontend/CompilerInvocation.cpp
+++ b/clang/lib/Frontend/CompilerInvocation.cpp
@@ -99,6 +99,7 @@
 #include <type_traits>
 #include <utility>
 #include <vector>
+#include <sstream>
 
 using namespace clang;
 using namespace driver;
@@ -1538,6 +1539,20 @@ void CompilerInvocation::GenerateCodeGenArgs(
     GenerateArg(Args, OPT_fno_finite_loops, SA);
     break;
   }
+
+  if (Opts.EnabledSWARdaiteq) {
+    GenerateArg(Args, OPT_daiteq_swar_enable, SA);
+  }
+  if (Opts.EnabledPackedHalf) {
+    GenerateArg(Args, OPT_menable_packedhalf, SA);
+  }
+  if (Opts.EnabledPackedSingle) {
+    GenerateArg(Args, OPT_menable_packedsingle, SA);
+  }
+  GenerateArg(Args, OPT_msoft_double, std::to_string(Opts.SoftFopsDouble), SA);
+  GenerateArg(Args, OPT_msoft_single, std::to_string(Opts.SoftFopsSingle), SA);
+  GenerateArg(Args, OPT_msoft_half, std::to_string(Opts.SoftFopsHalf), SA);
+
 }
 
 bool CompilerInvocation::ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args,
@@ -1770,6 +1785,63 @@ bool CompilerInvocation::ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args,
     }
   }
 
+  /*
+   * For daiteq sparc/riscv architecture all options around soft-float operations will be position
+   * dependent because they will mask different operations and it si only one way to
+   * reach required combination of all possible possibilities.
+   * First, architecture extensions are checked for enabled FP extensions.
+   */
+  bool isdtq =  (T.getArch() == llvm::Triple::sparc ||
+                 T.getArch() == llvm::Triple::riscv32 ||
+                 T.getArch() == llvm::Triple::riscv64) && // TODO: enable for all architectures supported in daiteq vendor
+                (T.getVendor() == llvm::Triple::Daiteq);
+  Opts.SoftFloat = Args.hasArg(OPT_msoft_float);
+  if (isdtq) {
+    Opts.SoftFopsHalf = -1; /* default is FP in a software */
+    Opts.SoftFopsSingle = -1; /* default is FP in a software */
+    Opts.SoftFopsDouble = -1; /* default is FP in a software */
+
+    /* only for RISC-V prepare FPU selection from CPU features */
+    if (T.getArch() == llvm::Triple::riscv32 ||
+        T.getArch() == llvm::Triple::riscv64) {
+      for (Arg *A : Args.filtered(OPT_target_feature)) {
+        StringRef SFeat = A->getValue();
+        if (SFeat=="+f") Opts.SoftFopsSingle = 0;
+        else if (SFeat=="+d") Opts.SoftFopsDouble = 0;
+        else if (SFeat=="+zfh") Opts.SoftFopsHalf = 0;
+        else if (SFeat=="+x-fph") Opts.EnabledPackedHalf = true;
+        else if (SFeat=="+x-fps") Opts.EnabledPackedSingle = true;
+        else if (SFeat=="+x-swar") Opts.EnabledSWARdaiteq = true;
+      }
+    }
+    if (Arg *A = Args.getLastArg(OPT_daiteq_swar_type)) {
+      StringRef SKind = A->getValue();
+      if (SKind=="alu") {
+        Opts.UseSWARUnit = llvm::SwarKinds::ALU;
+      } else if (SKind=="video") {
+        Opts.UseSWARUnit = llvm::SwarKinds::Video;
+      } else if (SKind=="audio") {
+        Opts.UseSWARUnit = llvm::SwarKinds::Audio;
+      } else if (SKind=="infer") {
+        Opts.UseSWARUnit = llvm::SwarKinds::Infer;
+      } else
+        Diags.Report(diag::err_drv_invalid_value)
+            << A->getAsString(Args) << A->getValue();
+    } else
+      Opts.UseSWARUnit = llvm::SwarKinds::Infer;
+
+    if (Arg *A = Args.getLastArg(OPT_msoft_double)) {
+      Opts.SoftFopsDouble = atoi(A->getValue());
+    }
+    if (Arg *A = Args.getLastArg(OPT_msoft_single)) {
+      Opts.SoftFopsSingle = atoi(A->getValue());
+    }
+    if (Arg *A = Args.getLastArg(OPT_msoft_half)) {
+      Opts.SoftFopsHalf = atoi(A->getValue());
+    }
+  }
+
+
   auto XRayInstrBundles =
       Args.getAllArgValues(OPT_fxray_instrumentation_bundle);
   if (XRayInstrBundles.empty())
@@ -3533,6 +3605,119 @@ void CompilerInvocation::GenerateLangArgs(const LangOptions &Opts,
     GenerateArg(Args, OPT_fmacro_prefix_map_EQ, MP.first + "=" + MP.second, SA);
 }
 
+
+enum daiteq_ext_bits {
+  DAI_EX_BIT_M     = 0x01,
+  DAI_EX_BIT_A     = 0x02,
+  DAI_EX_BIT_F     = 0x04,
+  DAI_EX_BIT_D     = 0x08,
+  DAI_EX_BIT_C     = 0x10,
+  DAI_EX_BIT_ZFH   = 0x20,
+  DAI_EX_BIT_XFPS  = 0x40,
+  DAI_EX_BIT_XFPH  = 0x80,
+  DAI_EX_BIT_XSWAR = 0x100,
+};
+
+enum daiteq_daufpu_unit {
+  DAIFPU_UNKNOWN = 0,
+  DAIFPU_DUAL_DPSP_DIVSQRT = 1,
+  DAIFPU_DUAL_DPSP_DIVONLY = 2,
+  DAIFPU_DUAL_DPSP_NONE    = 3,
+  DAIFPU_DUAL_SPHP_DIVSQRT = 4,
+  DAIFPU_DUAL_SPHP_DIVONLY = 5,
+  DAIFPU_DUAL_SPHP_NONE    = 6,
+  DAIFPU_DP_DIVSQRT        = 7,
+  DAIFPU_DP_DIVONLY        = 8,
+  DAIFPU_DP_NONE           = 9,
+  DAIFPU_SP_DIVSQRT        = 10,
+  DAIFPU_SP_DIVONLY        = 11,
+  DAIFPU_SP_NONE           = 12,
+  DAIFPU_HP_DIVSQRT        = 13,
+  DAIFPU_HP_DIVONLY        = 14,
+  DAIFPU_HP_NONE           = 15,
+  DAIFPU_PSP_DIVSQRT       = 16,
+  DAIFPU_PSP_DIVONLY       = 17,
+  DAIFPU_PSP_NONE          = 18,
+  DAIFPU_PHP_DIVSQRT       = 19,
+  DAIFPU_PHP_DIVONLY       = 20,
+  DAIFPU_PHP_NONE          = 21,
+  DAIFPU_NONE              = 22,
+};
+
+#define DAI_EX_BIT_TESTMASK \
+            (DAI_EX_BIT_F | DAI_EX_BIT_D | DAI_EX_BIT_ZFH | \
+             DAI_EX_BIT_XFPS | DAI_EX_BIT_XFPH)
+
+unsigned parseRISCVsfsel(unsigned extBits, unsigned sfDblMask, 
+                         unsigned sfFltMask, unsigned sfHalfMask) 
+{
+  sfDblMask &= llvm::SoftFops::FPOP_KNOWN_MASK; // bounded masks
+  sfFltMask &= llvm::SoftFops::FPOP_KNOWN_MASK;
+  sfHalfMask &= llvm::SoftFops::FPOP_KNOWN_MASK;
+  extBits &= DAI_EX_BIT_TESTMASK; // limited to tested bits
+
+  if (extBits==(DAI_EX_BIT_F | DAI_EX_BIT_D) && (sfHalfMask==llvm::SoftFops::FPOP_KNOWN_MASK)) {           // dual_dpsp, dp
+    if (sfFltMask==llvm::SoftFops::FPOP_KNOWN_MASK) { // soft sp -> only dp
+      if (sfDblMask==0) return DAIFPU_DP_DIVSQRT;
+      else if (sfDblMask==llvm::SoftFops::FPOP_SQRT) return DAIFPU_DP_DIVONLY;
+      else if (sfDblMask==(llvm::SoftFops::FPOP_DIV | llvm::SoftFops::FPOP_SQRT)) return DAIFPU_DP_NONE;
+    } else {                          // dual_dpsp
+      if (sfDblMask==0 && sfFltMask==0) return DAIFPU_DUAL_DPSP_DIVSQRT;
+      else if (sfDblMask==llvm::SoftFops::FPOP_SQRT && sfFltMask==llvm::SoftFops::FPOP_SQRT) return DAIFPU_DUAL_DPSP_DIVONLY;
+      else if (sfDblMask==(llvm::SoftFops::FPOP_DIV | llvm::SoftFops::FPOP_SQRT) &&
+               sfFltMask==(llvm::SoftFops::FPOP_DIV | llvm::SoftFops::FPOP_SQRT)) return DAIFPU_DUAL_DPSP_NONE;
+    }
+  } 
+
+  if (extBits==(DAI_EX_BIT_F | DAI_EX_BIT_ZFH) && (sfDblMask==llvm::SoftFops::FPOP_KNOWN_MASK)) {  // dual_sphp
+    if (sfFltMask==0 && sfHalfMask==0) return DAIFPU_DUAL_SPHP_DIVSQRT;
+    else if (sfFltMask==llvm::SoftFops::FPOP_SQRT && sfHalfMask==llvm::SoftFops::FPOP_SQRT) return DAIFPU_DUAL_SPHP_DIVONLY;
+    else if (sfFltMask==(llvm::SoftFops::FPOP_DIV | llvm::SoftFops::FPOP_SQRT) &&
+             sfHalfMask==(llvm::SoftFops::FPOP_DIV | llvm::SoftFops::FPOP_SQRT)) return DAIFPU_DUAL_SPHP_NONE;
+  } 
+
+  if (extBits==(DAI_EX_BIT_F) &&
+             (sfDblMask==llvm::SoftFops::FPOP_KNOWN_MASK) &&
+             (sfHalfMask==llvm::SoftFops::FPOP_KNOWN_MASK)) {                                   // sp
+    if (sfFltMask==0) return DAIFPU_SP_DIVSQRT;
+    else if (sfFltMask==llvm::SoftFops::FPOP_SQRT) return DAIFPU_SP_DIVONLY;
+    else if (sfFltMask==(llvm::SoftFops::FPOP_DIV | llvm::SoftFops::FPOP_SQRT)) return DAIFPU_SP_NONE;
+  } 
+
+  if (extBits==(DAI_EX_BIT_ZFH) &&
+             (sfDblMask==llvm::SoftFops::FPOP_KNOWN_MASK) &&
+             (sfFltMask==llvm::SoftFops::FPOP_KNOWN_MASK)) {                                    // hp
+    if (sfHalfMask==0) return DAIFPU_HP_DIVSQRT;
+    else if (sfHalfMask==llvm::SoftFops::FPOP_SQRT) return DAIFPU_HP_DIVONLY;
+    else if (sfHalfMask==(llvm::SoftFops::FPOP_DIV | llvm::SoftFops::FPOP_SQRT)) return DAIFPU_HP_NONE;
+  } 
+  
+  if (extBits==(DAI_EX_BIT_F | DAI_EX_BIT_XFPS) &&
+             (sfDblMask==llvm::SoftFops::FPOP_KNOWN_MASK) &&
+             (sfHalfMask==llvm::SoftFops::FPOP_KNOWN_MASK)) {                                   // psp
+    if (sfFltMask==0) return DAIFPU_PSP_DIVSQRT;
+    else if (sfFltMask==llvm::SoftFops::FPOP_SQRT) return DAIFPU_PSP_DIVONLY;
+    else if (sfFltMask==(llvm::SoftFops::FPOP_DIV | llvm::SoftFops::FPOP_SQRT)) return DAIFPU_PSP_NONE;
+  } 
+  
+  if (extBits==(DAI_EX_BIT_ZFH | DAI_EX_BIT_XFPH) &&
+             (sfDblMask==llvm::SoftFops::FPOP_KNOWN_MASK) &&
+             (sfFltMask==llvm::SoftFops::FPOP_KNOWN_MASK)) {                                    // php
+    if (sfHalfMask==0) return DAIFPU_PHP_DIVSQRT;
+    else if (sfHalfMask==llvm::SoftFops::FPOP_SQRT) return DAIFPU_PHP_DIVONLY;
+    else if (sfHalfMask==(llvm::SoftFops::FPOP_DIV | llvm::SoftFops::FPOP_SQRT)) return DAIFPU_PHP_NONE;
+  } 
+  
+  if (extBits==0 ||                                                                      // none
+               ((sfDblMask==llvm::SoftFops::FPOP_KNOWN_MASK) && 
+                (sfFltMask==llvm::SoftFops::FPOP_KNOWN_MASK) && 
+                (sfHalfMask==llvm::SoftFops::FPOP_KNOWN_MASK))) {
+    return DAIFPU_NONE;
+  }
+
+  return DAIFPU_UNKNOWN; // unsupported combination
+}
+
 bool CompilerInvocation::ParseLangArgs(LangOptions &Opts, ArgList &Args,
                                        InputKind IK, const llvm::Triple &T,
                                        std::vector<std::string> &Includes,
@@ -3643,6 +3828,197 @@ bool CompilerInvocation::ParseLangArgs(LangOptions &Opts, ArgList &Args,
 #include "clang/Driver/Options.inc"
 #undef LANG_OPTION_WITH_MARSHALLING
 
+  // daiteq extensions for Sparc with configurable FPU
+  if ((T.getArch() == llvm::Triple::sparc ||
+       T.getArch() == llvm::Triple::riscv32 ||
+       T.getArch() == llvm::Triple::riscv64) && // enable for all architectures
+      T.getVendor() == llvm::Triple::Daiteq) {
+    Opts.NativeHalfType = 1;
+    Opts.NativeHalfArgsAndReturns = 1;
+    Opts.Half = 1;
+    Opts.HalfArgsAndReturns = 1;
+
+    Opts.EnabledSWARdaiteq = Args.hasArg(OPT_daiteq_swar_enable);
+    if (Arg *A = Args.getLastArg(OPT_daiteq_swar_type)) {
+      StringRef SKind = A->getValue();
+      if (SKind=="alu") {
+        Opts.UseSWARUnit = llvm::SwarKinds::ALU;
+      } else if (SKind=="video") {
+        Opts.UseSWARUnit = llvm::SwarKinds::Video;
+      } else if (SKind=="audio") {
+        Opts.UseSWARUnit = llvm::SwarKinds::Audio;
+      } else if (SKind=="infer") {
+        Opts.UseSWARUnit = llvm::SwarKinds::Infer;
+      } else
+        Diags.Report(diag::err_drv_invalid_value)
+            << A->getAsString(Args) << A->getValue();
+    } else
+      Opts.UseSWARUnit = llvm::SwarKinds::Infer;
+
+    /* only for RISC-V prepare FPU selection from CPU features */
+    if (T.getArch() == llvm::Triple::riscv32 ||
+        T.getArch() == llvm::Triple::riscv64) {
+      for (const auto *A : Args.filtered(OPT_target_feature)) {
+        StringRef SFeat = A->getValue();
+        //if (SFeat=="+f") Opts.SoftFopsSingle = 0;
+        //else if (SFeat=="+d") Opts.SoftFopsDouble = 0;
+        //else if (SFeat=="+zfh") Opts.SoftFopsHalf = 0;
+        //else
+        if (SFeat=="+x-fph") Opts.EnabledPackedHalf = true;
+        else if (SFeat=="+x-fps") Opts.EnabledPackedSingle = true;
+        else if (SFeat=="+x-swar") Opts.EnabledSWARdaiteq = true;
+      }
+    }
+
+    if (Arg *A = Args.getLastArg(OPT_msoft_double)) {
+      Opts.SoftFopsDouble = atoi(A->getValue());
+    }
+    if (Arg *A = Args.getLastArg(OPT_msoft_single)) {
+      Opts.SoftFopsSingle = atoi(A->getValue());
+    }
+    if (Arg *A = Args.getLastArg(OPT_msoft_half)) {
+      Opts.SoftFopsHalf = atoi(A->getValue());
+    }
+
+    if (Args.hasArg(OPT_print_sf_uid)) {
+      std::stringstream stream;
+      std::string Buffer;
+      llvm::raw_string_ostream OS(Buffer);
+
+      // 1. rv32i/rv32e/rv64i
+      if (T.getArch()==llvm::Triple::riscv64)
+        OS << "rv64i";
+      else if (T.getArch()==llvm::Triple::riscv32)
+        OS << "rv32i";
+      else /* unsupported e.g. rv32e */
+        OS << "rv";
+
+      // 2. +m
+      // 3. +a
+      // 4. +f
+      // 5. +d
+      // 6. +c
+      // 7. +zfh
+      // 8. +x-fps
+      // 9. +x-fph
+      // 10. +x-swar
+      unsigned extbits = 0;
+      for (const auto *A : Args.filtered(OPT_target_feature)) {
+        StringRef SF = A->getValue();
+        if (SF=="+m") extbits |= DAI_EX_BIT_M;
+        else if (SF=="+a") extbits |= DAI_EX_BIT_A;
+        else if (SF=="+f") extbits |= DAI_EX_BIT_F;
+        else if (SF=="+d") extbits |= DAI_EX_BIT_D;
+        else if (SF=="+c") extbits |= DAI_EX_BIT_C;
+        else if (SF=="+zfh") extbits |= DAI_EX_BIT_ZFH;
+        else if (SF=="+x-fps") extbits |= DAI_EX_BIT_XFPS;
+        else if (SF=="+x-fph") extbits |= DAI_EX_BIT_XFPH;
+        else if (SF=="+x-swar") extbits |= DAI_EX_BIT_XSWAR;
+      }
+      if (extbits & DAI_EX_BIT_M) OS << "m";
+      if (extbits & DAI_EX_BIT_A) OS << "a";
+      if (extbits & DAI_EX_BIT_F) OS << "f";
+      if (extbits & DAI_EX_BIT_D) OS << "d";
+      if (extbits & DAI_EX_BIT_C) OS << "c";
+      if (extbits & DAI_EX_BIT_ZFH) OS << "_zfh";
+      if (extbits & DAI_EX_BIT_XFPS) OS << "_x-fps";
+      if (extbits & DAI_EX_BIT_XFPH) OS << "_x-fph";
+      if (extbits & DAI_EX_BIT_XSWAR) OS << "_x-swar";
+      
+      OS << "-";
+      if (Args.hasArg(OPT_target_abi)) {
+        OS << Args.getLastArgValue(OPT_target_abi);
+      } else {
+        if (T.getArch() == llvm::Triple::riscv32)
+          OS << "lp32";
+        else
+          OS << "lp64";
+      }
+      switch(parseRISCVsfsel(extbits, Opts.SoftFopsDouble, 
+                              Opts.SoftFopsSingle,Opts.SoftFopsHalf)) {
+        default:
+        case DAIFPU_UNKNOWN: // unknown combination
+          stream << std::hex << Opts.SoftFopsDouble;
+          OS << "-" << stream.str();
+          stream.str("");
+          stream << std::hex << Opts.SoftFopsSingle;
+          OS << "-" << stream.str();
+          stream.str("");
+          stream << std::hex << Opts.SoftFopsHalf;
+          OS << "-" << stream.str();
+          break;
+        case DAIFPU_DUAL_DPSP_DIVSQRT: // daifpu_divsqrt, daifpu_dual_dpsp_divsqrt
+          OS << "-daifpu_dual_dpsp_divsqrt";
+          break;
+        case DAIFPU_DUAL_DPSP_DIVONLY: // daifpu_divonly, daifpu_dual_dpsp_divonly
+          OS << "-daifpu_dual_dpsp_divonly";
+          break;
+        case DAIFPU_DUAL_DPSP_NONE: // daifpu_none, daifpu_dual_dpsp_none
+          OS << "-daifpu_dual_dpsp_none";
+          break;
+        case DAIFPU_DUAL_SPHP_DIVSQRT: // daifpu_dual_sphp_divsqrt
+          OS << "-daifpu_dual_sphp_divsqrt";
+          break;
+        case DAIFPU_DUAL_SPHP_DIVONLY: // daifpu_dual_sphp_divonly
+          OS << "-daifpu_dual_sphp_divonly";
+          break;
+        case DAIFPU_DUAL_SPHP_NONE: // daifpu_dual_sphp_none
+          OS << "-daifpu_dual_sphp_none";
+          break;
+        case DAIFPU_DP_DIVSQRT: // daifpu_dp_divsqrt
+          OS << "-daifpu_dp_divsqrt";
+          break;
+        case DAIFPU_DP_DIVONLY: // daifpu_dp_divonly
+          OS << "-daifpu_dp_divonly";
+          break;
+        case DAIFPU_DP_NONE: // daifpu_dp_none
+          OS << "-daifpu_dp_none";
+          break;
+        case DAIFPU_SP_DIVSQRT: // daifpu_sp_divsqrt
+          OS << "-daifpu_sp_divsqrt";
+          break;
+        case DAIFPU_SP_DIVONLY: // daifpu_sp_divonly
+          OS << "-daifpu_sp_divonly";
+          break;
+        case DAIFPU_SP_NONE: // daifpu_sp_none
+          OS << "-daifpu_sp_none";
+          break;
+        case DAIFPU_HP_DIVSQRT: // daifpu_hp_divsqrt
+          OS << "-daifpu_hp_divsqrt";
+          break;
+        case DAIFPU_HP_DIVONLY: // daifpu_hp_divonly
+          OS << "-daifpu_hp_divonly";
+          break;
+        case DAIFPU_HP_NONE: // daifpu_hp_none
+          OS << "-daifpu_hp_none";
+          break;
+        case DAIFPU_PSP_DIVSQRT: // daifpu_psp_divsqrt
+          OS << "-daifpu_psp_divsqrt";
+          break;
+        case DAIFPU_PSP_DIVONLY: // daifpu_psp_divonly
+          OS << "-daifpu_psp_divonly";
+          break;
+        case DAIFPU_PSP_NONE: // daifpu_psp_none
+          OS << "-daifpu_psp_none";
+          break;
+        case DAIFPU_PHP_DIVSQRT: // daifpu_php_divsqrt
+          OS << "-daifpu_php_divsqrt";
+          break;
+        case DAIFPU_PHP_DIVONLY: // daifpu_php_divonly
+          OS << "-daifpu_php_divonly";
+          break;
+        case DAIFPU_PHP_NONE: // daifpu_php_none
+          OS << "-daifpu_php_none";
+          break;
+        case DAIFPU_NONE: // none
+          OS << "-none";
+          break;
+      }
+      fprintf(stdout,"%s\n", Buffer.c_str());
+    }
+
+  }
+
   if (const Arg *A = Args.getLastArg(OPT_fcf_protection_EQ)) {
     StringRef Name = A->getValue();
     if (Name == "full" || Name == "branch") {
@@ -4388,6 +4764,10 @@ bool CompilerInvocation::CreateFromArgsImpl(
 
   ParseLangArgs(LangOpts, Args, DashX, T, Res.getPreprocessorOpts().Includes,
                 Diags);
+  if (Args.hasArg(OPT_print_sf_uid)) {
+    return false;
+  }
+
   if (Res.getFrontendOpts().ProgramAction == frontend::RewriteObjC)
     LangOpts.ObjCExceptions = 1;
 
diff --git a/clang/lib/Frontend/Rewrite/RewriteModernObjC.cpp b/clang/lib/Frontend/Rewrite/RewriteModernObjC.cpp
index fd54bcbf7c35..5ac8e25a03ed 100644
--- a/clang/lib/Frontend/Rewrite/RewriteModernObjC.cpp
+++ b/clang/lib/Frontend/Rewrite/RewriteModernObjC.cpp
@@ -1229,7 +1229,6 @@ void RewriteModernObjC::RewriteTypeIntoString(QualType T, std::string &ResultStr
 void RewriteModernObjC::RewriteObjCMethodDecl(const ObjCInterfaceDecl *IDecl,
                                         ObjCMethodDecl *OMD,
                                         std::string &ResultStr) {
-  //fprintf(stderr,"In RewriteObjCMethodDecl\n");
   const FunctionType *FPRetType = nullptr;
   ResultStr += "\nstatic ";
   RewriteTypeIntoString(OMD->getReturnType(), ResultStr, FPRetType);
@@ -4448,7 +4447,6 @@ static void BuildUniqueMethodName(std::string &Name,
 }
 
 void RewriteModernObjC::InsertBlockLiteralsWithinMethod(ObjCMethodDecl *MD) {
-  // fprintf(stderr,"In InsertBlockLiteralsWitinMethod\n");
   // SourceLocation FunLocStart = MD->getBeginLoc();
   SourceLocation FunLocStart = MD->getBeginLoc();
   std::string FuncName;
diff --git a/clang/lib/Frontend/Rewrite/RewriteObjC.cpp b/clang/lib/Frontend/Rewrite/RewriteObjC.cpp
index 0750d36b02ac..7843976e29a2 100644
--- a/clang/lib/Frontend/Rewrite/RewriteObjC.cpp
+++ b/clang/lib/Frontend/Rewrite/RewriteObjC.cpp
@@ -1063,7 +1063,6 @@ void RewriteObjC::RewriteTypeIntoString(QualType T, std::string &ResultStr,
 void RewriteObjC::RewriteObjCMethodDecl(const ObjCInterfaceDecl *IDecl,
                                         ObjCMethodDecl *OMD,
                                         std::string &ResultStr) {
-  //fprintf(stderr,"In RewriteObjCMethodDecl\n");
   const FunctionType *FPRetType = nullptr;
   ResultStr += "\nstatic ";
   RewriteTypeIntoString(OMD->getReturnType(), ResultStr, FPRetType);
@@ -3635,7 +3634,6 @@ static void BuildUniqueMethodName(std::string &Name,
 }
 
 void RewriteObjC::InsertBlockLiteralsWithinMethod(ObjCMethodDecl *MD) {
-  // fprintf(stderr,"In InsertBlockLiteralsWitinMethod\n");
   // SourceLocation FunLocStart = MD->getBeginLoc();
   SourceLocation FunLocStart = MD->getBeginLoc();
   std::string FuncName;
diff --git a/clang/lib/Parse/ParseExpr.cpp b/clang/lib/Parse/ParseExpr.cpp
index 22f3b7624c45..1bca3497e42c 100644
--- a/clang/lib/Parse/ParseExpr.cpp
+++ b/clang/lib/Parse/ParseExpr.cpp
@@ -1416,6 +1416,8 @@ ExprResult Parser::ParseCastExpression(CastParseKind ParseKind,
                            // unary-expression: '__alignof' '(' type-name ')'
   case tok::kw_sizeof:     // unary-expression: 'sizeof' unary-expression
                            // unary-expression: 'sizeof' '(' type-name ')'
+  case tok::kw_sizeofswar: // unary-expression: 'sizeofswar' unary-expression
+                           // unary-expression: 'sizeofswar' '(' type-name ')'
   case tok::kw_vec_step:   // unary-expression: OpenCL 'vec_step' expression
   // unary-expression: '__builtin_omp_required_simd_align' '(' type-name ')'
   case tok::kw___builtin_omp_required_simd_align:
@@ -2250,8 +2252,9 @@ Parser::ParseExprAfterUnaryExprOrTypeTrait(const Token &OpTok,
                                            ParsedType &CastTy,
                                            SourceRange &CastRange) {
 
-  assert(OpTok.isOneOf(tok::kw_typeof, tok::kw_sizeof, tok::kw___alignof,
-                       tok::kw_alignof, tok::kw__Alignof, tok::kw_vec_step,
+  assert(OpTok.isOneOf(tok::kw_typeof, tok::kw_sizeof, tok::kw_sizeofswar,
+                       tok::kw___alignof, tok::kw_alignof, tok::kw__Alignof,
+                       tok::kw_vec_step,
                        tok::kw___builtin_omp_required_simd_align) &&
          "Not a typeof/sizeof/alignof/vec_step expression!");
 
@@ -2261,8 +2264,8 @@ Parser::ParseExprAfterUnaryExprOrTypeTrait(const Token &OpTok,
   if (Tok.isNot(tok::l_paren)) {
     // If construct allows a form without parenthesis, user may forget to put
     // pathenthesis around type name.
-    if (OpTok.isOneOf(tok::kw_sizeof, tok::kw___alignof, tok::kw_alignof,
-                      tok::kw__Alignof)) {
+    if (OpTok.isOneOf(tok::kw_sizeof, tok::kw_sizeofswar, tok::kw___alignof,
+                      tok::kw_alignof, tok::kw__Alignof)) {
       if (isTypeIdUnambiguously()) {
         DeclSpec DS(AttrFactory);
         ParseSpecifierQualifierList(DS);
@@ -2368,15 +2371,16 @@ ExprResult Parser::ParseSYCLUniqueStableNameExpression() {
 /// [C++11] 'alignof' '(' type-id ')'
 /// \endverbatim
 ExprResult Parser::ParseUnaryExprOrTypeTraitExpression() {
-  assert(Tok.isOneOf(tok::kw_sizeof, tok::kw___alignof, tok::kw_alignof,
-                     tok::kw__Alignof, tok::kw_vec_step,
+  assert(Tok.isOneOf(tok::kw_sizeof, tok::kw_sizeofswar, tok::kw___alignof,
+                     tok::kw_alignof, tok::kw__Alignof, tok::kw_vec_step,
                      tok::kw___builtin_omp_required_simd_align) &&
          "Not a sizeof/alignof/vec_step expression!");
   Token OpTok = Tok;
   ConsumeToken();
 
   // [C++11] 'sizeof' '...' '(' identifier ')'
-  if (Tok.is(tok::ellipsis) && OpTok.is(tok::kw_sizeof)) {
+  if (Tok.is(tok::ellipsis) && OpTok.is(tok::kw_sizeof) &&
+      OpTok.is(tok::kw_sizeofswar)) {
     SourceLocation EllipsisLoc = ConsumeToken();
     SourceLocation LParenLoc, RParenLoc;
     IdentifierInfo *Name = nullptr;
@@ -2438,7 +2442,9 @@ ExprResult Parser::ParseUnaryExprOrTypeTraitExpression() {
                                                           CastRange);
 
   UnaryExprOrTypeTrait ExprKind = UETT_SizeOf;
-  if (OpTok.isOneOf(tok::kw_alignof, tok::kw__Alignof))
+  if (OpTok.is(tok::kw_sizeofswar))
+    ExprKind = UETT_SizeOfSwar;
+  else if (OpTok.isOneOf(tok::kw_alignof, tok::kw__Alignof))
     ExprKind = UETT_AlignOf;
   else if (OpTok.is(tok::kw___alignof))
     ExprKind = UETT_PreferredAlignOf;
diff --git a/clang/lib/Parse/ParseObjc.cpp b/clang/lib/Parse/ParseObjc.cpp
index 9e145f57d61f..73f762eba189 100644
--- a/clang/lib/Parse/ParseObjc.cpp
+++ b/clang/lib/Parse/ParseObjc.cpp
@@ -1084,6 +1084,7 @@ IdentifierInfo *Parser::ParseObjCSelectorPiece(SourceLocation &SelectorLoc) {
   case tok::kw_short:
   case tok::kw_signed:
   case tok::kw_sizeof:
+  case tok::kw_sizeofswar:
   case tok::kw_static:
   case tok::kw_static_cast:
   case tok::kw_struct:
diff --git a/clang/lib/Parse/ParsePragma.cpp b/clang/lib/Parse/ParsePragma.cpp
index 42072fe63fc8..bb90952b67bc 100644
--- a/clang/lib/Parse/ParsePragma.cpp
+++ b/clang/lib/Parse/ParsePragma.cpp
@@ -298,6 +298,46 @@ void markAsReinjectedForRelexing(llvm::MutableArrayRef<clang::Token> Toks) {
   for (auto &T : Toks)
     T.setFlag(clang::Token::IsReinjected);
 }
+
+/// PragmaSWARSaturateHandler - "\#pragma swar saturate".
+struct PragmaSWARSaturateHandler : public PragmaHandler {
+  explicit PragmaSWARSaturateHandler(Sema &S)
+             : PragmaHandler("saturate"), Actions(S) {}
+  void HandlePragma(Preprocessor &PP, PragmaIntroducer Introducer,
+                    Token &FirstToken) override;
+private:
+  Sema &Actions;
+};
+/// PragmaSWARReductionHandler - "\#pragma swar reduction".
+struct PragmaSWARReductionHandler : public PragmaHandler {
+  explicit PragmaSWARReductionHandler(Sema &S)
+             : PragmaHandler("reduce"), Actions(S) {}
+  void HandlePragma(Preprocessor &PP, PragmaIntroducer Introducer,
+                    Token &FirstToken) override;
+private:
+  Sema &Actions;
+};
+/// PragmaSWARNormalizeHandler - "\#pragma swar normalize".
+struct PragmaSWARNormalizeHandler : public PragmaHandler {
+  explicit PragmaSWARNormalizeHandler(Sema &S)
+             : PragmaHandler("normalize"), Actions(S) {}
+  void HandlePragma(Preprocessor &PP, PragmaIntroducer Introducer,
+                    Token &FirstToken) override;
+private:
+  Sema &Actions;
+};
+
+/// PragmaSWARManualHandler - "\#pragma swar manual".
+struct PragmaSWARManualHandler : public PragmaHandler {
+  explicit PragmaSWARManualHandler(Sema &S)
+             : PragmaHandler("manual"), Actions(S) {}
+  void HandlePragma(Preprocessor &PP, PragmaIntroducer Introducer,
+                    Token &FirstToken) override;
+private:
+  Sema &Actions;
+};
+
+
 }  // end namespace
 
 void Parser::initializePragmaHandlers() {
@@ -431,6 +471,19 @@ void Parser::initializePragmaHandlers() {
 
   MaxTokensTotalPragmaHandler = std::make_unique<PragmaMaxTokensTotalHandler>();
   PP.AddPragmaHandler("clang", MaxTokensTotalPragmaHandler.get());
+
+
+  SwarSaturateHandler = std::make_unique<PragmaSWARSaturateHandler>(Actions);
+  PP.AddPragmaHandler("swar", SwarSaturateHandler.get());
+
+  SwarReductionHandler = std::make_unique<PragmaSWARReductionHandler>(Actions);
+  PP.AddPragmaHandler("swar", SwarReductionHandler.get());
+
+  SwarNormalizeHandler = std::make_unique<PragmaSWARNormalizeHandler>(Actions);
+  PP.AddPragmaHandler("swar", SwarNormalizeHandler.get());
+
+  SwarManualHandler = std::make_unique<PragmaSWARManualHandler>(Actions);
+  PP.AddPragmaHandler("swar", SwarManualHandler.get());
 }
 
 void Parser::resetPragmaHandlers() {
@@ -549,6 +602,19 @@ void Parser::resetPragmaHandlers() {
 
   PP.RemovePragmaHandler("clang", MaxTokensTotalPragmaHandler.get());
   MaxTokensTotalPragmaHandler.reset();
+
+
+  PP.RemovePragmaHandler("swar", SwarSaturateHandler.get());
+  SwarSaturateHandler.reset();
+
+  PP.RemovePragmaHandler("swar", SwarReductionHandler.get());
+  SwarReductionHandler.reset();
+
+  PP.RemovePragmaHandler("swar", SwarNormalizeHandler.get());
+  SwarNormalizeHandler.reset();
+
+  PP.RemovePragmaHandler("swar", SwarManualHandler.get());
+  SwarManualHandler.reset();
 }
 
 /// Handle the annotation token produced for #pragma unused(...)
@@ -3314,6 +3380,69 @@ void PragmaLoopHintHandler::HandlePragma(Preprocessor &PP,
                       /*DisableMacroExpansion=*/false, /*IsReinject=*/false);
 }
 
+
+/// Handle the SWAR saturate pragma.
+///  #pragma swar saturate
+///
+/// Set the saturation flag for the following swar instructions in the current block.
+void PragmaSWARSaturateHandler::HandlePragma(Preprocessor &PP,
+                                           PragmaIntroducer Introducer,
+                                           Token &FirstToken) {
+  Token Tok;
+  PP.Lex(Tok);
+  if (!Tok.is(tok::eod)) {
+    fprintf(stderr,"SWAR saturate pragma with argument...\n");
+  }
+  Actions.ActOnPragmaSwarSaturate(FirstToken.getLocation(), Actions.getCurScope(), true);
+}
+
+/// Handle the SWAR reduction pragma.
+///  #pragma swar reduction
+///
+/// Set the reduction flag for the following swar instructions in the current block.
+void PragmaSWARReductionHandler::HandlePragma(Preprocessor &PP,
+                                              PragmaIntroducer Introducer,
+                                              Token &FirstToken) {
+  Token Tok;
+  PP.Lex(Tok);
+  if (!Tok.is(tok::eod)) {
+    fprintf(stderr,"SWAR reduction pragma with argument...\n");
+  }
+  Actions.ActOnPragmaSwarReduce(FirstToken.getLocation(), Actions.getCurScope(), true);
+}
+
+/// Handle the SWAR normalize pragma.
+///  #pragma swar normalize
+///
+/// Set the normalize flag for the following swar instructions in the current scope block.
+void PragmaSWARNormalizeHandler::HandlePragma(Preprocessor &PP,
+                                              PragmaIntroducer Introducer,
+                                              Token &FirstToken) {
+  Token Tok;
+  PP.Lex(Tok);
+  if (!Tok.is(tok::eod)) {
+    fprintf(stderr,"SWAR normalize pragma with argument...\n");
+  }
+  Actions.ActOnPragmaSwarNormalize(FirstToken.getLocation(), Actions.getCurScope(), true);
+}
+
+/// Handle the SWAR manual pragma.
+///  #pragma swar manual
+///
+/// Set the manual flag for the following swar instructions in the current scope block.
+/// Manual flag disable automatical inserting "swarctrl" for the all following swar instructions in the current block.
+void PragmaSWARManualHandler::HandlePragma(Preprocessor &PP,
+                                           PragmaIntroducer Introducer,
+                                           Token &FirstToken) {
+  Token Tok;
+  PP.Lex(Tok);
+  if (!Tok.is(tok::eod)) {
+    fprintf(stderr,"SWAR manual pragma with argument...\n");
+  }
+  Actions.ActOnPragmaSwarManual(FirstToken.getLocation(), Actions.getCurScope(), true);
+}
+
+
 /// Handle the loop unroll optimization pragmas.
 ///  #pragma unroll
 ///  #pragma unroll unroll-hint-value
diff --git a/clang/lib/Sema/DeclSpec.cpp b/clang/lib/Sema/DeclSpec.cpp
index 72d9ea6dd3bf..7446b24575a0 100644
--- a/clang/lib/Sema/DeclSpec.cpp
+++ b/clang/lib/Sema/DeclSpec.cpp
@@ -1300,7 +1300,7 @@ void DeclSpec::Finish(Sema &S, const PrintingPolicy &Policy) {
       if (!S.getLangOpts().CPlusPlus)
         S.Diag(TSTLoc, diag::ext_integer_complex);
     } else if (TypeSpecType != TST_float && TypeSpecType != TST_double &&
-               TypeSpecType != TST_float128) {
+               TypeSpecType != TST_float128 && TypeSpecType != TST_half) {
       // FIXME: _Float16, __fp16?
       S.Diag(TSCLoc, diag::err_invalid_complex_spec)
         << getSpecifierName((TST)TypeSpecType, Policy);
diff --git a/clang/lib/Sema/SemaAttr.cpp b/clang/lib/Sema/SemaAttr.cpp
index fe8f02f02368..923f36f81ff0 100644
--- a/clang/lib/Sema/SemaAttr.cpp
+++ b/clang/lib/Sema/SemaAttr.cpp
@@ -1262,3 +1262,42 @@ bool Sema::checkCommonAttributeFeatures(const Decl *D, const ParsedAttr &A) {
 bool Sema::checkCommonAttributeFeatures(const Stmt *S, const ParsedAttr &A) {
   return ::checkCommonAttributeFeatures(*this, S, A);
 }
+
+/* update swarflags specific for each scope block */
+void Sema::ActOnPragmaSwarSaturate(SourceLocation PragmaLoc, Scope *curScope, bool enbl) {
+  if (curScope->getFnParent()->getEntity()) {
+    DeclContext *dc = curScope->getFnParent()->getEntity();
+    if (!dc->swarPragmaLoc[DeclContext::SwarIndices::saturateIdx].isValid())
+      dc->swarPragmaLoc[DeclContext::SwarIndices::saturateIdx] = PragmaLoc;
+  } else {
+    Diag(PragmaLoc, diag::err_swar_pragma_outside_declctx);
+  }
+}
+void Sema::ActOnPragmaSwarReduce(SourceLocation PragmaLoc, Scope *curScope, bool enbl) {
+  if (curScope->getFnParent()->getEntity()) {
+    DeclContext *dc = curScope->getFnParent()->getEntity();
+    if (!dc->swarPragmaLoc[DeclContext::SwarIndices::reduceIdx].isValid())
+      dc->swarPragmaLoc[DeclContext::SwarIndices::reduceIdx] = PragmaLoc;
+  } else {
+    Diag(PragmaLoc, diag::err_swar_pragma_outside_declctx);
+  }
+}
+void Sema::ActOnPragmaSwarNormalize(SourceLocation PragmaLoc, Scope *curScope, bool enbl) {
+  if (curScope->getFnParent()->getEntity()) {
+    DeclContext *dc = curScope->getFnParent()->getEntity();
+    if (!dc->swarPragmaLoc[DeclContext::SwarIndices::normalizeIdx].isValid())
+      dc->swarPragmaLoc[DeclContext::SwarIndices::normalizeIdx] = PragmaLoc;
+  } else {
+    Diag(PragmaLoc, diag::err_swar_pragma_outside_declctx);
+  }
+}
+void Sema::ActOnPragmaSwarManual(SourceLocation PragmaLoc, Scope *curScope, bool enbl) {
+
+  if (curScope->getFnParent()->getEntity()) {
+    DeclContext *dc = curScope->getFnParent()->getEntity();
+    if (!dc->swarPragmaLoc[DeclContext::SwarIndices::manualIdx].isValid())
+      dc->swarPragmaLoc[DeclContext::SwarIndices::manualIdx] = PragmaLoc;
+  } else {
+    Diag(PragmaLoc, diag::err_swar_pragma_outside_declctx);
+  }
+}
diff --git a/clang/lib/Sema/SemaCast.cpp b/clang/lib/Sema/SemaCast.cpp
index cac43075f860..8a16111392fb 100644
--- a/clang/lib/Sema/SemaCast.cpp
+++ b/clang/lib/Sema/SemaCast.cpp
@@ -2900,7 +2900,8 @@ void CastOperation::CheckCStyleCast() {
     return;
   }
 
-  if (!DestType->isScalarType() && !DestType->isVectorType() &&
+  if (!DestType->isScalarType() &&
+      !(DestType->isVectorType() || DestType->isSubwordType()) &&
       !DestType->isMatrixType()) {
     const RecordType *DestRecordTy = DestType->getAs<RecordType>();
 
@@ -2952,6 +2953,12 @@ void CastOperation::CheckCStyleCast() {
     return;
   }
 
+  if (const SubwordType *DestSWTy = DestType->getAs<SubwordType>()) {
+      Kind = CK_IntegralCast;
+      return;
+    return;
+  }
+
   // The type we're casting to is known to be a scalar, a vector, or a matrix.
 
   // Require the operand to be a scalar, a vector, or a matrix.
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index de75c10417e7..8b7f7e982a9b 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -406,6 +406,62 @@ static bool SemaBuiltinCallWithStaticChain(Sema &S, CallExpr *BuiltinCall) {
   return false;
 }
 
+
+static ExprResult SemaBuiltinSwarOverload(Sema &S, ExprResult TheCallResult) { //CallExpr *TheCall, unsigned BuiltinID) {
+  CallExpr *TheCall = static_cast<CallExpr *>(TheCallResult.get());
+  Expr *Callee = TheCall->getCallee();
+  DeclRefExpr *DRE = cast<DeclRefExpr>(Callee->IgnoreParenCasts());
+  FunctionDecl *FDecl = cast<FunctionDecl>(DRE->getDecl());
+  unsigned BuiltinID = FDecl->getBuiltinID();
+  unsigned nArgs = TheCall->getNumArgs();
+  bool isSwar = false;
+
+  if (BuiltinID==Builtin::BI__builtin_swarctrl || BuiltinID==Builtin::BI__builtin_swaraccum) {
+    if (checkArgCount(S, TheCall, 1))
+      return ExprError();
+  } else {
+    isSwar = true;
+    if (checkArgCount(S, TheCall, 2))
+      return ExprError();
+  }
+  // get the return type from a type of the first argument
+  Expr *FirstArg = TheCall->getArg(0);
+  ExprResult FirstArgResult = S.DefaultFunctionArrayLvalueConversion(FirstArg);
+  if (FirstArgResult.isInvalid())
+    return ExprError();
+  FirstArg = FirstArgResult.get();
+  TheCall->setArg(0, FirstArg);
+
+  QualType FAType = FirstArg->getType();
+  if (!FAType->isIntegerType() && (isSwar && !FAType->isSubwordType())) {
+    S.Diag(FirstArg->getBeginLoc(), diag::err_overflow_builtin_must_be_int)
+        << FAType << FirstArg->getSourceRange();
+    return ExprError();
+    }
+
+  if (nArgs==2) {
+    ExprResult SecArgResult = S.DefaultFunctionArrayLvalueConversion(TheCall->getArg(1));
+    if (SecArgResult.isInvalid()) return ExprError();
+    TheCall->setArg(1, SecArgResult.get());
+  }
+
+  FAType = FAType.getUnqualifiedType();
+  QualType ResultType = FAType;
+
+  if (BuiltinID==Builtin::BI__builtin_swarctrl) {
+    ResultType = S.Context.VoidTy;
+  } else if (BuiltinID==Builtin::BI__builtin_swaraccum) {
+    if (S.getASTContext().getTargetInfo().getTriple().getArch()==llvm::Triple::riscv64)
+      ResultType = S.Context.UnsignedLongTy;
+    else
+      ResultType = S.Context.UnsignedIntTy;
+  }
+
+  TheCall->setType(ResultType);
+
+  return TheCallResult;
+}
+
 namespace {
 
 class EstimateSizeFormatHandler
@@ -1989,7 +2045,15 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID,
            diag::err_hip_invalid_args_builtin_mangled_name);
       return ExprError();
     }
+    break;
   }
+
+  case Builtin::BI__builtin_swarctrl:   // void F(u32/u64)
+  case Builtin::BI__builtin_swaraccum:  // u32/u64 F(i)
+  case Builtin::BI__builtin_swar:       // u32/u64 F(u32/u64, u32/u64)
+  case Builtin::BI__builtin_swarcc:     // u32/u64 F(u32/u64, u32/u64)
+    return SemaBuiltinSwarOverload(*this, TheCallResult); // *this, TheCall, BuiltinID))
+
   }
 
   // Since the target specific builtins for each arch overlap, only check those
@@ -9620,6 +9684,8 @@ static unsigned getLargerAbsoluteValueFunction(unsigned AbsFunction) {
   case Builtin::BI__builtin_llabs:
     return 0;
 
+  case Builtin::BI__builtin_fabsh:
+    return Builtin::BI__builtin_fabsf;
   case Builtin::BI__builtin_fabsf:
     return Builtin::BI__builtin_fabs;
   case Builtin::BI__builtin_fabs:
@@ -9641,6 +9707,8 @@ static unsigned getLargerAbsoluteValueFunction(unsigned AbsFunction) {
   case Builtin::BIllabs:
     return 0;
 
+  case Builtin::BIfabsh:
+    return Builtin::BIfabsf;
   case Builtin::BIfabsf:
     return Builtin::BIfabs;
   case Builtin::BIfabs:
@@ -9725,6 +9793,7 @@ static unsigned changeAbsFunction(unsigned AbsKind,
     switch (AbsKind) {
     default:
       return 0;
+    case Builtin::BI__builtin_fabsh:
     case Builtin::BI__builtin_fabsf:
     case Builtin::BI__builtin_fabs:
     case Builtin::BI__builtin_fabsl:
@@ -9732,6 +9801,7 @@ static unsigned changeAbsFunction(unsigned AbsKind,
     case Builtin::BI__builtin_cabs:
     case Builtin::BI__builtin_cabsl:
       return Builtin::BI__builtin_abs;
+    case Builtin::BIfabsh:
     case Builtin::BIfabsf:
     case Builtin::BIfabs:
     case Builtin::BIfabsl:
@@ -9766,6 +9836,7 @@ static unsigned changeAbsFunction(unsigned AbsKind,
     case Builtin::BI__builtin_abs:
     case Builtin::BI__builtin_labs:
     case Builtin::BI__builtin_llabs:
+    case Builtin::BI__builtin_fabsh:
     case Builtin::BI__builtin_fabsf:
     case Builtin::BI__builtin_fabs:
     case Builtin::BI__builtin_fabsl:
@@ -9773,6 +9844,7 @@ static unsigned changeAbsFunction(unsigned AbsKind,
     case Builtin::BIabs:
     case Builtin::BIlabs:
     case Builtin::BIllabs:
+    case Builtin::BIfabsh:
     case Builtin::BIfabsf:
     case Builtin::BIfabs:
     case Builtin::BIfabsl:
@@ -9792,6 +9864,7 @@ static unsigned getAbsoluteValueFunctionKind(const FunctionDecl *FDecl) {
     return 0;
   case Builtin::BI__builtin_abs:
   case Builtin::BI__builtin_fabs:
+  case Builtin::BI__builtin_fabsh:
   case Builtin::BI__builtin_fabsf:
   case Builtin::BI__builtin_fabsl:
   case Builtin::BI__builtin_labs:
@@ -9802,6 +9875,7 @@ static unsigned getAbsoluteValueFunctionKind(const FunctionDecl *FDecl) {
   case Builtin::BIabs:
   case Builtin::BIlabs:
   case Builtin::BIllabs:
+  case Builtin::BIfabsh:
   case Builtin::BIfabs:
   case Builtin::BIfabsf:
   case Builtin::BIfabsl:
diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp
index 0e6c933cd4f3..6a036069a4e5 100644
--- a/clang/lib/Sema/SemaExpr.cpp
+++ b/clang/lib/Sema/SemaExpr.cpp
@@ -3849,7 +3849,8 @@ ExprResult Sema::ActOnNumericConstant(const Token &Tok, Scope *UDLScope) {
   } else if (Literal.isFloatingLiteral()) {
     QualType Ty;
     if (Literal.isHalf){
-      if (getOpenCLOptions().isAvailableOption("cl_khr_fp16", getLangOpts()))
+      if (getOpenCLOptions().isAvailableOption("cl_khr_fp16", getLangOpts()) ||
+          (getLangOpts().Half && getLangOpts().NativeHalfType))
         Ty = Context.HalfTy;
       else {
         Diag(Tok.getLocation(), diag::err_half_const_requires_fp16);
@@ -4394,6 +4395,7 @@ static void captureVariablyModifiedType(ASTContext &Context, QualType T,
     case Type::Vector:
     case Type::ExtVector:
     case Type::ConstantMatrix:
+    case Type::Subword:
     case Type::Record:
     case Type::Enum:
     case Type::Elaborated:
@@ -5487,7 +5489,8 @@ Sema::CreateBuiltinArraySubscriptExpr(Expr *Base, SourceLocation LLoc,
   }
 
   // Perform default conversions.
-  if (!LHSExp->getType()->getAs<VectorType>()) {
+  if (!LHSExp->getType()->getAs<VectorType>() &&
+      !LHSExp->getType()->getAs<SubwordType>()) {
     ExprResult Result = DefaultFunctionArrayLvalueConversion(LHSExp);
     if (Result.isInvalid())
       return ExprError();
@@ -5589,6 +5592,29 @@ Sema::CreateBuiltinArraySubscriptExpr(Expr *Base, SourceLocation LLoc,
     BaseExpr = RHSExp;
     IndexExpr = LHSExp;
     ResultType = RHSTy->castAs<PointerType>()->getPointeeType();
+
+  } else if (const SubwordType *SWTy = LHSTy->getAs<SubwordType>()) {
+    BaseExpr = LHSExp;    // Subword: V[123]
+    IndexExpr = RHSExp;
+    // We apply C++ DR1213 to vector subscripting too.
+    if (getLangOpts().CPlusPlus11 && LHSExp->getValueKind() == VK_PRValue) {
+      ExprResult Materialized = TemporaryMaterializationConversion(LHSExp);
+      if (Materialized.isInvalid())
+        return ExprError();
+      LHSExp = Materialized.get();
+    }
+    VK = LHSExp->getValueKind();
+    if (VK != VK_PRValue)
+      OK = OK_VectorComponent;
+
+    ResultType = SWTy->getBasicType();
+    QualType BaseType = BaseExpr->getType();
+    Qualifiers BaseQuals = BaseType.getQualifiers();
+    Qualifiers MemberQuals = ResultType.getQualifiers();
+    Qualifiers Combined = BaseQuals + MemberQuals;
+    if (Combined != MemberQuals)
+      ResultType = Context.getQualifiedType(ResultType, Combined);
+
   } else {
     return ExprError(Diag(LLoc, diag::err_typecheck_subscript_value)
        << LHSExp->getSourceRange() << RHSExp->getSourceRange());
@@ -6522,6 +6548,44 @@ ExprResult Sema::BuildCallExpr(Scope *Scope, Expr *Fn, SourceLocation LParenLoc,
 
     FunctionDecl *FDecl = dyn_cast<FunctionDecl>(NDecl);
     if (FDecl && FDecl->getBuiltinID()) {
+
+    /* hack for updating the first argument of swarctrl builtin function (ORing input constant with flags defined by swar pragmas in the currect scope block) */
+      if (FDecl->getBuiltinID()==Builtin::BI__builtin_swarctrl) do {
+        unsigned swfl = 0;
+        if (Scope) {
+          DeclContext *dc = Scope->getFnParent()->getEntity();
+          if (dc && dc->swarPragmaLoc[DeclContext::SwarIndices::manualIdx].isValid() &&
+              dc->swarPragmaLoc[DeclContext::SwarIndices::manualIdx]<LParenLoc) {
+            dc->swarPragmaLoc[DeclContext::SwarIndices::manualIdx] = SourceLocation();
+            break;  /* skip automatic swarctrl */
+          }
+          if (dc && dc->swarPragmaLoc[DeclContext::SwarIndices::reduceIdx].isValid() &&
+              dc->swarPragmaLoc[DeclContext::SwarIndices::reduceIdx]<LParenLoc) {
+            dc->swarPragmaLoc[DeclContext::SwarIndices::reduceIdx] = SourceLocation();
+            swfl |= DeclContext::SwarFlags::reduceFlg;
+          }
+          if (dc && dc->swarPragmaLoc[DeclContext::SwarIndices::saturateIdx].isValid() &&
+              dc->swarPragmaLoc[DeclContext::SwarIndices::saturateIdx]<LParenLoc) {
+            dc->swarPragmaLoc[DeclContext::SwarIndices::saturateIdx] = SourceLocation();
+            swfl |= DeclContext::SwarFlags::saturateFlg;
+          }
+          if (dc && dc->swarPragmaLoc[DeclContext::SwarIndices::normalizeIdx].isValid() &&
+              dc->swarPragmaLoc[DeclContext::SwarIndices::normalizeIdx]<LParenLoc) {
+            dc->swarPragmaLoc[DeclContext::SwarIndices::normalizeIdx] = SourceLocation();
+            swfl |= DeclContext::SwarFlags::normalizeFlg;
+          }
+        }
+        if (ArgExprs[0]->isIntegerConstantExpr(Context, nullptr)) {
+          Optional<llvm::APSInt> argval = ArgExprs[0]->getIntegerConstantExpr(Context, nullptr, false);
+          ConstantExpr *CE = (ConstantExpr *)ArgExprs[0];
+          llvm::APSInt &aval = *argval;
+          aval |= llvm::APSInt::get(swfl).extOrTrunc(aval.getBitWidth());
+          // set updated argval value to the first argument - probably there is a better way how to do it
+          CE = ConstantExpr::Create(Context, CE, APValue(aval));
+          ArgExprs[0] = CE;
+        }
+      } while(0);
+
       // Rewrite the function decl for this builtin by replacing parameters
       // with no explicit address space with the address space of the arguments
       // in ArgExprs.
@@ -7597,6 +7661,84 @@ ExprResult Sema::CheckExtVectorCast(SourceRange R, QualType DestTy,
   return prepareVectorSplat(DestTy, CastExpr);
 }
 
+/* Subword */
+static bool breakDownSubwordType(QualType type, unsigned &bwd, unsigned &pck, QualType &btp) {
+  if (const SubwordType *swType = type->getAs<SubwordType>()) {
+    bwd = swType->getBitWidth();
+    pck = swType->getPacking();
+    btp = swType->getBasicType();
+    assert(btp->isScalarType());
+    return true;
+  }
+  // We allow conversion to and from non-vector types, but only if they're integer types (i.e. non-complex, non-pointer scalar types).
+  if (!type->isIntegerType()) return false;
+  bwd = 0;
+  pck = 1;
+  btp = type;
+  return true;
+}
+
+// both subword types have to contain the same number of elements in the basic type (packing) and the same width of elements
+// ... or the destination type has to the same or greater width and the same number of elements
+// ... or the size of
+bool Sema::areCompatibleSubwordTypes(QualType srcTy, QualType destTy) {
+  assert(destTy->isSubwordType() || srcTy->isSubwordType());
+  unsigned srcbitsz, destbitsz;
+  unsigned srcpack, destpack;
+  QualType srcbastp, destbastp;
+  if (!breakDownSubwordType(srcTy, srcbitsz, srcpack, srcbastp)) return false;
+  if (srcbitsz==0) srcbitsz = static_cast<unsigned>(Context.getTypeSize(srcTy));
+  if (!breakDownSubwordType(destTy, destbitsz, destpack, destbastp)) return false;
+  if (destbitsz==0) destbitsz = static_cast<unsigned>(Context.getTypeSize(destTy));
+
+  if (srcpack!=destpack) return false;
+  if (srcbitsz>destbitsz) return false;
+  return true;
+}
+
+bool Sema::CheckSubwordCast(SourceRange R, QualType SubwordTy, QualType Ty,
+                       CastKind &Kind)
+{
+  assert(SubwordTy->isSubwordType() && "Not a subword type!");
+
+  if (Ty->isSubwordType() || Ty->isIntegralType(Context)) {
+    if (!areCompatibleSubwordTypes(Ty, SubwordTy))
+      return Diag(R.getBegin(),
+                  Ty->isSubwordType() ?
+                  diag::err_invalid_conversion_between_subwords :
+                  diag::err_invalid_conversion_between_subword_and_integer)
+        << SubwordTy << Ty << R;
+  } else {
+    return Diag(R.getBegin(),
+                diag::err_invalid_conversion_between_subword_and_scalar)
+      << SubwordTy << Ty << R;
+  }
+
+  Kind = CK_BitCast;
+  return false;
+}
+
+ExprResult Sema::prepareSubwordSplat(QualType SubwordTy, Expr *SplattedExpr)
+{
+  QualType DestBasicTy = SubwordTy->castAs<SubwordType>()->getBasicType();
+  unsigned DestBitWidth = SubwordTy->castAs<SubwordType>()->getBitWidth();
+  QualType SWcanTy = SubwordTy.getCanonicalType();
+
+  if (DestBasicTy == SplattedExpr->getType())
+    return SplattedExpr;
+
+  assert(DestBasicTy->isIntegralOrEnumerationType());
+
+  CastKind CK;
+  ExprResult CastExprRes = SplattedExpr;
+  CK = PrepareScalarCast(CastExprRes, DestBasicTy);
+  if (CastExprRes.isInvalid())
+    return ExprError();
+  SplattedExpr = CastExprRes.get();
+  return ImpCastExprToType(SplattedExpr, DestBasicTy, CK);
+}
+/* Subword - end */
+
 ExprResult
 Sema::ActOnCastExpr(Scope *S, SourceLocation LParenLoc,
                     Declarator &D, ParsedType &Ty,
@@ -7829,6 +7971,17 @@ static bool checkCondition(Sema &S, Expr *Cond, SourceLocation QuestionLoc) {
     return true;
   }
 
+  // daiteq packed half/single
+  if ((S.Context.getTargetInfo().getTriple().getArch() == llvm::Triple::sparc ||
+       S.Context.getTargetInfo().getTriple().getArch() == llvm::Triple::riscv32 ||
+       S.Context.getTargetInfo().getTriple().getArch() == llvm::Triple::riscv64) &&
+      S.Context.getTargetInfo().getTriple().getVendor() == llvm::Triple::Daiteq) {
+    if (CondTy->isVectorType()) {
+      QualType ElmTy = CondTy->castAs<VectorType>()->getElementType();
+      if (ElmTy->isFloatingType()) return true;
+    }
+  }
+
   // C99 6.5.15p2
   if (CondTy->isScalarType()) return false;
 
@@ -9481,6 +9634,15 @@ Sema::CheckAssignmentConstraints(QualType LHSType, ExprResult &RHS,
     return Compatible;
   }
 
+  if (LHSType->isSubwordType() && RHSType->isIntegerType()) {
+    Kind = CK_IntegralCast;
+    return Compatible;
+  }
+  if (LHSType->isIntegerType() && RHSType->isSubwordType()) { // convert subword to integer ... is used in 'sw_16b2[3] = (sw_b2)2
+    Kind = CK_UserDefinedConversion;
+    return Compatible;
+  }
+
   return Incompatible;
 }
 
@@ -10238,6 +10400,51 @@ QualType Sema::CheckVectorOperands(ExprResult &LHS, ExprResult &RHS,
   return QualType();
 }
 
+// Check operands for operations with subword types
+QualType Sema::CheckSubwordOperands(ExprResult &LHS, ExprResult &RHS,
+                                    SourceLocation Loc, bool IsCompAssign) {
+
+  QualType LHSType = LHS.get()->getType().getUnqualifiedType();
+  QualType RHSType = RHS.get()->getType().getUnqualifiedType();
+
+
+  const SubwordType *LHSSWType;
+  const SubwordType *RHSSWType;
+
+  if (LHSType->isArrayType()) {
+    LHSSWType = Context.getAsArrayType(LHSType)->getElementType()->getAs<SubwordType>();
+  } else {
+    LHSSWType = LHSType->getAs<SubwordType>();
+  }
+
+  if (RHSType->isArrayType()) {
+    RHSSWType = Context.getAsArrayType(RHSType)->getElementType()->getAs<SubwordType>();
+  } else {
+    RHSSWType = RHSType->getAs<SubwordType>();
+  }
+
+  assert(LHSSWType || RHSSWType);
+
+  // If the subword types are identical, return.
+  if (Context.hasSameType(LHSType, RHSType))
+    return LHSType;
+
+  // Combinations of subword types are not allowed now
+  if (LHSSWType->getPacking() == RHSSWType->getPacking()) {
+    if (RHSSWType->getBitWidth()>LHSSWType->getBitWidth())
+      return RHSType;
+    else
+      return LHSType;
+  }
+
+  // Otherwise, use generic diagnostic.
+  Diag(Loc, diag::err_typecheck_subword_length_not_equal)
+        << LHSSWType->getPacking() << RHSSWType->getPacking();
+  return QualType();
+}
+
+
+
 // checkArithmeticNull - Detect when a NULL constant is used improperly in an
 // expression.  These are mainly cases where the null pointer is used as an
 // integer instead of a pointer.
@@ -10343,6 +10550,11 @@ QualType Sema::CheckMultiplyDivideOperands(ExprResult &LHS, ExprResult &RHS,
                                            bool IsCompAssign, bool IsDiv) {
   checkArithmeticNull(*this, LHS, RHS, Loc, /*IsCompare=*/false);
 
+  if (LHS.get()->getType()->isSubwordType() &&
+      RHS.get()->getType()->isSubwordType()) {
+    return CheckSubwordOperands(LHS, RHS, Loc, IsCompAssign);
+  }
+
   QualType LHSTy = LHS.get()->getType();
   QualType RHSTy = RHS.get()->getType();
   if (LHSTy->isVectorType() || RHSTy->isVectorType())
@@ -10700,6 +10912,24 @@ QualType Sema::CheckAdditionOperands(ExprResult &LHS, ExprResult &RHS,
     return compType;
   }
 
+  if (LHS.get()->getType()->isSubwordType() &&
+      RHS.get()->getType()->isSubwordType()) {
+    QualType compType = CheckSubwordOperands(LHS, RHS, Loc, CompLHSTy);
+    if (CompLHSTy) *CompLHSTy = compType;
+    return compType;
+  }
+
+  if (LHS.get()->getType()->isArrayType() && RHS.get()->getType()->isArrayType()) {
+    const ArrayType *LHSArrTy = Context.getAsArrayType(LHS.get()->getType());
+    const ArrayType *RHSArrTy = Context.getAsArrayType(RHS.get()->getType());
+    if (LHSArrTy->getElementType()->isSubwordType() &&
+        RHSArrTy->getElementType()->isSubwordType()) {
+      QualType compType = CheckSubwordOperands(LHS, RHS, Loc, CompLHSTy);
+      if (CompLHSTy) *CompLHSTy = compType;
+      return compType;
+    }
+  }
+
   QualType compType = UsualArithmeticConversions(
       LHS, RHS, Loc, CompLHSTy ? ACK_CompAssign : ACK_Arithmetic);
   if (LHS.isInvalid() || RHS.isInvalid())
@@ -10804,6 +11034,28 @@ QualType Sema::CheckSubtractionOperands(ExprResult &LHS, ExprResult &RHS,
     return compType;
   }
 
+  // direct subword types
+  if (LHS.get()->getType()->isSubwordType() &&
+      RHS.get()->getType()->isSubwordType()) {
+    theLastSubwordOperation = 2; // subtraction
+    QualType compType = CheckSubwordOperands(LHS, RHS, Loc, CompLHSTy);
+    if (CompLHSTy) *CompLHSTy = compType;
+    return compType;
+  }
+
+  // array of subwords types
+  if (LHS.get()->getType()->isArrayType() && RHS.get()->getType()->isArrayType()) {
+    const ArrayType *LHSArrTy = Context.getAsArrayType(LHS.get()->getType());
+    const ArrayType *RHSArrTy = Context.getAsArrayType(RHS.get()->getType());
+    if (LHSArrTy->getElementType()->isSubwordType() &&
+        RHSArrTy->getElementType()->isSubwordType()) {
+      theLastSubwordOperation = 2; // sub (array)
+      QualType compType = CheckSubwordOperands(LHS, RHS, Loc, CompLHSTy);
+      if (CompLHSTy) *CompLHSTy = compType;
+      return compType;
+    }
+  }
+
   QualType compType = UsualArithmeticConversions(
       LHS, RHS, Loc, CompLHSTy ? ACK_CompAssign : ACK_Arithmetic);
   if (LHS.isInvalid() || RHS.isInvalid())
@@ -11796,6 +12048,10 @@ QualType Sema::CheckCompareOperands(ExprResult &LHS, ExprResult &RHS,
     CheckPtrComparisonWithNullChar(RHS, LHS);
   }
 
+  if (LHS.get()->getType()->isSubwordType() &&
+      RHS.get()->getType()->isSubwordType()) {
+    return CheckSubwordCompareOperands(LHS, RHS, Loc, Opc);
+  }
   // Handle vector comparisons separately.
   if (LHS.get()->getType()->isVectorType() ||
       RHS.get()->getType()->isVectorType())
@@ -12214,6 +12470,37 @@ QualType Sema::CheckCompareOperands(ExprResult &LHS, ExprResult &RHS,
   return InvalidOperands(Loc, LHS, RHS);
 }
 
+/// CheckSubwordCompareOperands - subword comparisons are a clang extension that
+/// operates on subword types. It produces an IntTy result like a scalar
+/// comparison only for EQ,NEQ comparision.
+QualType Sema::CheckSubwordCompareOperands(ExprResult &LHS, ExprResult &RHS,
+                                           SourceLocation Loc, BinaryOperatorKind Opc)
+{
+  if (Opc == BO_Cmp) {
+    Diag(Loc, diag::err_three_way_vector_comparison);
+    return QualType();
+  }
+
+  // Check to make sure we're operating on vectors of the same type and width,
+  // Allowing one side to be a scalar of element type.
+  QualType vType = CheckSubwordOperands(LHS, RHS, Loc, /*isCompAssign*/false);
+  if (vType.isNull())
+    return vType;
+
+  QualType LHSType = LHS.get()->getType();
+
+  // For non-floating point types, check for self-comparisons of the form
+  // x == x, x != x, x < x, etc.  These always evaluate to a constant, and
+  // often indicate logic errors in the program.
+  diagnoseTautologicalComparison(*this, Loc, LHS.get(), RHS.get(), Opc);
+
+  if (BinaryOperator::isEqualityOp(Opc)) {
+    return Context.IntTy;
+  }
+  // Return a signed type for the vector.
+  return QualType();
+}
+
 // Return a signed ext_vector_type that is of identical size and number of
 // elements. For floating point vectors, return an integer type of identical
 // size and number of elements. In the non ext_vector_type case, search from
@@ -12224,6 +12511,18 @@ QualType Sema::GetSignedVectorType(QualType V) {
   unsigned TypeSize = Context.getTypeSize(VTy->getElementType());
 
   if (isa<ExtVectorType>(VTy)) {
+
+if (Context.getTargetInfo().getTriple().getVendor()==llvm::Triple::Daiteq) {
+    // packed single
+    if (VTy->getElementType()==Context.FloatTy && VTy->getNumElements()==2) {
+      return Context.IntTy;
+    }
+    // packed half
+    if (VTy->getElementType()==Context.HalfTy && VTy->getNumElements()==2) {
+      return Context.IntTy;
+    }
+}
+
     if (TypeSize == Context.getTypeSize(Context.CharTy))
       return Context.getExtVectorType(Context.CharTy, VTy->getNumElements());
     else if (TypeSize == Context.getTypeSize(Context.ShortTy))
diff --git a/clang/lib/Sema/SemaInit.cpp b/clang/lib/Sema/SemaInit.cpp
index 78574e34d906..4da527d909a8 100644
--- a/clang/lib/Sema/SemaInit.cpp
+++ b/clang/lib/Sema/SemaInit.cpp
@@ -337,6 +337,13 @@ class InitListChecker {
                        InitListExpr *IList, QualType DeclType, unsigned &Index,
                        InitListExpr *StructuredList,
                        unsigned &StructuredIndex);
+
+  void CheckSubwordType(const InitializedEntity &Entity,
+                        InitListExpr *IList, QualType DeclType,
+                        unsigned &Index,
+                        InitListExpr *StructuredList,
+                        unsigned &StructuredIndex);
+
   void CheckStructUnionTypes(const InitializedEntity &Entity,
                              InitListExpr *IList, QualType DeclType,
                              CXXRecordDecl::base_class_range Bases,
@@ -1132,6 +1139,7 @@ static void warnBracedScalarInit(Sema &S, const InitializedEntity &Entity,
   unsigned DiagID = 0;
 
   switch (Entity.getKind()) {
+  case InitializedEntity::EK_SubWordElement:
   case InitializedEntity::EK_VectorElement:
   case InitializedEntity::EK_ComplexElement:
   case InitializedEntity::EK_ArrayElement:
@@ -1327,7 +1335,11 @@ void InitListChecker::CheckListElementTypes(const InitializedEntity &Entity,
     // Checks for scalar type are sufficient for these types too.
     CheckScalarType(Entity, IList, DeclType, Index, StructuredList,
                     StructuredIndex);
+  } else if (DeclType->isSubwordType()) {
+    CheckSubwordType(Entity, IList, DeclType, Index,
+                    StructuredList, StructuredIndex);
   } else {
+
     if (!VerifyOnly)
       SemaRef.Diag(IList->getBeginLoc(), diag::err_illegal_initializer_type)
           << DeclType;
@@ -1829,6 +1841,48 @@ void InitListChecker::CheckVectorType(const InitializedEntity &Entity,
   }
 }
 
+void InitListChecker::CheckSubwordType(const InitializedEntity &Entity,
+                                      InitListExpr *IList, QualType DeclType,
+                                      unsigned &Index,
+                                      InitListExpr *StructuredList,
+                                      unsigned &StructuredIndex) {
+  const SubwordType *SubT = DeclType->castAs<SubwordType>();
+  unsigned maxElements = SubT->getPacking();
+  unsigned elmBitSize = SubT->getBitWidth();
+  unsigned numEltsInit = 0;
+  QualType basicType = SubT->getBasicType();
+
+  if (maxElements==0) { /* compute number of elements from sizeof(basicType) and elmBits */
+    unsigned basTpSz = SemaRef.Context.getTypeSize(basicType);
+    maxElements = basTpSz/elmBitSize;
+  }
+  if (Index >= IList->getNumInits()) {
+    // Make sure the element type can be value-initialized.
+    CheckEmptyInitializable(
+        InitializedEntity::InitializeElement(SemaRef.Context, 0, Entity),
+        IList->getEndLoc());
+    return;
+  }
+
+  InitializedEntity ElementEntity =
+    InitializedEntity::InitializeElement(SemaRef.Context, 0, Entity);
+
+  // OpenCL initializers allows vectors to be constructed from vectors.
+  for (unsigned i = 0; i < maxElements; ++i) {
+    // Don't attempt to go past the end of the init list
+    if (Index >= IList->getNumInits())
+      break;
+
+    ElementEntity.setElementIndex(Index);
+
+    QualType IType = IList->getInit(Index)->getType();
+    CheckSubElementType(ElementEntity, IList, basicType, Index,  /* basicType should be elementType */
+                        StructuredList, StructuredIndex);
+    ++numEltsInit;
+  }
+}
+
+
 /// Check if the type of a class element has an accessible destructor, and marks
 /// it referenced. Returns true if we shouldn't form a reference to the
 /// destructor.
@@ -3278,6 +3332,9 @@ InitializedEntity::InitializedEntity(ASTContext &Context, unsigned Index,
   } else if (const VectorType *VT = Parent.getType()->getAs<VectorType>()) {
     Kind = EK_VectorElement;
     Type = VT->getElementType();
+  } else if (const SubwordType *SWT = Parent.getType()->getAs<SubwordType>()) {
+    Kind = EK_SubWordElement;
+    Type = SWT->getBasicType();
   } else {
     const ComplexType *CT = Parent.getType()->getAs<ComplexType>();
     assert(CT && "Unexpected type");
@@ -3325,6 +3382,7 @@ DeclarationName InitializedEntity::getName() const {
   case EK_Delegating:
   case EK_ArrayElement:
   case EK_VectorElement:
+  case EK_SubWordElement:
   case EK_ComplexElement:
   case EK_BlockElement:
   case EK_LambdaToBlockConversionBlockElement:
@@ -3357,6 +3415,7 @@ ValueDecl *InitializedEntity::getDecl() const {
   case EK_Delegating:
   case EK_ArrayElement:
   case EK_VectorElement:
+  case EK_SubWordElement:
   case EK_ComplexElement:
   case EK_BlockElement:
   case EK_LambdaToBlockConversionBlockElement:
@@ -3389,6 +3448,7 @@ bool InitializedEntity::allowsNRVO() const {
   case EK_Delegating:
   case EK_ArrayElement:
   case EK_VectorElement:
+  case EK_SubWordElement:
   case EK_ComplexElement:
   case EK_BlockElement:
   case EK_LambdaToBlockConversionBlockElement:
@@ -3425,6 +3485,7 @@ unsigned InitializedEntity::dumpImpl(raw_ostream &OS) const {
   case EK_Delegating: OS << "Delegating"; break;
   case EK_ArrayElement: OS << "ArrayElement " << Index; break;
   case EK_VectorElement: OS << "VectorElement " << Index; break;
+  case EK_SubWordElement: OS << "SubWordElement " << Index; break;
   case EK_ComplexElement: OS << "ComplexElement " << Index; break;
   case EK_BlockElement: OS << "Block"; break;
   case EK_LambdaToBlockConversionBlockElement:
@@ -6092,6 +6153,7 @@ getAssignmentAction(const InitializedEntity &Entity, bool Diagnose = false) {
   case InitializedEntity::EK_Binding:
   case InitializedEntity::EK_ArrayElement:
   case InitializedEntity::EK_VectorElement:
+  case InitializedEntity::EK_SubWordElement:
   case InitializedEntity::EK_ComplexElement:
   case InitializedEntity::EK_BlockElement:
   case InitializedEntity::EK_LambdaToBlockConversionBlockElement:
@@ -6116,6 +6178,7 @@ static bool shouldBindAsTemporary(const InitializedEntity &Entity) {
   case InitializedEntity::EK_Base:
   case InitializedEntity::EK_Delegating:
   case InitializedEntity::EK_VectorElement:
+  case InitializedEntity::EK_SubWordElement:
   case InitializedEntity::EK_ComplexElement:
   case InitializedEntity::EK_Exception:
   case InitializedEntity::EK_BlockElement:
@@ -6146,6 +6209,7 @@ static bool shouldDestroyEntity(const InitializedEntity &Entity) {
     case InitializedEntity::EK_Base:
     case InitializedEntity::EK_Delegating:
     case InitializedEntity::EK_VectorElement:
+    case InitializedEntity::EK_SubWordElement:
     case InitializedEntity::EK_ComplexElement:
     case InitializedEntity::EK_BlockElement:
     case InitializedEntity::EK_LambdaToBlockConversionBlockElement:
@@ -6197,6 +6261,7 @@ static SourceLocation getInitializationLoc(const InitializedEntity &Entity,
   case InitializedEntity::EK_Base:
   case InitializedEntity::EK_Delegating:
   case InitializedEntity::EK_VectorElement:
+  case InitializedEntity::EK_SubWordElement:
   case InitializedEntity::EK_ComplexElement:
   case InitializedEntity::EK_BlockElement:
   case InitializedEntity::EK_LambdaToBlockConversionBlockElement:
@@ -6751,6 +6816,7 @@ static LifetimeResult getEntityLifetime(
   case InitializedEntity::EK_LambdaToBlockConversionBlockElement:
   case InitializedEntity::EK_LambdaCapture:
   case InitializedEntity::EK_VectorElement:
+  case InitializedEntity::EK_SubWordElement:
   case InitializedEntity::EK_ComplexElement:
     return {nullptr, LK_FullExpression};
 
diff --git a/clang/lib/Sema/SemaLookup.cpp b/clang/lib/Sema/SemaLookup.cpp
index 5e8c4de61e5d..431ff7ec9b6a 100644
--- a/clang/lib/Sema/SemaLookup.cpp
+++ b/clang/lib/Sema/SemaLookup.cpp
@@ -2934,6 +2934,7 @@ addAssociatedClassesAndNamespaces(AssociatedLookup &Result, QualType Ty) {
     case Type::ExtVector:
     case Type::ConstantMatrix:
     case Type::Complex:
+    case Type::Subword:
     case Type::ExtInt:
       break;
 
diff --git a/clang/lib/Sema/SemaStmt.cpp b/clang/lib/Sema/SemaStmt.cpp
index 3baccec2d7bb..6d0fde3f767d 100644
--- a/clang/lib/Sema/SemaStmt.cpp
+++ b/clang/lib/Sema/SemaStmt.cpp
@@ -43,6 +43,109 @@
 using namespace clang;
 using namespace sema;
 
+
+/* check if @SubStmt is a subword variable or array of subwords (one element or the whole array)
+ * SubStmt is a
+ * - DeclRefExpr - direct reference to variable (return 1)
+ * - ArraySubscriptExpr - indexed element in an array (return 2)
+ * - ArrayType ... - TODO (return 3)
+ * - others (return 0)
+ * outBitWidth - buffer for bitwidth of subword type (or NULL)
+ * isSigned - buffer for flag if subword is signed (or NULL)
+ */
+int Sema::CheckSwarOperandType(Stmt *SubStmt, int *outBitWidth, bool *isSigned)
+{
+  if (!getLangOpts().EnabledSWARdaiteq) return 0; /* skip checking if swar is not required */
+  /* check direct reference to variable */
+  if (const auto *BchDEC = dyn_cast<DeclRefExpr>(SubStmt)) {
+    if (BchDEC->getDecl()->getType().getTypePtr()->isSubwordType()) {
+      const SubwordType *SWTy = BchDEC->getDecl()->getType().getTypePtr()->castAs<SubwordType>();
+      if (outBitWidth) *outBitWidth = SWTy->getBitWidth();
+      if (isSigned) {
+        QualType qtp = SWTy->getBasicType();
+        const Type *btp = qtp.getTypePtrOrNull();
+        if (btp && btp->isSignedIntegerType())
+          *isSigned = true;
+        else
+          *isSigned = false;
+      }
+      return 1;
+    }
+  }
+  /* check array */
+  if (const auto *BchARR = dyn_cast<ArraySubscriptExpr>(SubStmt)) {
+    const Type *PTp = BchARR->getBase()->getType().getTypePtr();
+    if (PTp->isPointerType()) {
+      PTp = PTp->getPointeeType().getTypePtr();
+    }
+    if (PTp->isSubwordType()) {
+      const SubwordType *SWTy = PTp->castAs<SubwordType>();
+      if (outBitWidth) *outBitWidth = SWTy->getBitWidth();
+      if (isSigned) {
+        QualType qtp = SWTy->getBasicType();
+        const Type *btp = qtp.getTypePtrOrNull();
+        if (btp && btp->isSignedIntegerType())
+          *isSigned = true;
+        else
+          *isSigned = false;
+      }
+      return 2;
+    }
+  }
+  return 0;
+}
+
+/* insert automatically generated instruction for SWAR configuration */
+Stmt *Sema::BuildSwarCtrlComp(Stmt *SubStmt, SourceLocation pos, int swop) {
+  StringRef swarctrlName = "__builtin_swarctrl";
+  LookupResult R(*this, &Context.Idents.get(swarctrlName), SubStmt->getBeginLoc(), Sema::LookupOrdinaryName);
+  LookupName(R, TUScope, true);
+  FunctionDecl *SwarCtrl = R.getAsSingle<FunctionDecl>();
+  ExprResult SwarCtrlRef = BuildDeclRefExpr(SwarCtrl, Context.BuiltinFnTy, VK_PRValue, SubStmt->getBeginLoc(), nullptr);
+
+  Scope *curscope = getCurScope();
+  if (curscope) {
+    DeclContext *dc = curscope->getFnParent()->getEntity();
+    if (dc && dc->swarPragmaLoc[DeclContext::SwarIndices::manualIdx].isValid() &&
+        dc->swarPragmaLoc[DeclContext::SwarIndices::manualIdx]<SubStmt->getBeginLoc()) {
+      dc->swarPragmaLoc[DeclContext::SwarIndices::manualIdx] = SourceLocation();
+      return SubStmt; /* skip automatic swarctrl */
+    }
+
+    unsigned swfl = 0;
+    if (dc && dc->swarPragmaLoc[DeclContext::SwarIndices::reduceIdx].isValid() &&
+        dc->swarPragmaLoc[DeclContext::SwarIndices::reduceIdx]<SubStmt->getBeginLoc()) {
+      dc->swarPragmaLoc[DeclContext::SwarIndices::reduceIdx] = SourceLocation();
+      swfl |= DeclContext::SwarFlags::reduceFlg;
+    }
+    if (dc && dc->swarPragmaLoc[DeclContext::SwarIndices::saturateIdx].isValid() &&
+        dc->swarPragmaLoc[DeclContext::SwarIndices::saturateIdx]<SubStmt->getBeginLoc()) {
+      dc->swarPragmaLoc[DeclContext::SwarIndices::saturateIdx] = SourceLocation();
+      swfl |= DeclContext::SwarFlags::saturateFlg;
+    }
+    if (dc && dc->swarPragmaLoc[DeclContext::SwarIndices::normalizeIdx].isValid() &&
+        dc->swarPragmaLoc[DeclContext::SwarIndices::normalizeIdx]<SubStmt->getBeginLoc()) {
+      dc->swarPragmaLoc[DeclContext::SwarIndices::normalizeIdx] = SourceLocation();
+      swfl |= DeclContext::SwarFlags::normalizeFlg;
+    }
+    swop |= swfl;
+  } else {
+    //fprintf(stderr, "no scope for swarflags\n");
+  }
+
+
+  llvm::APInt swcval(Context.getTypeSize(Context.IntTy), swop);
+  Expr *CallArgs[] = {
+    IntegerLiteral::Create(Context, swcval, Context.IntTy, SubStmt->getBeginLoc())
+  };
+  ExprResult Call = BuildCallExpr(/*Scope=*/nullptr, SwarCtrlRef.get(),
+                                    SubStmt->getBeginLoc(), CallArgs, SubStmt->getBeginLoc());
+  llvm::SmallVector<Stmt*, 16> nwcpmstmt;
+  nwcpmstmt.push_back(Call.getAs<Stmt>());
+  nwcpmstmt.push_back(SubStmt);
+  return CompoundStmt::Create(Context, nwcpmstmt, SubStmt->getBeginLoc(), SubStmt->getEndLoc());
+}
+
 StmtResult Sema::ActOnExprStmt(ExprResult FE, bool DiscardedValue) {
   if (FE.isInvalid())
     return StmtError();
@@ -434,7 +537,28 @@ StmtResult Sema::ActOnCompoundStmt(SourceLocation L, SourceLocation R,
       DiagnoseEmptyLoopBody(Elts[i], Elts[i + 1]);
   }
 
-  return CompoundStmt::Create(Context, Elts, L, R);
+  StmtResult sr = CompoundStmt::Create(Context, Elts, L, R);
+
+  if (getLangOpts().EnabledSWARdaiteq) {
+/* search SWAR operations and add swarctrl cmd */
+/* skip compound stmt in for loop */
+    Scope *psc = getCurScope()->getParent();
+    if (!((psc->getFlags() & Scope::ScopeFlags::ContinueScope) &&
+        (getCurScope()->getFlags() & Scope::ScopeFlags::CompoundStmtScope)) ) {
+      Stmt::child_iterator schi = sr.get()->child_begin();
+      while (schi!=sr.get()->child_end()) {
+        Stmt *SubStmt = *schi;
+        int swop = CheckSwarOperation(SubStmt);
+
+        if (swop>=0) {
+          *schi = BuildSwarCtrlComp(SubStmt, L, swop);
+        }
+        schi++;
+      }
+    }
+  }
+
+  return sr;
 }
 
 ExprResult
@@ -2091,6 +2215,243 @@ void Sema::CheckBreakContinueBinding(Expr *E) {
   }
 }
 
+
+
+Stmt *Sema::CheckAndAddSwarCtrlOp(const BinaryOperator *BO, Stmt *SubStmt, bool *already, int *swop)
+{
+  if (BO->getOpcode()==BO_Assign ||
+      BO->getOpcode()==BO_MulAssign ||
+      BO->getOpcode()==BO_AddAssign ||
+      BO->getOpcode()==BO_SubAssign) { /* R = XXX , R += XXX , R-= XXX , R *= XXX */
+    int boidx = 0; /* 0 is result, 1 is a part of computation for operator '=' */
+    int swoparrtype = -1;
+    int swoptype = -1;
+    int subwordop = 0;
+    bool subsign = false;
+/* TODO: check if sign/unsign is used correctly */
+    for (Stmt *bchild: SubStmt->children()) {
+      if (boidx==0) {
+        int subtp;
+        bool issign = false;
+        int swt = CheckSwarOperandType(bchild, &subtp, &issign);
+        subsign = issign;
+        if (swt==1) {         // direct var
+          swoptype = subtp;
+        } else if (swt==2) {  // array element
+          swoparrtype = subtp;
+        }
+      }
+      if (boidx==1) {
+        // test for binary operation
+        if (const auto *BchBO = dyn_cast<BinaryOperator>(bchild)) {
+          int lsubtp, rsubtp;
+          int lswt, rswt;
+          bool lsubsig, rsubsig;
+          lswt = CheckSwarOperandType(BchBO->getLHS(), &lsubtp, &lsubsig);
+          rswt = CheckSwarOperandType(BchBO->getRHS(), &rsubtp, &rsubsig);
+          if (lswt>0 && rswt==lswt && lsubsig==rsubsig) {
+            switch (BchBO->getOpcode()) {
+              case BO_Add: subwordop=1; break;
+              case BO_Sub: subwordop=2; break;
+              case BO_Mul: subwordop=3; break;
+              default:
+                break;
+            }
+          }
+        }
+      }
+
+      /* block is a swar operation on an array x[i] = a[i] <+/-/*> b[i] */
+      if (swoparrtype>=0 && subwordop) {
+        if (*swop>=0) {  /* another swar operation on an array (swarctrl is already before loop) */
+          Diag(SubStmt->getBeginLoc(), diag::warn_subword_crossover);
+          return NULL;
+        }
+        if (*already) {  /* a local swar operation in the loop (swarctrl is already in the loop) */
+          Diag(SubStmt->getBeginLoc(), diag::warn_subword_crossover);
+          return NULL;
+        }
+        switch (subwordop) {
+          case 1: *swop = SWAR_CTRL_OP_ADD; break; // SWADD
+          case 2: *swop = SWAR_CTRL_OP_SUB; break; // SWSUB
+          case 3: *swop = SWAR_CTRL_OP_MUL; break; // SWMUL
+        }
+        if (subsign) *swop |= SWAR_CTRL_SIGNED;
+        switch ((unsigned)getLangOpts().UseSWARUnit) {
+          default: /* SwarKind::SWAR_Unit_ByType = by variable type */
+            if (swoparrtype==16)
+              *swop |= SWAR_CTRL_AUDIO;
+            else if (swoparrtype==8)
+              *swop |= SWAR_CTRL_VIDEO;
+            else
+              *swop |= SWAR_CTRL_ALU;
+            break;
+          case llvm::SwarKinds::Audio:
+            *swop |= SWAR_CTRL_AUDIO;
+            break;
+          case llvm::SwarKinds::Video:
+            *swop |= SWAR_CTRL_VIDEO;
+            break;
+          case llvm::SwarKinds::ALU:
+            *swop |= SWAR_CTRL_ALU;
+            break;
+        }
+      }
+
+      /* block is a local swar operation on direct subword var x = a <+/-/*> b  */
+      if (swoptype>=0 && subwordop) {
+        if (*swop>=0) {  /* swar operation on an array is already in the loop */
+          Diag(SubStmt->getBeginLoc(), diag::warn_subword_crossover);
+          return NULL;
+        }
+        *already = true;
+        /* insert swarctrl builtin function before this SubStmt block */
+        /* create CompoundStmt from calling swarctrl and the original BinaryOperation(subword) */
+        /* exchange the original stmt with the created compound stmt */
+        if (swoptype>0 && subwordop) {
+          int swctrl = 0;
+          switch (subwordop) {
+            case 1: swctrl = SWAR_CTRL_OP_ADD; break; // SWADD
+            case 2: swctrl = SWAR_CTRL_OP_SUB; break; // SWSUB
+            case 3: swctrl = SWAR_CTRL_OP_MUL; break; // SWMUL
+          }
+          if (subsign) swctrl |= SWAR_CTRL_SIGNED;
+          switch ((unsigned)getLangOpts().UseSWARUnit) {
+            default: /* SwarKind::SWAR_Unit_ByType = by variable type */
+              if (swoptype==16)
+                swctrl |= SWAR_CTRL_AUDIO;
+              else if (swoptype==8)
+                swctrl |= SWAR_CTRL_VIDEO;
+              else
+                swctrl |= SWAR_CTRL_ALU;
+              break;
+            case llvm::SwarKinds::Audio:
+              swctrl |= SWAR_CTRL_AUDIO;
+              break;
+            case llvm::SwarKinds::Video:
+              swctrl |= SWAR_CTRL_VIDEO;
+              break;
+            case llvm::SwarKinds::ALU:
+              swctrl |= SWAR_CTRL_ALU;
+              break;
+          }
+          SubStmt = BuildSwarCtrlComp(SubStmt, SubStmt->getBeginLoc(), swctrl);
+          break;
+        }
+      }
+
+      boidx++;
+    }
+  }
+  return SubStmt;
+}
+
+// The function tries to find a binary operation with subword arguments in the FOR stmt
+// block - only on the first level of hierarchy.
+int Sema::CheckSwarArrayOperation(Stmt *block) {
+  int swop = -1;
+  bool locswop = false; /* local swarctrl in a loop */
+
+  if (const auto *BO = dyn_cast<BinaryOperator>(block)) {
+    block = CheckAndAddSwarCtrlOp(BO, block, &locswop, &swop);
+    if (block==NULL) return swop;
+
+  } else {
+    Stmt::child_iterator chi = block->child_begin();
+    while (chi!=block->child_end()) {
+      if (*chi) {
+        Stmt *SubStmt = *chi;
+        if (const auto *BO = dyn_cast<BinaryOperator>(SubStmt)) {
+          *chi = CheckAndAddSwarCtrlOp(BO, SubStmt, &locswop, &swop);
+          if (*chi==NULL) return swop;
+
+        }
+      }
+      chi++;
+    }
+  }
+  return swop;
+}
+
+//  The function finds swar operations (without for loops)
+int Sema::CheckSwarOperation(Stmt *sop) {
+  int swop = -1;
+
+  if (const auto *BO = dyn_cast<BinaryOperator>(sop)) {
+    if (BO->getOpcode()==BO_Assign ||
+        BO->getOpcode()==BO_MulAssign ||
+        BO->getOpcode()==BO_AddAssign ||
+        BO->getOpcode()==BO_SubAssign) { /* R = XXX , R += XXX , R-= XXX , R *= XXX */
+      int boidx = 0; /* 0 is result, 1 is part of computation for operator '=' */
+      int swoptype = -1;
+      int subwordop = 0;
+      bool subsign = false;
+
+      for (Stmt *bchild: sop->children()) {
+        if (boidx==0) { // result - is it a subword type ?
+          int swbit;
+          int swtp = CheckSwarOperandType(bchild, &swbit, &subsign);
+          if (swtp==1) // direct variable
+            swoptype = swbit;
+          else if (swtp==2) // array type
+            swoptype = swbit;
+        }
+        if (boidx==1) { // operation + arguments
+          // test for binary operation
+          if (const auto *BchBO = dyn_cast<BinaryOperator>(bchild)) {
+            int lsubtp, rsubtp;
+            int lswt, rswt;
+            bool lsubsig, rsubsig;
+            lswt = CheckSwarOperandType(BchBO->getLHS(), &lsubtp, &lsubsig);
+            rswt = CheckSwarOperandType(BchBO->getRHS(), &rsubtp, &rsubsig);
+            if (lswt>0 && rswt==lswt && lsubsig==rsubsig) {
+              switch (BchBO->getOpcode()) {
+                case BO_Add: subwordop=1; break;
+                case BO_Sub: subwordop=2; break;
+                case BO_Mul: subwordop=3; break;
+                default:
+                  break;
+              }
+            }
+          }
+        }
+
+        /* block is a local swar operation on direct subword var x = a <+/-/*> b  */
+        if (swoptype>0 && subwordop) {
+          switch (subwordop) {
+            case 1: swop = SWAR_CTRL_OP_ADD; break; // SWADD
+            case 2: swop = SWAR_CTRL_OP_SUB; break; // SWSUB
+            case 3: swop = SWAR_CTRL_OP_MUL; break; // SWMUL
+          }
+          if (subsign) swop |= SWAR_CTRL_SIGNED;
+          switch ((unsigned)getLangOpts().UseSWARUnit) {
+            default: /* SwarKind::SWAR_Unit_ByType = by variable type */
+              if (swoptype==16)
+                swop |= SWAR_CTRL_AUDIO;
+              else if (swoptype==8)
+                swop |= SWAR_CTRL_VIDEO;
+              else
+                swop |= SWAR_CTRL_ALU;
+              break;
+            case llvm::SwarKinds::Audio:
+              swop |= SWAR_CTRL_AUDIO;
+              break;
+            case llvm::SwarKinds::Video:
+              swop |= SWAR_CTRL_VIDEO;
+              break;
+            case llvm::SwarKinds::ALU:
+              swop |= SWAR_CTRL_ALU;
+              break;
+          }
+          break;
+        }
+        boidx++;
+      }
+    }
+  }
+  return swop;
+}
+
 StmtResult Sema::ActOnForStmt(SourceLocation ForLoc, SourceLocation LParenLoc,
                               Stmt *First, ConditionResult Second,
                               FullExprArg third, SourceLocation RParenLoc,
@@ -2098,6 +2459,8 @@ StmtResult Sema::ActOnForStmt(SourceLocation ForLoc, SourceLocation LParenLoc,
   if (Second.isInvalid())
     return StmtError();
 
+  theLastSubwordOperation = 0;
+
   if (!getLangOpts().CPlusPlus) {
     if (DeclStmt *DS = dyn_cast_or_null<DeclStmt>(First)) {
       // C99 6.8.5p3: The declaration part of a 'for' statement shall only
@@ -2144,9 +2507,20 @@ StmtResult Sema::ActOnForStmt(SourceLocation ForLoc, SourceLocation LParenLoc,
   if (isa<NullStmt>(Body))
     getCurCompoundScope().setHasEmptyLoopBodies();
 
-  return new (Context)
+  if (!getLangOpts().EnabledSWARdaiteq)
+    return new (Context) ForStmt(Context, First, Second.get().second, Second.get().first, Third,
+                    Body, ForLoc, LParenLoc, RParenLoc);
+
+  int swarop = CheckSwarArrayOperation(Body);
+  inForLoopSubwordChecking = true;
+  Stmt *forres = new (Context)
       ForStmt(Context, First, Second.get().second, Second.get().first, Third,
               Body, ForLoc, LParenLoc, RParenLoc);
+  inForLoopSubwordChecking = false;
+  if (swarop>=0) {
+    forres = BuildSwarCtrlComp(forres, ForLoc, swarop);
+  }
+  return forres;
 }
 
 /// In an Objective C collection iteration statement:
diff --git a/clang/lib/Sema/SemaTemplate.cpp b/clang/lib/Sema/SemaTemplate.cpp
index 5d26f2d2c11a..952eec053e98 100644
--- a/clang/lib/Sema/SemaTemplate.cpp
+++ b/clang/lib/Sema/SemaTemplate.cpp
@@ -6038,6 +6038,10 @@ bool UnnamedLocalNoLinkageFinder::VisitConstantMatrixType(
   return Visit(T->getElementType());
 }
 
+bool UnnamedLocalNoLinkageFinder::VisitSubwordType(const SubwordType* T) {
+  return Visit(T->getBasicType());
+}
+
 bool UnnamedLocalNoLinkageFinder::VisitFunctionProtoType(
                                                   const FunctionProtoType* T) {
   for (const auto &A : T->param_types()) {
diff --git a/clang/lib/Sema/SemaTemplateDeduction.cpp b/clang/lib/Sema/SemaTemplateDeduction.cpp
index 08e798304b0c..02d60e15d758 100644
--- a/clang/lib/Sema/SemaTemplateDeduction.cpp
+++ b/clang/lib/Sema/SemaTemplateDeduction.cpp
@@ -1630,6 +1630,7 @@ DeduceTemplateArgumentsByTypeMatch(Sema &S,
     case Type::Builtin:
     case Type::VariableArray:
     case Type::Vector:
+    case Type::Subword:
     case Type::FunctionNoProto:
     case Type::Record:
     case Type::Enum:
@@ -5890,6 +5891,12 @@ MarkUsedTemplateParameters(ASTContext &Ctx, QualType T,
     break;
   }
 
+  case Type::Subword:
+    MarkUsedTemplateParameters(Ctx,
+                               cast<SubwordType>(T)->getBasicType(),
+                               OnlyDeduced, Depth, Used);
+    break;
+
   case Type::DependentAddressSpace: {
     const DependentAddressSpaceType *DependentASType =
         cast<DependentAddressSpaceType>(T);
diff --git a/clang/lib/Sema/SemaType.cpp b/clang/lib/Sema/SemaType.cpp
index bca21b351c91..09ed00aa13d3 100644
--- a/clang/lib/Sema/SemaType.cpp
+++ b/clang/lib/Sema/SemaType.cpp
@@ -2747,6 +2747,33 @@ QualType Sema::BuildMatrixType(QualType ElementTy, Expr *NumRows, Expr *NumCols,
   return Context.getConstantMatrixType(ElementTy, MatrixRows, MatrixColumns);
 }
 
+QualType Sema::BuildSubwordType(QualType BasicType, unsigned BitWidth,
+                                unsigned Packing, SourceLocation AttrLoc) {
+  // The base type must be integer (not Boolean or enumeration) or float, and
+  // can't already be a vector.
+  if (!BasicType->isDependentType() &&
+      (!BasicType->isBuiltinType() || BasicType->isBooleanType() ||
+       (!BasicType->isIntegerType() && !BasicType->isRealFloatingType()))) {
+    Diag(AttrLoc, diag::err_attribute_invalid_vector_type) << BasicType;
+    return QualType();
+  }
+
+  // Bitsize of the basic type
+  unsigned TypeSize = static_cast<unsigned>(Context.getTypeSize(BasicType));
+
+  // !!! PackSize = currently Number of elements in basic type word
+  unsigned maxpack = TypeSize/BitWidth;
+  // length of array of basic type words to cover all subword elements
+  //unsigned arrlen = (ne+(neiow-1))/neiow;
+  if (Packing>maxpack) {
+    Diag(AttrLoc, diag::err_attribute_subword_oversized) << Packing << BitWidth << TypeSize;
+    return QualType();
+  }
+  if (Packing==0) Packing = maxpack;
+
+  return Context.getSubwordType(BasicType, BitWidth, Packing);
+}
+
 bool Sema::CheckFunctionReturnType(QualType T, SourceLocation Loc) {
   if (T->isArrayType() || T->isFunctionType()) {
     Diag(Loc, diag::err_func_returning_array_function)
@@ -7954,6 +7981,77 @@ static void HandleArmMveStrictPolymorphismAttr(TypeProcessingState &State,
                               CurType, CurType);
 }
 
+static void HandleSubwordAttr(QualType &CurType, const ParsedAttr &Attr,
+                              Sema &S) {
+  if (!S.getLangOpts().EnabledSWARdaiteq) {
+    S.Diag(Attr.getLoc(), diag::err_attribute_subword_disabled);
+    return;
+  }
+// check the attribute arguments.
+  if (Attr.getNumArgs() < 1 || Attr.getNumArgs() > 2) {
+    S.Diag(Attr.getLoc(), diag::err_attribute_wrong_number_arguments)
+      << Attr.getAttrName()->getName() << 1;
+    return;
+  }
+
+// BitWidth - the first mandatory argument
+  Expr *BitSizeExpr;
+  // Special case where the argument is a template id.
+  if (Attr.isArgIdent(0)) {
+    CXXScopeSpec SS;
+    SourceLocation TemplateKWLoc;
+    UnqualifiedId Id;
+    Id.setIdentifier(Attr.getArgAsIdent(0)->Ident, Attr.getLoc());
+    ExprResult Size = S.ActOnIdExpression(S.getCurScope(), SS, TemplateKWLoc,
+                                          Id, false, false);
+    if (Size.isInvalid())
+      return;
+    BitSizeExpr = Size.get();
+  } else {
+    BitSizeExpr = Attr.getArgAsExpr(0);
+  }
+  Optional<llvm::APSInt> BitWidth = BitSizeExpr->getIntegerConstantExpr(S.Context);
+  if (!BitSizeExpr) {
+    S.Diag(Attr.getLoc(), diag::err_attribute_argument_type)
+        << "subword BS " << Attr.getAttrName()->getName() << BitSizeExpr->getSourceRange();
+    return;
+  }
+  unsigned BWidth = static_cast<unsigned>(BitWidth->getZExtValue());
+
+// Packing - the second optional argument
+  unsigned packing = 0; /* if the attribute has only one argument (bitwidth), packing is 0 by default for automatically filling the whole basic type */
+  if (Attr.getNumArgs()==2) {
+    Expr *PackingExpr;
+    // Special case where the argument is a template id.
+    if (Attr.isArgIdent(1)) {
+      CXXScopeSpec SS;
+      SourceLocation TemplateKWLoc;
+      UnqualifiedId Id;
+      Id.setIdentifier(Attr.getArgAsIdent(1)->Ident, Attr.getLoc());
+      ExprResult PckSz = S.ActOnIdExpression(S.getCurScope(), SS, TemplateKWLoc,
+                                              Id, false, false);
+      if (PckSz.isInvalid()) return;
+      PackingExpr = PckSz.get();
+    } else {
+      PackingExpr = Attr.getArgAsExpr(1);
+    }
+    Optional<llvm::APSInt> Packing = PackingExpr->getIntegerConstantExpr(S.Context);
+    if (!Packing) {
+      S.Diag(Attr.getLoc(), diag::err_attribute_argument_type)
+          << "subword Pack " << Attr.getAttrName()->getName() << PackingExpr->getSourceRange();
+      return;
+    }
+    packing = static_cast<unsigned>(Packing->getZExtValue());
+  }
+
+  QualType T = S.BuildSubwordType(CurType, BWidth, packing, Attr.getLoc());
+  if (!T.isNull())
+    CurType = T;
+  else
+    Attr.setInvalid();
+//  S.Diag(Attr.getLoc(), diag::err_attribute_unsupported) << Attr.getName();
+}
+
 /// Handle OpenCL Access Qualifier Attribute.
 static void HandleOpenCLAccessAttr(QualType &CurType, const ParsedAttr &Attr,
                                    Sema &S) {
@@ -8170,6 +8268,12 @@ static void processTypeAttrs(TypeProcessingState &state, QualType &type,
       attr.setUsedAsTypeAttr();
       break;
     }
+
+    case ParsedAttr::AT_Subword:
+      HandleSubwordAttr(type, attr, state.getSema());
+      attr.setUsedAsTypeAttr();
+      break;
+
     case ParsedAttr::AT_OpenCLAccess:
       HandleOpenCLAccessAttr(type, attr, state.getSema());
       attr.setUsedAsTypeAttr();
diff --git a/clang/lib/Sema/TreeTransform.h b/clang/lib/Sema/TreeTransform.h
index 70ba631dbfc6..96af8019d603 100644
--- a/clang/lib/Sema/TreeTransform.h
+++ b/clang/lib/Sema/TreeTransform.h
@@ -906,6 +906,14 @@ public:
                                            Expr *ColumnExpr,
                                            SourceLocation AttributeLoc);
 
+  /// Build a new subword type given the element type, element bitwidth and
+  /// packed number of elements.
+  ///
+  /// By default, performs semantic analysis when building the vector type.
+  /// Subclasses may override this routine to provide different behavior.
+  QualType RebuildSubwordType(QualType ElementType, unsigned BitWidth,
+                              unsigned Packing, SourceLocation AttributeLoc);
+
   /// Build a new DependentAddressSpaceType or return the pointee
   /// type variable with the correct address space (retrieved from
   /// AddrSpaceExpr) applied to it. The former will be returned in cases
@@ -5536,6 +5544,31 @@ QualType TreeTransform<Derived>::TransformExtVectorType(TypeLocBuilder &TLB,
   return Result;
 }
 
+template<typename Derived>
+QualType TreeTransform<Derived>::TransformSubwordType(TypeLocBuilder &TLB,
+                                                      SubwordTypeLoc TL) {
+  const SubwordType *T = TL.getTypePtr();
+  QualType BasicType = getDerived().TransformType(T->getBasicType());
+  if (BasicType.isNull())
+    return QualType();
+
+  QualType Result = TL.getType();
+  if (getDerived().AlwaysRebuild() ||
+      BasicType != T->getBasicType()) {
+    Result = getDerived().RebuildSubwordType(BasicType,
+                                              T->getBitWidth(),
+                                              T->getPacking(),
+                                               /*FIXME*/ SourceLocation());
+    if (Result.isNull())
+      return QualType();
+  }
+
+  SubwordTypeLoc NewTL = TLB.push<SubwordTypeLoc>(Result);
+  NewTL.setNameLoc(TL.getNameLoc());
+
+  return Result;
+}
+
 template <typename Derived>
 ParmVarDecl *TreeTransform<Derived>::TransformFunctionTypeParam(
     ParmVarDecl *OldParm, int indexAdjustment, Optional<unsigned> NumExpansions,
@@ -14365,6 +14398,12 @@ QualType TreeTransform<Derived>::RebuildDependentSizedMatrixType(
                                  AttributeLoc);
 }
 
+template<typename Derived>
+QualType TreeTransform<Derived>::RebuildSubwordType(QualType BasicType,
+        unsigned BitWidth, unsigned Packing, SourceLocation AttributeLoc) {
+  return SemaRef.BuildSubwordType(BasicType, BitWidth, Packing, AttributeLoc);
+}
+
 template<typename Derived>
 QualType TreeTransform<Derived>::RebuildFunctionProtoType(
     QualType T,
diff --git a/clang/lib/Serialization/ASTReader.cpp b/clang/lib/Serialization/ASTReader.cpp
index 83bade9941b3..1775a4f5049f 100644
--- a/clang/lib/Serialization/ASTReader.cpp
+++ b/clang/lib/Serialization/ASTReader.cpp
@@ -6616,6 +6616,10 @@ void TypeLocReader::VisitDependentSizedMatrixTypeLoc(
   TL.setAttrColumnOperand(Reader.readExpr());
 }
 
+void TypeLocReader::VisitSubwordTypeLoc(SubwordTypeLoc TL) {
+  TL.setNameLoc(readSourceLocation());
+}
+
 void TypeLocReader::VisitFunctionTypeLoc(FunctionTypeLoc TL) {
   TL.setLocalRangeBegin(readSourceLocation());
   TL.setLParenLoc(readSourceLocation());
diff --git a/clang/lib/Serialization/ASTWriter.cpp b/clang/lib/Serialization/ASTWriter.cpp
index 66c207ad9243..ab6f6d3c2f88 100644
--- a/clang/lib/Serialization/ASTWriter.cpp
+++ b/clang/lib/Serialization/ASTWriter.cpp
@@ -309,6 +309,10 @@ void TypeLocWriter::VisitDependentSizedMatrixTypeLoc(
   Record.AddStmt(TL.getAttrColumnOperand());
 }
 
+void TypeLocWriter::VisitSubwordTypeLoc(SubwordTypeLoc TL) {
+  Record.AddSourceLocation(TL.getNameLoc());
+}
+
 void TypeLocWriter::VisitFunctionTypeLoc(FunctionTypeLoc TL) {
   Record.AddSourceLocation(TL.getLocalRangeBegin());
   Record.AddSourceLocation(TL.getLParenLoc());
@@ -845,6 +849,9 @@ void ASTWriter::WriteBlockInfoBlock() {
   RECORD(TYPE_VARIABLE_ARRAY);
   RECORD(TYPE_VECTOR);
   RECORD(TYPE_EXT_VECTOR);
+
+  RECORD(TYPE_SUBWORD);
+
   RECORD(TYPE_FUNCTION_NO_PROTO);
   RECORD(TYPE_FUNCTION_PROTO);
   RECORD(TYPE_TYPEDEF);
diff --git a/clang/tools/libclang/CIndex.cpp b/clang/tools/libclang/CIndex.cpp
index 7b93164ccaa2..a353df12bf78 100644
--- a/clang/tools/libclang/CIndex.cpp
+++ b/clang/tools/libclang/CIndex.cpp
@@ -1817,6 +1817,7 @@ DEFAULT_TYPELOC_IMPL(SubstTemplateTypeParmPack, Type)
 DEFAULT_TYPELOC_IMPL(Auto, Type)
 DEFAULT_TYPELOC_IMPL(ExtInt, Type)
 DEFAULT_TYPELOC_IMPL(DependentExtInt, Type)
+DEFAULT_TYPELOC_IMPL(Subword, Type)
 
 bool CursorVisitor::VisitCXXRecordDecl(CXXRecordDecl *D) {
   // Visit the nested-name-specifier, if present.
diff --git a/llvm/include/llvm-c/Core.h b/llvm/include/llvm-c/Core.h
index 1a5e763cfc60..7647a9aa67b4 100644
--- a/llvm/include/llvm-c/Core.h
+++ b/llvm/include/llvm-c/Core.h
@@ -163,7 +163,8 @@ typedef enum {
   LLVMTokenTypeKind,     /**< Tokens */
   LLVMScalableVectorTypeKind, /**< Scalable SIMD vector type */
   LLVMBFloatTypeKind,    /**< 16 bit brain floating point type */
-  LLVMX86_AMXTypeKind    /**< X86 AMX */
+  LLVMX86_AMXTypeKind,   /**< X86 AMX */
+  LLVMSubwordVectorTypeKind /**< Subword SIMD vector type */
 } LLVMTypeKind;
 
 typedef enum {
@@ -1472,6 +1473,22 @@ LLVMTypeRef LLVMVectorType(LLVMTypeRef ElementType, unsigned ElementCount);
 LLVMTypeRef LLVMScalableVectorType(LLVMTypeRef ElementType,
                                    unsigned ElementCount);
 
+/**
+ * Create a vector type that contains elements with defined type packed into
+ * another type - the vector contains specific number of elements in each pack
+ * and specific elements in the vector.
+ *
+ * The created type will exist in the context thats its element type
+ * exists in.
+ *
+ * @see llvm::SubwordVectorType::get()
+ */
+LLVMTypeRef LLVMSubwordVectorType(LLVMTypeRef ElementType,
+                                  unsigned ElementCount,
+                                  LLVMTypeRef BasicType,
+                                  unsigned PackingFactor,
+                                  unsigned Signed);
+
 /**
  * Obtain the (possibly scalable) number of elements in a vector type.
  *
diff --git a/llvm/include/llvm/ADT/Triple.h b/llvm/include/llvm/ADT/Triple.h
index 76f3514050f0..4fb4ec37c06e 100644
--- a/llvm/include/llvm/ADT/Triple.h
+++ b/llvm/include/llvm/ADT/Triple.h
@@ -159,7 +159,8 @@ public:
     Mesa,
     SUSE,
     OpenEmbedded,
-    LastVendorType = OpenEmbedded
+    Daiteq,
+    LastVendorType = Daiteq
   };
   enum OSType {
     UnknownOS,
diff --git a/llvm/include/llvm/AsmParser/LLToken.h b/llvm/include/llvm/AsmParser/LLToken.h
index aa49c68fe924..5449807b9362 100644
--- a/llvm/include/llvm/AsmParser/LLToken.h
+++ b/llvm/include/llvm/AsmParser/LLToken.h
@@ -37,6 +37,8 @@ enum Kind {
   bar,     // |
   colon,   // :
 
+  kw_subword,
+  kw_in,
   kw_vscale,
   kw_x,
   kw_true,
diff --git a/llvm/include/llvm/CodeGen/RuntimeLibcalls.h b/llvm/include/llvm/CodeGen/RuntimeLibcalls.h
index d8c631060b7e..95a1480d0eb8 100644
--- a/llvm/include/llvm/CodeGen/RuntimeLibcalls.h
+++ b/llvm/include/llvm/CodeGen/RuntimeLibcalls.h
@@ -36,6 +36,7 @@ namespace RTLIB {
   /// GetFPLibCall - Helper to return the right libcall for the given floating
   /// point type, or UNKNOWN_LIBCALL if there is none.
   Libcall getFPLibCall(EVT VT,
+                       Libcall Call_F16,
                        Libcall Call_F32,
                        Libcall Call_F64,
                        Libcall Call_F80,
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
index deeca98af3f3..73d18a2fbc10 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -194,7 +194,10 @@ public:
   }
 
   uint64_t getScalarValueSizeInBits() const {
-    return getValueType().getScalarType().getFixedSizeInBits();
+   if (getValueType().isSubwordVector())
+     return getValueType().getSizeInBits();
+   else
+     return getValueType().getScalarType().getFixedSizeInBits();
   }
 
   // Forwarding methods - These forward to the corresponding methods in SDNode.
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index a4955e2a973a..767bf07d8dd7 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -1413,6 +1413,11 @@ public:
 
     if (auto *VTy = dyn_cast<VectorType>(Ty)) {
       Type *EltTy = VTy->getElementType();
+
+      if (isa<SubwordVectorType>(Ty)) {
+        return EVT::getEVT(Ty, false);
+      }
+
       // Lower vectors of pointers to native pointer types.
       if (auto *PTy = dyn_cast<PointerType>(EltTy)) {
         EVT PointerTy(getPointerTy(DL, PTy->getAddressSpace()));
@@ -1431,6 +1436,9 @@ public:
     if (PointerType *PTy = dyn_cast<PointerType>(Ty))
       return getPointerMemTy(DL, PTy->getAddressSpace());
     else if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
+      if (isa<SubwordVectorType>(Ty)) {
+        return EVT::getEVT(cast<SubwordVectorType>(Ty)->getBasicType(), false);
+      }
       Type *Elm = VTy->getElementType();
       if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
         EVT PointerTy(getPointerMemTy(DL, PT->getAddressSpace()));
diff --git a/llvm/include/llvm/CodeGen/ValueTypes.h b/llvm/include/llvm/CodeGen/ValueTypes.h
index 7b17b98d5c55..4f148cfb5fbf 100644
--- a/llvm/include/llvm/CodeGen/ValueTypes.h
+++ b/llvm/include/llvm/CodeGen/ValueTypes.h
@@ -88,6 +88,44 @@ namespace llvm {
       return getExtendedVectorVT(Context, VT, EC);
     }
 
+/* returns EVT Type which represents LLVM::Type (Subword vector). The output type is a vector type of vswp32 or vswp64 */
+/* BasicType is MVT::i32 or MVT::i64, ElmBW is one from 1/2/3/4/8/16(/32),
+ * Packing is a number of elements packed in each basic types */
+    static EVT getSubwordVT(LLVMContext &Context, MVT BasicType,
+                            unsigned ElmBW, unsigned Packing) {
+      assert ((BasicType.SimpleTy==MVT::i32 || BasicType.SimpleTy==MVT::i64) && "getSubwordVT for unsupported basic type");
+      EVT extVT;
+      if (BasicType.SimpleTy==MVT::i64) {
+        assert ((ElmBW<64) && "getSubwordVT for too wide elements");
+        if (ElmBW==1) extVT = EVT(MVT::vswp64i1);
+        else if (ElmBW==2) extVT = EVT(MVT::vswp64i2);
+        else if (ElmBW==3) extVT = EVT(MVT::vswp64i3);
+        else if (ElmBW==4) extVT = EVT(MVT::vswp64i4);
+        else if (ElmBW==8) extVT = EVT(MVT::vswp64i8);
+        else if (ElmBW==16) extVT = EVT(MVT::vswp64i16);
+        else if (ElmBW==32) extVT = EVT(MVT::vswp64i32);
+        else {
+          assert(false && "unsupported subword type packed in i64");
+        }
+//        extVT = EVT(MVT::vswp64);
+      } else {
+        assert ((ElmBW<32) && "getSubwordVT for too wide elements");
+        if (ElmBW==1) extVT = EVT(MVT::vswp32i1);
+        else if (ElmBW==2) extVT = EVT(MVT::vswp32i2);
+        else if (ElmBW==3) extVT = EVT(MVT::vswp32i3);
+        else if (ElmBW==4) extVT = EVT(MVT::vswp32i4);
+        else if (ElmBW==8) extVT = EVT(MVT::vswp32i8);
+        else if (ElmBW==16) extVT = EVT(MVT::vswp32i16);
+        else {
+          assert(false && "unsupported subword type packed in i32");
+        }
+//        extVT = EVT(MVT::vswp32);
+      }
+//      extVT.ElmBitWidth = ElmBW;
+//      extVT.Packing = Packing;
+      return extVT;
+    }
+
     /// Return a vector with the same number of elements as this vector, but
     /// with the element type converted to an integer type with the same
     /// bitwidth.
@@ -156,6 +194,10 @@ namespace llvm {
       return isSimple() ? V.isVector() : isExtendedVector();
     }
 
+    bool isSubwordVector() const {
+      return isSimple() ? V.isSubwordVector() : isExtendedSubword();
+    }
+
     /// Return true if this is a vector type where the runtime
     /// length is machine dependent
     bool isScalableVector() const {
@@ -294,6 +336,7 @@ namespace llvm {
     /// If this is a vector type, return the element type, otherwise return
     /// this.
     EVT getScalarType() const {
+      if (isSubwordVector()) return EVT(MVT::i32); //getBasicType(); /* basic type is only i32 now */
       return isVector() ? getVectorElementType() : *this;
     }
 
@@ -307,7 +350,7 @@ namespace llvm {
 
     /// Given a vector type, return the number of elements it contains.
     unsigned getVectorNumElements() const {
-      assert(isVector() && "Invalid vector type!");
+      assert((isVector() || isSubwordVector()) && "Invalid vector type!");
 
       if (isScalableVector())
         llvm::reportInvalidSizeRequest(
@@ -495,6 +538,7 @@ namespace llvm {
     bool isExtendedInteger() const LLVM_READONLY;
     bool isExtendedScalarInteger() const LLVM_READONLY;
     bool isExtendedVector() const LLVM_READONLY;
+    bool isExtendedSubword() const LLVM_READONLY;
     bool isExtended16BitVector() const LLVM_READONLY;
     bool isExtended32BitVector() const LLVM_READONLY;
     bool isExtended64BitVector() const LLVM_READONLY;
diff --git a/llvm/include/llvm/CodeGen/ValueTypes.td b/llvm/include/llvm/CodeGen/ValueTypes.td
index 8bacf687ac76..5bd09748cd1c 100644
--- a/llvm/include/llvm/CodeGen/ValueTypes.td
+++ b/llvm/include/llvm/CodeGen/ValueTypes.td
@@ -209,14 +209,28 @@ def nxv2f64  : ValueType<128, 168>;  // n x  2 x  f64 vector value
 def nxv4f64  : ValueType<256, 169>;  // n x  4 x  f64 vector value
 def nxv8f64  : ValueType<512, 170>;  // n x  8 x  f64 vector value
 
-def x86mmx    : ValueType<64,   171>;  // X86 MMX value
-def FlagVT    : ValueType<0,    172>;  // Pre-RA sched glue
-def isVoid    : ValueType<0,    173>;  // Produces no value
-def untyped   : ValueType<8,    174>;  // Produces an untyped value
-def funcref   : ValueType<0,    175>;  // WebAssembly's funcref type
-def externref : ValueType<0,    176>;  // WebAssembly's externref type
-def x86amx    : ValueType<8192, 177>;  // X86 AMX value
-def i64x8     : ValueType<512,  178>;  // 8 Consecutive GPRs (AArch64)
+def vswp32i1   : ValueType<32 , 171>; // i1 packed in i32 subword vector value
+def vswp32i2   : ValueType<32 , 172>; // i2 packed in i32 subword vector value
+def vswp32i3   : ValueType<32 , 173>; // i3 packed in i32 subword vector value
+def vswp32i4   : ValueType<32 , 174>; // i4 packed in i32 subword vector value
+def vswp32i8   : ValueType<32 , 175>; // i8 packed in i32 subword vector value
+def vswp32i16  : ValueType<32 , 176>; // i16 packed in i32 subword vector value
+def vswp64i1   : ValueType<64 , 177>; // i1 packed in i64 subword vector value
+def vswp64i2   : ValueType<64 , 178>; // i2 packed in i64 subword vector value
+def vswp64i3   : ValueType<64 , 179>; // i3 packed in i64 subword vector value
+def vswp64i4   : ValueType<64 , 180>; // i4 packed in i64 subword vector value
+def vswp64i8   : ValueType<64 , 181>; // i8 packed in i64 subword vector value
+def vswp64i16   : ValueType<64 , 182>; // i16 packed in i64 subword vector value
+def vswp64i32   : ValueType<64 , 183>; // i32 packed in i64 subword vector value
+
+def x86mmx    : ValueType<64,   184>;  // X86 MMX value
+def FlagVT    : ValueType<0,    185>;  // Pre-RA sched glue
+def isVoid    : ValueType<0,    186>;  // Produces no value
+def untyped   : ValueType<8,    187>;  // Produces an untyped value
+def funcref   : ValueType<0,    188>;  // WebAssembly's funcref type
+def externref : ValueType<0,    189>;  // WebAssembly's externref type
+def x86amx    : ValueType<8192, 190>;  // X86 AMX value
+def i64x8     : ValueType<512,  191>;  // 8 Consecutive GPRs (AArch64)
 
 
 def token      : ValueType<0, 248>;  // TokenTy
diff --git a/llvm/include/llvm/IR/DIBuilder.h b/llvm/include/llvm/IR/DIBuilder.h
index 23ac47ca4d81..48f6e5a67a97 100644
--- a/llvm/include/llvm/IR/DIBuilder.h
+++ b/llvm/include/llvm/IR/DIBuilder.h
@@ -523,6 +523,14 @@ namespace llvm {
     DICompositeType *createVectorType(uint64_t Size, uint32_t AlignInBits,
                                       DIType *Ty, DINodeArray Subscripts);
 
+    /// Create debugging information entry for a subword type.
+    /// \param ESize        Element size.
+    /// \param ECount       Number of elements.
+    /// \param Ty           Basic type.
+    /// \param Subscripts   Subscripts.
+    DICompositeType *createSubwordType(uint64_t ESize, uint64_t ECount,
+                                      DIType *Ty, DINodeArray Subscripts);
+
     /// Create debugging information entry for an
     /// enumeration.
     /// \param Scope          Scope in which this enumeration is defined.
diff --git a/llvm/include/llvm/IR/DataLayout.h b/llvm/include/llvm/IR/DataLayout.h
index 300f73c12df0..9eef8b3c7803 100644
--- a/llvm/include/llvm/IR/DataLayout.h
+++ b/llvm/include/llvm/IR/DataLayout.h
@@ -695,6 +695,11 @@ inline TypeSize DataLayout::getTypeSizeInBits(Type *Ty) const {
                        getTypeSizeInBits(VTy->getElementType()).getFixedSize();
     return TypeSize(MinBits, EltCnt.isScalable());
   }
+  case Type::SubwordVectorTyID: { /* TODO: probably it should be a size of all words of basic type */
+    SubwordVectorType *VTy = cast<SubwordVectorType>(Ty);
+    uint64_t bits = VTy->getNumPacks() * getTypeSizeInBits(VTy->getBasicType()).getFixedSize();
+    return TypeSize(bits, false);
+  }
   default:
     llvm_unreachable("DataLayout::getTypeSizeInBits(): Unsupported type");
   }
diff --git a/llvm/include/llvm/IR/DebugInfoFlags.def b/llvm/include/llvm/IR/DebugInfoFlags.def
index df375b6c68e8..15a80d142bd1 100644
--- a/llvm/include/llvm/IR/DebugInfoFlags.def
+++ b/llvm/include/llvm/IR/DebugInfoFlags.def
@@ -58,6 +58,7 @@ HANDLE_DI_FLAG((1 << 26), NonTrivial)
 HANDLE_DI_FLAG((1 << 27), BigEndian)
 HANDLE_DI_FLAG((1 << 28), LittleEndian)
 HANDLE_DI_FLAG((1 << 29), AllCallsDescribed)
+HANDLE_DI_FLAG((1 << 30), Subword)
 
 // To avoid needing a dedicated value for IndirectVirtualBase, we use
 // the bitwise or of Virtual and FwdDecl, which does not otherwise
@@ -67,7 +68,7 @@ HANDLE_DI_FLAG((1 << 2) | (1 << 5), IndirectVirtualBase)
 #ifdef DI_FLAG_LARGEST_NEEDED
 // intended to be used with ADT/BitmaskEnum.h
 // NOTE: always must be equal to largest flag, check this when adding new flag
-HANDLE_DI_FLAG((1 << 29), Largest)
+HANDLE_DI_FLAG((1 << 30), Largest)
 #undef DI_FLAG_LARGEST_NEEDED
 #endif
 
diff --git a/llvm/include/llvm/IR/DebugInfoMetadata.h b/llvm/include/llvm/IR/DebugInfoMetadata.h
index 20a032f04909..ca31fd8215ca 100644
--- a/llvm/include/llvm/IR/DebugInfoMetadata.h
+++ b/llvm/include/llvm/IR/DebugInfoMetadata.h
@@ -736,6 +736,7 @@ public:
     return getFlags() & FlagObjcClassComplete;
   }
   bool isVector() const { return getFlags() & FlagVector; }
+  bool isSubword() const { return getFlags() & FlagSubword; }
   bool isBitField() const { return getFlags() & FlagBitField; }
   bool isStaticMember() const { return getFlags() & FlagStaticMember; }
   bool isLValueReference() const { return getFlags() & FlagLValueReference; }
diff --git a/llvm/include/llvm/IR/DerivedTypes.h b/llvm/include/llvm/IR/DerivedTypes.h
index b68a912b5f70..afd322869f30 100644
--- a/llvm/include/llvm/IR/DerivedTypes.h
+++ b/llvm/include/llvm/IR/DerivedTypes.h
@@ -398,6 +398,9 @@ class VectorType : public Type {
   /// <4 x i32>          - a vector containing 4 i32s
   /// <vscale x 4 x i32> - a vector containing an unknown integer multiple
   ///                      of 4 i32s
+  ///
+  /// <subword 'PckSz' x 'eltTy' in 'BasTp' > - a vector of subword elements
+  ///
 
   /// The element type of the vector.
   Type *ContainedType;
@@ -410,6 +413,7 @@ protected:
   /// - For ScalableVectorType = <vscale x ElementQuantity x ty>,
   ///   there are vscale * ElementQuantity elements in this vector, where
   ///   vscale is a runtime-constant integer greater than 0.
+  /// - For SubwordVectorType = <ElementQuantity x BasTy>,
   const unsigned ElementQuantity;
 
   VectorType(Type *ElType, unsigned EQ, Type::TypeID TID);
@@ -433,6 +437,9 @@ public:
     return VectorType::get(ElementType, Other->getElementCount());
   }
 
+  // For Subword type - ElementQuantity contains number of packed elements
+  static VectorType *get(Type *ElementType, unsigned NumElms, Type *BasicType, unsigned PckSz, bool Sign);
+
   /// This static method gets a VectorType with the same number of elements as
   /// the input type, and the element type is an integer type of the same width
   /// as the input element type.
@@ -516,7 +523,8 @@ public:
   /// Methods for support type inquiry through isa, cast, and dyn_cast.
   static bool classof(const Type *T) {
     return T->getTypeID() == FixedVectorTyID ||
-           T->getTypeID() == ScalableVectorTyID;
+           T->getTypeID() == ScalableVectorTyID ||
+           T->getTypeID() == SubwordVectorTyID;
   }
 };
 
@@ -623,6 +631,106 @@ public:
   }
 };
 
+/// Class to represent subword SIMD vectors
+/// Each subword vector consists of a set of elements of integer type <ElTy> which
+/// are packed in <NumPcks> basic type
+class SubwordVectorType : public VectorType {
+protected:
+  SubwordVectorType(Type *ElTy, unsigned NumEl, Type *BasTy, unsigned Pckg,
+                    bool Signed) : VectorType(ElTy, NumEl, SubwordVectorTyID),
+                    SubwordSubTys{ElTy,BasTy} {
+    BasicType = BasTy;
+    Packing = Pckg;
+    signedEls = Signed;
+
+    ContainedTys = SubwordSubTys;
+    NumContainedTys = 2;
+  }
+
+  // The subword type is described by a type of elements <ElTy>,
+  // a basic type <BasTy>, a number of all elements <NumEl> and packing factor
+  // (number of elements in each basic type <Pckg> ... the last word can contain
+  // less elements) If <Pckg> is 0, the maximum elements in basic type is used
+  // i.e. pcksz = size(basicType)/size(elementType).
+  // <NumEl> is saved in VectorType::ElementQuantity.
+  // <ElTy> is placed in VectorType::ContainedType.
+  // <BasTy> is placed in SubwordVectorType::BasicType.
+  // <Pckg> is placed in SubwordVectorType::Packing.
+  Type *BasicType;
+  unsigned Packing;
+  bool signedEls;
+
+  Type *SubwordSubTys[2]; /* 0: elementType, 1: basicType */
+
+//VectorType::VectorType(Type *BasType, Type *ElType, unsigned Packing, bool IsSigned)
+  //: SequentialType(VectorTyID, ElType, Packing), Subword(true), BasicType(BasType),
+                   //SubwordSubTys{ElType,BasType}, signedBasicType(IsSigned) {
+  ///* exchange underlying component types */
+  ////ContainedType = getElementType();
+  ////BasicType = BasType;
+  //ContainedTys = SubwordSubTys;
+  //NumContainedTys = 2;
+//}
+
+  // This special constructor is only for subword type
+//  VectorType(Type *BasType, Type *ElType, unsigned Packing, bool IsSigned);
+
+public:
+  Type *getBasicType() const { return BasicType; }
+  unsigned getPacking() const { return Packing; }
+  bool getSigned() const { return signedEls; }
+  unsigned getNumElements() const { return ElementQuantity; }
+  unsigned getNumPacks() const { return (ElementQuantity/Packing + ((ElementQuantity%Packing) ? 1 : 0));}
+
+  static SubwordVectorType *get(Type *ElementType, unsigned NumElms, Type *BasicType, unsigned PckSz, bool Sign);
+
+  static SubwordVectorType *getInteger(SubwordVectorType *VTy) {
+    return cast<SubwordVectorType>(VectorType::getInteger(VTy));
+  }
+
+  static SubwordVectorType *
+  getExtendedElementVectorType(SubwordVectorType *VTy) {
+    return cast<SubwordVectorType>(
+        VectorType::getExtendedElementVectorType(VTy));
+  }
+
+  static SubwordVectorType *
+  getTruncatedElementVectorType(SubwordVectorType *VTy) {
+    return cast<SubwordVectorType>(
+        VectorType::getTruncatedElementVectorType(VTy));
+  }
+
+  static SubwordVectorType *getSubdividedVectorType(SubwordVectorType *VTy,
+                                                     int NumSubdivs) {
+    return cast<SubwordVectorType>(
+        VectorType::getSubdividedVectorType(VTy, NumSubdivs));
+  }
+
+  static SubwordVectorType *
+  getHalfElementsVectorType(SubwordVectorType *VTy) {
+    return cast<SubwordVectorType>(VectorType::getHalfElementsVectorType(VTy));
+  }
+
+  static SubwordVectorType *
+  getDoubleElementsVectorType(SubwordVectorType *VTy) {
+    return cast<SubwordVectorType>(
+        VectorType::getDoubleElementsVectorType(VTy));
+  }
+
+  /// Get the minimum number of elements in this vector. The actual number of
+  /// elements in the vector is an integer multiple <NumPacks> of this value.
+  uint64_t getMinNumElements() const { return ElementQuantity; }
+
+  static bool classof(const Type *T) {
+    return T->getTypeID() == SubwordVectorTyID;
+  }
+};
+
+bool Type::getVectorIsSubword() const {
+  return (isa<SubwordVectorType>(this));
+}
+
+
 inline ElementCount VectorType::getElementCount() const {
   return ElementCount::get(ElementQuantity, isa<ScalableVectorType>(this));
 }
diff --git a/llvm/include/llvm/IR/GetElementPtrTypeIterator.h b/llvm/include/llvm/IR/GetElementPtrTypeIterator.h
index ed854e458da2..de619ac784d5 100644
--- a/llvm/include/llvm/IR/GetElementPtrTypeIterator.h
+++ b/llvm/include/llvm/IR/GetElementPtrTypeIterator.h
@@ -86,6 +86,8 @@ public:
       CurTy = VTy->getElementType();
       if (isa<ScalableVectorType>(VTy))
         NumElements = Unbounded;
+      else if (isa<SubwordVectorType>(VTy))
+        NumElements = cast<SubwordVectorType>(VTy)->getNumElements();
       else
         NumElements = cast<FixedVectorType>(VTy)->getNumElements();
     } else
diff --git a/llvm/include/llvm/IR/InstrTypes.h b/llvm/include/llvm/IR/InstrTypes.h
index ef2c279ed455..33d304cf4708 100644
--- a/llvm/include/llvm/IR/InstrTypes.h
+++ b/llvm/include/llvm/IR/InstrTypes.h
@@ -189,6 +189,8 @@ public:
 class BinaryOperator : public Instruction {
   void AssertOK();
 
+  bool SubwordOp;
+
 protected:
   BinaryOperator(BinaryOps iType, Value *S1, Value *S2, Type *Ty,
                  const Twine &Name, Instruction *InsertBefore);
@@ -205,6 +207,8 @@ public:
   void *operator new(size_t S) { return User::operator new(S, 2); }
   void operator delete(void *Ptr) { User::operator delete(Ptr); }
 
+  bool isSubwordOp(void) const { return SubwordOp; }
+
   /// Transparently provide more efficient getOperand methods.
   DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
 
@@ -1029,6 +1033,9 @@ public:
 
   /// Create a result type for fcmp/icmp
   static Type* makeCmpResultType(Type* opnd_type) {
+    if (SubwordVectorType *swvt = dyn_cast<SubwordVectorType>(opnd_type)) { /* comparing of subword types returns integer type identical to the basic type */
+      return swvt->getBasicType();
+    }
     if (VectorType* vt = dyn_cast<VectorType>(opnd_type)) {
       return VectorType::get(Type::getInt1Ty(opnd_type->getContext()),
                              vt->getElementCount());
diff --git a/llvm/include/llvm/IR/Instructions.h b/llvm/include/llvm/IR/Instructions.h
index 0c43a56daa33..6b417a099fdd 100644
--- a/llvm/include/llvm/IR/Instructions.h
+++ b/llvm/include/llvm/IR/Instructions.h
@@ -1204,12 +1204,16 @@ class ICmpInst: public CmpInst {
   void AssertOK() {
     assert(isIntPredicate() &&
            "Invalid ICmp predicate value");
-    assert(getOperand(0)->getType() == getOperand(1)->getType() &&
-          "Both operands to ICmp instruction are not of the same type!");
+//    assert(getOperand(0)->getType() == getOperand(1)->getType() &&
+//          "Both operands to ICmp instruction are not of the same type!");
     // Check that the operands are the right type
     assert((getOperand(0)->getType()->isIntOrIntVectorTy() ||
             getOperand(0)->getType()->isPtrOrPtrVectorTy()) &&
            "Invalid operand types for ICmp instruction");
+
+    assert((getOperand(1)->getType()->isIntOrIntVectorTy() ||
+            getOperand(1)->getType()->isPtrOrPtrVectorTy()) &&
+           "Invalid second operand types for ICmp instruction");
   }
 
 protected:
diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td
index 28fcc13266b1..390b0fbe45a9 100644
--- a/llvm/include/llvm/IR/Intrinsics.td
+++ b/llvm/include/llvm/IR/Intrinsics.td
@@ -329,6 +329,23 @@ def llvm_v16f64_ty     : LLVMType<v16f64>;   // 16 x double
 
 def llvm_vararg_ty     : LLVMType<isVoid>;   // this means vararg here
 
+//def llvm_vswp32_ty     : LLVMType<vswp32>;
+//def llvm_vswp64_ty     : LLVMType<vswp64>;
+def llvm_vswp32i1_ty   : LLVMType<vswp32i1>;   // subword 32xi1 in i32
+def llvm_vswp32i2_ty   : LLVMType<vswp32i2>;   // subword 16xi2 in i32
+def llvm_vswp32i3_ty   : LLVMType<vswp32i3>;   // subword 10xi3 in i32
+def llvm_vswp32i4_ty   : LLVMType<vswp32i4>;   // subword 8xi4 in i32
+def llvm_vswp32i8_ty   : LLVMType<vswp32i8>;   // subword 4xi8 in i32
+def llvm_vswp32i16_ty  : LLVMType<vswp32i16>;   // subword 2xi16 in i32
+def llvm_vswp64i1_ty   : LLVMType<vswp64i1>;   // subword 64xi1 in i64
+def llvm_vswp64i2_ty   : LLVMType<vswp64i2>;   // subword 32xi2 in i64
+def llvm_vswp64i3_ty   : LLVMType<vswp64i3>;   // subword 21xi3 in i64
+def llvm_vswp64i4_ty   : LLVMType<vswp64i4>;   // subword 16xi4 in i64
+def llvm_vswp64i8_ty   : LLVMType<vswp64i8>;   // subword 8xi8 in i64
+def llvm_vswp64i16_ty  : LLVMType<vswp64i16>;   // subword 4xi16 in i64
+def llvm_vswp64i32_ty  : LLVMType<vswp64i32>;   // subword 2xi32 in i64
+
+
 //===----------------------------------------------------------------------===//
 // Intrinsic Definitions.
 //===----------------------------------------------------------------------===//
diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.def b/llvm/include/llvm/IR/RuntimeLibcalls.def
index c73172612b1e..eb0782b0b287 100644
--- a/llvm/include/llvm/IR/RuntimeLibcalls.def
+++ b/llvm/include/llvm/IR/RuntimeLibcalls.def
@@ -87,111 +87,152 @@ HANDLE_LIBCALL(CTLZ_I64, "__clzdi2")
 HANDLE_LIBCALL(CTLZ_I128, "__clzti2")
 
 // Floating-point
+HANDLE_LIBCALL(NEG_F16, "__neghf2")
+HANDLE_LIBCALL(NEG_F32, "__negsf2")
+HANDLE_LIBCALL(NEG_F64, "__negdf2")
+HANDLE_LIBCALL(ABS_F16, "fabsh")
+HANDLE_LIBCALL(ABS_F32, "fabsf")
+HANDLE_LIBCALL(ABS_F64, "fabs")
+
+
+HANDLE_LIBCALL(ADD_V2F16, "__addphf3")
+HANDLE_LIBCALL(ADD_V2F32, "__addpsf3")
+HANDLE_LIBCALL(SUB_V2F16, "__subphf3")
+HANDLE_LIBCALL(SUB_V2F32, "__subpsf3")
+HANDLE_LIBCALL(MUL_V2F16, "__mulphf3")
+HANDLE_LIBCALL(MUL_V2F32, "__mulpsf3")
+HANDLE_LIBCALL(DIV_V2F16, "__divphf3")
+HANDLE_LIBCALL(DIV_V2F32, "__divpsf3")
+HANDLE_LIBCALL(SQRT_V2F16, "sqrtph")
+HANDLE_LIBCALL(SQRT_V2F32, "sqrtps")
+
+HANDLE_LIBCALL(ADD_F16, "__addhf3")
 HANDLE_LIBCALL(ADD_F32, "__addsf3")
 HANDLE_LIBCALL(ADD_F64, "__adddf3")
 HANDLE_LIBCALL(ADD_F80, "__addxf3")
 HANDLE_LIBCALL(ADD_F128, "__addtf3")
 HANDLE_LIBCALL(ADD_PPCF128, "__gcc_qadd")
+HANDLE_LIBCALL(SUB_F16, "__subhf3")
 HANDLE_LIBCALL(SUB_F32, "__subsf3")
 HANDLE_LIBCALL(SUB_F64, "__subdf3")
 HANDLE_LIBCALL(SUB_F80, "__subxf3")
 HANDLE_LIBCALL(SUB_F128, "__subtf3")
 HANDLE_LIBCALL(SUB_PPCF128, "__gcc_qsub")
+HANDLE_LIBCALL(MUL_F16, "__mulhf3")
 HANDLE_LIBCALL(MUL_F32, "__mulsf3")
 HANDLE_LIBCALL(MUL_F64, "__muldf3")
 HANDLE_LIBCALL(MUL_F80, "__mulxf3")
 HANDLE_LIBCALL(MUL_F128, "__multf3")
 HANDLE_LIBCALL(MUL_PPCF128, "__gcc_qmul")
+HANDLE_LIBCALL(DIV_F16, "__divhf3")
 HANDLE_LIBCALL(DIV_F32, "__divsf3")
 HANDLE_LIBCALL(DIV_F64, "__divdf3")
 HANDLE_LIBCALL(DIV_F80, "__divxf3")
 HANDLE_LIBCALL(DIV_F128, "__divtf3")
 HANDLE_LIBCALL(DIV_PPCF128, "__gcc_qdiv")
+HANDLE_LIBCALL(REM_F16, "fmodh")
 HANDLE_LIBCALL(REM_F32, "fmodf")
 HANDLE_LIBCALL(REM_F64, "fmod")
 HANDLE_LIBCALL(REM_F80, "fmodl")
 HANDLE_LIBCALL(REM_F128, "fmodl")
 HANDLE_LIBCALL(REM_PPCF128, "fmodl")
+HANDLE_LIBCALL(FMA_F16, "fmah")
 HANDLE_LIBCALL(FMA_F32, "fmaf")
 HANDLE_LIBCALL(FMA_F64, "fma")
 HANDLE_LIBCALL(FMA_F80, "fmal")
 HANDLE_LIBCALL(FMA_F128, "fmal")
 HANDLE_LIBCALL(FMA_PPCF128, "fmal")
+HANDLE_LIBCALL(POWI_F16, "__powihf2")
 HANDLE_LIBCALL(POWI_F32, "__powisf2")
 HANDLE_LIBCALL(POWI_F64, "__powidf2")
 HANDLE_LIBCALL(POWI_F80, "__powixf2")
 HANDLE_LIBCALL(POWI_F128, "__powitf2")
 HANDLE_LIBCALL(POWI_PPCF128, "__powitf2")
+HANDLE_LIBCALL(SQRT_F16, "sqrth")
 HANDLE_LIBCALL(SQRT_F32, "sqrtf")
 HANDLE_LIBCALL(SQRT_F64, "sqrt")
 HANDLE_LIBCALL(SQRT_F80, "sqrtl")
 HANDLE_LIBCALL(SQRT_F128, "sqrtl")
 HANDLE_LIBCALL(SQRT_PPCF128, "sqrtl")
+HANDLE_LIBCALL(CBRT_F16, "cbrth")
 HANDLE_LIBCALL(CBRT_F32, "cbrtf")
 HANDLE_LIBCALL(CBRT_F64, "cbrt")
 HANDLE_LIBCALL(CBRT_F80, "cbrtl")
 HANDLE_LIBCALL(CBRT_F128, "cbrtl")
 HANDLE_LIBCALL(CBRT_PPCF128, "cbrtl")
+HANDLE_LIBCALL(LOG_F16, "logh")
 HANDLE_LIBCALL(LOG_F32, "logf")
 HANDLE_LIBCALL(LOG_F64, "log")
 HANDLE_LIBCALL(LOG_F80, "logl")
 HANDLE_LIBCALL(LOG_F128, "logl")
 HANDLE_LIBCALL(LOG_PPCF128, "logl")
+HANDLE_LIBCALL(LOG_FINITE_F16, "__logh_finite")
 HANDLE_LIBCALL(LOG_FINITE_F32, "__logf_finite")
 HANDLE_LIBCALL(LOG_FINITE_F64, "__log_finite")
 HANDLE_LIBCALL(LOG_FINITE_F80, "__logl_finite")
 HANDLE_LIBCALL(LOG_FINITE_F128, "__logl_finite")
 HANDLE_LIBCALL(LOG_FINITE_PPCF128, "__logl_finite")
+HANDLE_LIBCALL(LOG2_F16, "log2h")
 HANDLE_LIBCALL(LOG2_F32, "log2f")
 HANDLE_LIBCALL(LOG2_F64, "log2")
 HANDLE_LIBCALL(LOG2_F80, "log2l")
 HANDLE_LIBCALL(LOG2_F128, "log2l")
 HANDLE_LIBCALL(LOG2_PPCF128, "log2l")
+HANDLE_LIBCALL(LOG2_FINITE_F16, "__log2h_finite")
 HANDLE_LIBCALL(LOG2_FINITE_F32, "__log2f_finite")
 HANDLE_LIBCALL(LOG2_FINITE_F64, "__log2_finite")
 HANDLE_LIBCALL(LOG2_FINITE_F80, "__log2l_finite")
 HANDLE_LIBCALL(LOG2_FINITE_F128, "__log2l_finite")
 HANDLE_LIBCALL(LOG2_FINITE_PPCF128, "__log2l_finite")
+HANDLE_LIBCALL(LOG10_F16, "log10h")
 HANDLE_LIBCALL(LOG10_F32, "log10f")
 HANDLE_LIBCALL(LOG10_F64, "log10")
 HANDLE_LIBCALL(LOG10_F80, "log10l")
 HANDLE_LIBCALL(LOG10_F128, "log10l")
 HANDLE_LIBCALL(LOG10_PPCF128, "log10l")
+HANDLE_LIBCALL(LOG10_FINITE_F16, "__log10h_finite")
 HANDLE_LIBCALL(LOG10_FINITE_F32, "__log10f_finite")
 HANDLE_LIBCALL(LOG10_FINITE_F64, "__log10_finite")
 HANDLE_LIBCALL(LOG10_FINITE_F80, "__log10l_finite")
 HANDLE_LIBCALL(LOG10_FINITE_F128, "__log10l_finite")
 HANDLE_LIBCALL(LOG10_FINITE_PPCF128, "__log10l_finite")
+HANDLE_LIBCALL(EXP_F16, "exph")
 HANDLE_LIBCALL(EXP_F32, "expf")
 HANDLE_LIBCALL(EXP_F64, "exp")
 HANDLE_LIBCALL(EXP_F80, "expl")
 HANDLE_LIBCALL(EXP_F128, "expl")
 HANDLE_LIBCALL(EXP_PPCF128, "expl")
+HANDLE_LIBCALL(EXP_FINITE_F16, "__exph_finite")
 HANDLE_LIBCALL(EXP_FINITE_F32, "__expf_finite")
 HANDLE_LIBCALL(EXP_FINITE_F64, "__exp_finite")
 HANDLE_LIBCALL(EXP_FINITE_F80, "__expl_finite")
 HANDLE_LIBCALL(EXP_FINITE_F128, "__expl_finite")
 HANDLE_LIBCALL(EXP_FINITE_PPCF128, "__expl_finite")
+HANDLE_LIBCALL(EXP2_F16, "exp2h")
 HANDLE_LIBCALL(EXP2_F32, "exp2f")
 HANDLE_LIBCALL(EXP2_F64, "exp2")
 HANDLE_LIBCALL(EXP2_F80, "exp2l")
 HANDLE_LIBCALL(EXP2_F128, "exp2l")
 HANDLE_LIBCALL(EXP2_PPCF128, "exp2l")
+HANDLE_LIBCALL(EXP2_FINITE_F16, "__exp2h_finite")
 HANDLE_LIBCALL(EXP2_FINITE_F32, "__exp2f_finite")
 HANDLE_LIBCALL(EXP2_FINITE_F64, "__exp2_finite")
 HANDLE_LIBCALL(EXP2_FINITE_F80, "__exp2l_finite")
 HANDLE_LIBCALL(EXP2_FINITE_F128, "__exp2l_finite")
 HANDLE_LIBCALL(EXP2_FINITE_PPCF128, "__exp2l_finite")
+HANDLE_LIBCALL(SIN_F16, "sinf16")
 HANDLE_LIBCALL(SIN_F32, "sinf")
 HANDLE_LIBCALL(SIN_F64, "sin")
 HANDLE_LIBCALL(SIN_F80, "sinl")
 HANDLE_LIBCALL(SIN_F128, "sinl")
 HANDLE_LIBCALL(SIN_PPCF128, "sinl")
+HANDLE_LIBCALL(COS_F16, "cosf16")
 HANDLE_LIBCALL(COS_F32, "cosf")
 HANDLE_LIBCALL(COS_F64, "cos")
 HANDLE_LIBCALL(COS_F80, "cosl")
 HANDLE_LIBCALL(COS_F128, "cosl")
 HANDLE_LIBCALL(COS_PPCF128, "cosl")
+HANDLE_LIBCALL(SINCOS_F16, nullptr)
 HANDLE_LIBCALL(SINCOS_F32, nullptr)
 HANDLE_LIBCALL(SINCOS_F64, nullptr)
 HANDLE_LIBCALL(SINCOS_F80, nullptr)
@@ -199,81 +240,97 @@ HANDLE_LIBCALL(SINCOS_F128, nullptr)
 HANDLE_LIBCALL(SINCOS_PPCF128, nullptr)
 HANDLE_LIBCALL(SINCOS_STRET_F32, nullptr)
 HANDLE_LIBCALL(SINCOS_STRET_F64, nullptr)
+HANDLE_LIBCALL(POW_F16, "powh")
 HANDLE_LIBCALL(POW_F32, "powf")
 HANDLE_LIBCALL(POW_F64, "pow")
 HANDLE_LIBCALL(POW_F80, "powl")
 HANDLE_LIBCALL(POW_F128, "powl")
 HANDLE_LIBCALL(POW_PPCF128, "powl")
+HANDLE_LIBCALL(POW_FINITE_F16, "__powh_finite")
 HANDLE_LIBCALL(POW_FINITE_F32, "__powf_finite")
 HANDLE_LIBCALL(POW_FINITE_F64, "__pow_finite")
 HANDLE_LIBCALL(POW_FINITE_F80, "__powl_finite")
 HANDLE_LIBCALL(POW_FINITE_F128, "__powl_finite")
 HANDLE_LIBCALL(POW_FINITE_PPCF128, "__powl_finite")
+HANDLE_LIBCALL(CEIL_F16, "ceilh")
 HANDLE_LIBCALL(CEIL_F32, "ceilf")
 HANDLE_LIBCALL(CEIL_F64, "ceil")
 HANDLE_LIBCALL(CEIL_F80, "ceill")
 HANDLE_LIBCALL(CEIL_F128, "ceill")
 HANDLE_LIBCALL(CEIL_PPCF128, "ceill")
+HANDLE_LIBCALL(TRUNC_F16, "trunch")
 HANDLE_LIBCALL(TRUNC_F32, "truncf")
 HANDLE_LIBCALL(TRUNC_F64, "trunc")
 HANDLE_LIBCALL(TRUNC_F80, "truncl")
 HANDLE_LIBCALL(TRUNC_F128, "truncl")
 HANDLE_LIBCALL(TRUNC_PPCF128, "truncl")
+HANDLE_LIBCALL(RINT_F16, "rinth")
 HANDLE_LIBCALL(RINT_F32, "rintf")
 HANDLE_LIBCALL(RINT_F64, "rint")
 HANDLE_LIBCALL(RINT_F80, "rintl")
 HANDLE_LIBCALL(RINT_F128, "rintl")
 HANDLE_LIBCALL(RINT_PPCF128, "rintl")
+HANDLE_LIBCALL(NEARBYINT_F16, "nearbyinth")
 HANDLE_LIBCALL(NEARBYINT_F32, "nearbyintf")
 HANDLE_LIBCALL(NEARBYINT_F64, "nearbyint")
 HANDLE_LIBCALL(NEARBYINT_F80, "nearbyintl")
 HANDLE_LIBCALL(NEARBYINT_F128, "nearbyintl")
 HANDLE_LIBCALL(NEARBYINT_PPCF128, "nearbyintl")
+HANDLE_LIBCALL(ROUND_F16, "roundh")
 HANDLE_LIBCALL(ROUND_F32, "roundf")
 HANDLE_LIBCALL(ROUND_F64, "round")
 HANDLE_LIBCALL(ROUND_F80, "roundl")
 HANDLE_LIBCALL(ROUND_F128, "roundl")
 HANDLE_LIBCALL(ROUND_PPCF128, "roundl")
+HANDLE_LIBCALL(ROUNDEVEN_F16, "roundevenh")
 HANDLE_LIBCALL(ROUNDEVEN_F32, "roundevenf")
 HANDLE_LIBCALL(ROUNDEVEN_F64, "roundeven")
 HANDLE_LIBCALL(ROUNDEVEN_F80, "roundevenl")
 HANDLE_LIBCALL(ROUNDEVEN_F128, "roundevenl")
 HANDLE_LIBCALL(ROUNDEVEN_PPCF128, "roundevenl")
+HANDLE_LIBCALL(FLOOR_F16, "floorh")
 HANDLE_LIBCALL(FLOOR_F32, "floorf")
 HANDLE_LIBCALL(FLOOR_F64, "floor")
 HANDLE_LIBCALL(FLOOR_F80, "floorl")
 HANDLE_LIBCALL(FLOOR_F128, "floorl")
 HANDLE_LIBCALL(FLOOR_PPCF128, "floorl")
+HANDLE_LIBCALL(COPYSIGN_F16, "copysignh")
 HANDLE_LIBCALL(COPYSIGN_F32, "copysignf")
 HANDLE_LIBCALL(COPYSIGN_F64, "copysign")
 HANDLE_LIBCALL(COPYSIGN_F80, "copysignl")
 HANDLE_LIBCALL(COPYSIGN_F128, "copysignl")
 HANDLE_LIBCALL(COPYSIGN_PPCF128, "copysignl")
+HANDLE_LIBCALL(FMIN_F16, "fminh")
 HANDLE_LIBCALL(FMIN_F32, "fminf")
 HANDLE_LIBCALL(FMIN_F64, "fmin")
 HANDLE_LIBCALL(FMIN_F80, "fminl")
 HANDLE_LIBCALL(FMIN_F128, "fminl")
 HANDLE_LIBCALL(FMIN_PPCF128, "fminl")
+HANDLE_LIBCALL(FMAX_F16, "fmaxh")
 HANDLE_LIBCALL(FMAX_F32, "fmaxf")
 HANDLE_LIBCALL(FMAX_F64, "fmax")
 HANDLE_LIBCALL(FMAX_F80, "fmaxl")
 HANDLE_LIBCALL(FMAX_F128, "fmaxl")
 HANDLE_LIBCALL(FMAX_PPCF128, "fmaxl")
+HANDLE_LIBCALL(LROUND_F16, "lroundh")
 HANDLE_LIBCALL(LROUND_F32, "lroundf")
 HANDLE_LIBCALL(LROUND_F64, "lround")
 HANDLE_LIBCALL(LROUND_F80, "lroundl")
 HANDLE_LIBCALL(LROUND_F128, "lroundl")
 HANDLE_LIBCALL(LROUND_PPCF128, "lroundl")
+HANDLE_LIBCALL(LLROUND_F16, "llroundh")
 HANDLE_LIBCALL(LLROUND_F32, "llroundf")
 HANDLE_LIBCALL(LLROUND_F64, "llround")
 HANDLE_LIBCALL(LLROUND_F80, "llroundl")
 HANDLE_LIBCALL(LLROUND_F128, "llroundl")
 HANDLE_LIBCALL(LLROUND_PPCF128, "llroundl")
+HANDLE_LIBCALL(LRINT_F16, "lrinth")
 HANDLE_LIBCALL(LRINT_F32, "lrintf")
 HANDLE_LIBCALL(LRINT_F64, "lrint")
 HANDLE_LIBCALL(LRINT_F80, "lrintl")
 HANDLE_LIBCALL(LRINT_F128, "lrintl")
 HANDLE_LIBCALL(LRINT_PPCF128, "lrintl")
+HANDLE_LIBCALL(LLRINT_F16, "llrinth")
 HANDLE_LIBCALL(LLRINT_F32, "llrintf")
 HANDLE_LIBCALL(LLRINT_F64, "llrint")
 HANDLE_LIBCALL(LLRINT_F80, "llrintl")
@@ -303,6 +360,7 @@ HANDLE_LIBCALL(FPROUND_F80_F64, "__truncxfdf2")
 HANDLE_LIBCALL(FPROUND_F128_F64, "__trunctfdf2")
 HANDLE_LIBCALL(FPROUND_PPCF128_F64, "__gcc_qtod")
 HANDLE_LIBCALL(FPROUND_F128_F80, "__trunctfxf2")
+HANDLE_LIBCALL(FPTOSINT_F16_I16, "__fixhfhi")
 HANDLE_LIBCALL(FPTOSINT_F16_I32, "__fixhfsi")
 HANDLE_LIBCALL(FPTOSINT_F16_I64, "__fixhfdi")
 HANDLE_LIBCALL(FPTOSINT_F16_I128, "__fixhfti")
@@ -321,6 +379,7 @@ HANDLE_LIBCALL(FPTOSINT_F128_I128, "__fixtfti")
 HANDLE_LIBCALL(FPTOSINT_PPCF128_I32, "__gcc_qtou")
 HANDLE_LIBCALL(FPTOSINT_PPCF128_I64, "__fixtfdi")
 HANDLE_LIBCALL(FPTOSINT_PPCF128_I128, "__fixtfti")
+HANDLE_LIBCALL(FPTOUINT_F16_I16, "__fixunshfhi")
 HANDLE_LIBCALL(FPTOUINT_F16_I32, "__fixunshfsi")
 HANDLE_LIBCALL(FPTOUINT_F16_I64, "__fixunshfdi")
 HANDLE_LIBCALL(FPTOUINT_F16_I128, "__fixunshfti")
@@ -377,30 +436,37 @@ HANDLE_LIBCALL(UINTTOFP_I128_F128, "__floatuntitf")
 HANDLE_LIBCALL(UINTTOFP_I128_PPCF128, "__floatuntitf")
 
 // Comparison
+HANDLE_LIBCALL(OEQ_F16, "__eqhf2")
 HANDLE_LIBCALL(OEQ_F32, "__eqsf2")
 HANDLE_LIBCALL(OEQ_F64, "__eqdf2")
 HANDLE_LIBCALL(OEQ_F128, "__eqtf2")
 HANDLE_LIBCALL(OEQ_PPCF128, "__gcc_qeq")
+HANDLE_LIBCALL(UNE_F16, "__nehf2")
 HANDLE_LIBCALL(UNE_F32, "__nesf2")
 HANDLE_LIBCALL(UNE_F64, "__nedf2")
 HANDLE_LIBCALL(UNE_F128, "__netf2")
 HANDLE_LIBCALL(UNE_PPCF128, "__gcc_qne")
+HANDLE_LIBCALL(OGE_F16, "__gehf2")
 HANDLE_LIBCALL(OGE_F32, "__gesf2")
 HANDLE_LIBCALL(OGE_F64, "__gedf2")
 HANDLE_LIBCALL(OGE_F128, "__getf2")
 HANDLE_LIBCALL(OGE_PPCF128, "__gcc_qge")
+HANDLE_LIBCALL(OLT_F16, "__lthf2")
 HANDLE_LIBCALL(OLT_F32, "__ltsf2")
 HANDLE_LIBCALL(OLT_F64, "__ltdf2")
 HANDLE_LIBCALL(OLT_F128, "__lttf2")
 HANDLE_LIBCALL(OLT_PPCF128, "__gcc_qlt")
+HANDLE_LIBCALL(OLE_F16, "__lehf2")
 HANDLE_LIBCALL(OLE_F32, "__lesf2")
 HANDLE_LIBCALL(OLE_F64, "__ledf2")
 HANDLE_LIBCALL(OLE_F128, "__letf2")
 HANDLE_LIBCALL(OLE_PPCF128, "__gcc_qle")
+HANDLE_LIBCALL(OGT_F16, "__gthf2")
 HANDLE_LIBCALL(OGT_F32, "__gtsf2")
 HANDLE_LIBCALL(OGT_F64, "__gtdf2")
 HANDLE_LIBCALL(OGT_F128, "__gttf2")
 HANDLE_LIBCALL(OGT_PPCF128, "__gcc_qgt")
+HANDLE_LIBCALL(UO_F16, "__unordhf2")
 HANDLE_LIBCALL(UO_F32, "__unordsf2")
 HANDLE_LIBCALL(UO_F64, "__unorddf2")
 HANDLE_LIBCALL(UO_F128, "__unordtf2")
diff --git a/llvm/include/llvm/IR/Type.h b/llvm/include/llvm/IR/Type.h
index 430bc34a47e7..683b31f41d25 100644
--- a/llvm/include/llvm/IR/Type.h
+++ b/llvm/include/llvm/IR/Type.h
@@ -74,7 +74,8 @@ public:
     StructTyID,        ///< Structures
     ArrayTyID,         ///< Arrays
     FixedVectorTyID,   ///< Fixed width SIMD vector type
-    ScalableVectorTyID ///< Scalable SIMD vector type
+    ScalableVectorTyID,///< Scalable SIMD vector type
+    SubwordVectorTyID  ///< Subword SIMD vector type
   };
 
 private:
@@ -235,7 +236,7 @@ public:
 
   /// True if this is an instance of VectorType.
   inline bool isVectorTy() const {
-    return getTypeID() == ScalableVectorTyID || getTypeID() == FixedVectorTyID;
+    return getTypeID() == ScalableVectorTyID || getTypeID() == FixedVectorTyID || getTypeID() == SubwordVectorTyID;
   }
 
   /// Return true if this type could be converted with a lossless BitCast to
@@ -382,6 +383,8 @@ public:
     return ContainedTys[0];
   }
 
+  inline bool getVectorIsSubword() const;
+
   /// Given vector type, change the element type,
   /// whilst keeping the old number of elements.
   /// For non-vectors simply returns \p EltTy.
diff --git a/llvm/include/llvm/Support/MachineValueType.h b/llvm/include/llvm/Support/MachineValueType.h
index 5c73cece85c3..9ca3d6e0be25 100644
--- a/llvm/include/llvm/Support/MachineValueType.h
+++ b/llvm/include/llvm/Support/MachineValueType.h
@@ -254,23 +254,42 @@ namespace llvm {
       FIRST_SCALABLE_VECTOR_VALUETYPE = nxv1i1,
       LAST_SCALABLE_VECTOR_VALUETYPE = nxv8f64,
 
+      //vswp32        =  171,   // subword 1/2/3/4/8/16 bits packed in i32 (normally 32 x  1b in i32)
+      //vswp64        =  172,   // subword 1/2/3/4/8/16/32 bits packed in i64 (normally 64 x  1b in i64)
+      vswp32i1        =  171,   // subword 1 bit packed in i32 (normally 32 x  1b in i32)
+      vswp32i2        =  172,   // subword 2 bit packed in i32 (normally 16 x  2b in i32)
+      vswp32i3        =  173,   // subword 3 bit packed in i32 (normally 10 x  3b in i32)
+      vswp32i4        =  174,   // subword 4 bit packed in i32 (normally 8 x  4b in i32)
+      vswp32i8        =  175,   // subword 8 bit packed in i32 (normally 4 x  8b in i32)
+      vswp32i16       =  176,   // subword 16 bit packed in i32 (normally 2 x  16b in i32)
+      vswp64i1        =  177,   // subword 1 bit packed in i64 (normally 64 x  1b in i64)
+      vswp64i2        =  178,   // subword 2 bit packed in i64 (normally 32 x  2b in i64)
+      vswp64i3        =  179,   // subword 3 bit packed in i64 (normally 21 x  3b in i64)
+      vswp64i4        =  180,   // subword 4 bit packed in i64 (normally 16 x  4b in i64)
+      vswp64i8        =  181,   // subword 8 bit packed in i64 (normally 8 x  8b in i64)
+      vswp64i16       =  182,   // subword 16 bit packed in i64 (normally 4 x  16b in i64)
+      vswp64i32       =  183,   // subword 32 bit packed in i64 (normally 2 x  32b in i64)
+
+      FIRST_SUBWORD_VECTOR_VALUETYPE = vswp32i1,
+      LAST_SUBWORD_VECTOR_VALUETYPE = vswp64i32,
+
       FIRST_VECTOR_VALUETYPE = v1i1,
-      LAST_VECTOR_VALUETYPE  = nxv8f64,
+      LAST_VECTOR_VALUETYPE  = vswp64i32,
 
-      x86mmx         = 171,    // This is an X86 MMX value
+      x86mmx         = 184,    // This is an X86 MMX value
 
-      Glue           = 172,    // This glues nodes together during pre-RA sched
+      Glue           = 185,    // This glues nodes together during pre-RA sched
 
-      isVoid         = 173,    // This has no value
+      isVoid         = 186,    // This has no value
 
-      Untyped        = 174,    // This value takes a register, but has
+      Untyped        = 187,    // This value takes a register, but has
                                // unspecified type.  The register class
                                // will be determined by the opcode.
 
-      funcref        = 175,    // WebAssembly's funcref type
-      externref      = 176,    // WebAssembly's externref type
-      x86amx         = 177,    // This is an X86 AMX value
-      i64x8          = 178,    // 8 Consecutive GPRs (AArch64)
+      funcref        = 188,    // WebAssembly's funcref type
+      externref      = 189,    // WebAssembly's externref type
+      x86amx         = 190,    // This is an X86 AMX value
+      i64x8          = 191,    // 8 Consecutive GPRs (AArch64)
 
       FIRST_VALUETYPE =  1,    // This is always the beginning of the list.
       LAST_VALUETYPE = i64x8,  // This always remains at the end of the list.
@@ -353,7 +372,10 @@ namespace llvm {
               (SimpleTy >= MVT::FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE &&
                SimpleTy <= MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE) ||
               (SimpleTy >= MVT::FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE &&
-               SimpleTy <= MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE));
+               SimpleTy <= MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE) ||
+              (SimpleTy >= MVT::FIRST_SUBWORD_VECTOR_VALUETYPE &&
+               SimpleTy <= MVT::LAST_SUBWORD_VECTOR_VALUETYPE)
+               );
     }
 
     /// Return true if this is an integer, not including vectors.
@@ -375,9 +397,16 @@ namespace llvm {
               SimpleTy <= MVT::LAST_SCALABLE_VECTOR_VALUETYPE);
     }
 
+    bool isSubwordVector() const {
+      return (SimpleTy >= MVT::FIRST_SUBWORD_VECTOR_VALUETYPE &&
+              SimpleTy <= MVT::LAST_SUBWORD_VECTOR_VALUETYPE);
+    }
+
     bool isFixedLengthVector() const {
-      return (SimpleTy >= MVT::FIRST_FIXEDLEN_VECTOR_VALUETYPE &&
-              SimpleTy <= MVT::LAST_FIXEDLEN_VECTOR_VALUETYPE);
+      return ((SimpleTy >= MVT::FIRST_FIXEDLEN_VECTOR_VALUETYPE &&
+              SimpleTy <= MVT::LAST_FIXEDLEN_VECTOR_VALUETYPE) ||
+              (SimpleTy >= MVT::FIRST_SUBWORD_VECTOR_VALUETYPE &&
+              SimpleTy <= MVT::LAST_SUBWORD_VECTOR_VALUETYPE));
     }
 
     /// Return true if this is a 16-bit vector type.
@@ -391,7 +420,9 @@ namespace llvm {
       return (SimpleTy == MVT::v32i1 || SimpleTy == MVT::v4i8   ||
               SimpleTy == MVT::v2i16 || SimpleTy == MVT::v1i32  ||
               SimpleTy == MVT::v2f16 || SimpleTy == MVT::v2bf16 ||
-              SimpleTy == MVT::v1f32);
+              SimpleTy == MVT::v1f32 ||
+              (SimpleTy >= MVT::FIRST_SUBWORD_VECTOR_VALUETYPE &&   /* all subword types are i32 vectors in this version */
+               SimpleTy <= MVT::LAST_SUBWORD_VECTOR_VALUETYPE));
     }
 
     /// Return true if this is a 64-bit vector type.
@@ -676,6 +707,21 @@ namespace llvm {
       case nxv2f64:
       case nxv4f64:
       case nxv8f64: return f64;
+
+      /* TODO: return real element type for subword types (e.g. i3, i4 do not exist) */
+      case vswp32i1:
+      case vswp32i2:
+      case vswp32i3:
+      case vswp32i4:
+      case vswp32i8:
+      case vswp32i16: return i32;
+      case vswp64i1:
+      case vswp64i2:
+      case vswp64i3:
+      case vswp64i4:
+      case vswp64i8:
+      case vswp64i16:
+      case vswp64i32: return i64;
       }
     }
 
@@ -840,10 +886,29 @@ namespace llvm {
       case nxv1bf16:
       case nxv1f32:
       case nxv1f64: return 1;
+
+      case vswp32i1:
+      case vswp32i2:
+      case vswp32i3:
+      case vswp32i4:
+      case vswp32i8:
+      case vswp32i16: return 1;
+      case vswp64i1:
+      case vswp64i2:
+      case vswp64i3:
+      case vswp64i4:
+      case vswp64i8:
+      case vswp64i16:
+      case vswp64i32: return 1;
+
       }
     }
 
     ElementCount getVectorElementCount() const {
+      // TODO ? check if the function always returns required value for subword types (maybe in some cases it should return 32 instead of number of elements in the basic type
+      if (isSubwordVector()) {
+        return ElementCount::get(getVectorNumElements(), false);  /* it depends on all elements are required or elements packed in the basic type */
+      }
       return ElementCount::get(getVectorMinNumElements(), isScalableVector());
     }
 
@@ -852,6 +917,36 @@ namespace llvm {
       return getVectorMinNumElements();
     }
 
+    unsigned getSubwordElmBitWidth() const {
+      if (SimpleTy==MVT::vswp32i1 || SimpleTy==MVT::vswp64i1) return 1;
+      if (SimpleTy==MVT::vswp32i2 || SimpleTy==MVT::vswp64i2) return 2;
+      if (SimpleTy==MVT::vswp32i3 || SimpleTy==MVT::vswp64i3) return 3;
+      if (SimpleTy==MVT::vswp32i4 || SimpleTy==MVT::vswp64i4) return 4;
+      if (SimpleTy==MVT::vswp32i8 || SimpleTy==MVT::vswp64i8) return 8;
+      if (SimpleTy==MVT::vswp32i16 || SimpleTy==MVT::vswp64i16) return 16;
+      if (SimpleTy==MVT::vswp64i32) return 32;
+      return 0;
+    }
+
+    unsigned getSubwordPacking() const {
+      switch (SimpleTy) {
+        default: return 1; /* or return 0 for all other types */
+        case MVT::vswp64i1: return 64;
+        case MVT::vswp32i1:
+        case MVT::vswp64i2: return 32;
+        case MVT::vswp64i3: return 21;
+        case MVT::vswp32i2:
+        case MVT::vswp64i4: return 16;
+        case MVT::vswp32i3: return 10;
+        case MVT::vswp32i4:
+        case MVT::vswp64i8: return 8;
+        case MVT::vswp32i8:
+        case MVT::vswp64i16: return 4;
+        case MVT::vswp32i16:
+        case MVT::vswp64i32: return 2;
+      }
+    }
+
     /// Returns the size of the specified MVT in bits.
     ///
     /// If the value type is a scalable vector type, the scalable property will
@@ -916,6 +1011,24 @@ namespace llvm {
       case nxv2f16:
       case nxv2bf16:
       case nxv1f32: return TypeSize::Scalable(32);
+
+      /* subword types returns size of packet */
+//      case vswp32:  return TypeSize::Fixed(32);
+//      case vswp64:  return TypeSize::Fixed(64);
+      case vswp32i1:
+      case vswp32i2:
+      case vswp32i3:
+      case vswp32i4:
+      case vswp32i8:
+      case vswp32i16: return TypeSize::Fixed(32);
+      case vswp64i1:
+      case vswp64i2:
+      case vswp64i3:
+      case vswp64i4:
+      case vswp64i8:
+      case vswp64i16:
+      case vswp64i32: return TypeSize::Fixed(64);
+
       case v3i16:
       case v3f16:
       case v3bf16: return TypeSize::Fixed(48);
@@ -1451,6 +1564,24 @@ namespace llvm {
       return seq_inclusive(MVT::FIRST_FP_SCALABLE_VECTOR_VALUETYPE,
                            MVT::LAST_FP_SCALABLE_VECTOR_VALUETYPE);
     }
+
+    static auto subword_vector_valuetypes() {
+      return seq_inclusive(
+               MVT::FIRST_SUBWORD_VECTOR_VALUETYPE,
+               (MVT::SimpleValueType)(MVT::LAST_SUBWORD_VECTOR_VALUETYPE + 1));
+    }
+
+    static auto subword_vector_valuetypes_i32() {
+      return seq_inclusive(
+               MVT::vswp32i1,
+               (MVT::SimpleValueType)(MVT::vswp32i16 + 1));
+    }
+    static auto subword_vector_valuetypes_i64() {
+      return seq_inclusive(
+               MVT::vswp64i1,
+               (MVT::SimpleValueType)(MVT::vswp64i32 + 1));
+    }
+
     /// @}
   };
 
diff --git a/llvm/include/llvm/TableGen/Record.h b/llvm/include/llvm/TableGen/Record.h
index 713d9375448c..a1dfaeb0f8b9 100644
--- a/llvm/include/llvm/TableGen/Record.h
+++ b/llvm/include/llvm/TableGen/Record.h
@@ -1509,6 +1509,8 @@ private:
   bool IsAnonymous;
   bool IsClass;
 
+  int KindGroup;
+
   void checkName();
 
 public:
diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td
index e9720d765167..b777d19bd620 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -306,6 +306,9 @@ class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
   // the assembly matcher will provide a function to map from diagnostic types
   // to message strings.
   string DiagnosticString = "";
+
+  // User connection between register classes
+  int KindGroup = 0;
 }
 
 // The memberList in a RegisterClass is a dag of set operations. TableGen
diff --git a/llvm/include/llvm/Target/TargetOptions.h b/llvm/include/llvm/Target/TargetOptions.h
index e5bea9041479..0166c0b61581 100644
--- a/llvm/include/llvm/Target/TargetOptions.h
+++ b/llvm/include/llvm/Target/TargetOptions.h
@@ -24,6 +24,57 @@ namespace llvm {
   class MachineFunction;
   class MemoryBuffer;
 
+  namespace SoftFops {
+    enum SoftFPoperations {
+      SOFTFP_ADD  =  0,
+      SOFTFP_SUB  =  1,
+      SOFTFP_MUL  =  2,
+      SOFTFP_DIV  =  3,
+      SOFTFP_MULEX=  4,
+      SOFTFP_SQRT =  5,
+      SOFTFP_CMP  =  6,
+      SOFTFP_CI2F =  7,
+      SOFTFP_CF2I =  8,
+      SOFTFP_CFUP =  9,
+      SOFTFP_CFDN = 10,
+      SOFTFP_ABS  = 11,
+      SOFTFP_PACK = 12, // extract/pack for packed/complex registers
+      SOFTFP_MOV  = 13,
+      SOFTFP_NEG  = 14,
+    };
+    enum SoftFopsMasks {
+      FPOP_ADD  = (1<<SOFTFP_ADD), // 'a'
+      FPOP_SUB  = (1<<SOFTFP_SUB), // 's'
+      FPOP_MUL  = (1<<SOFTFP_MUL), // 'm'
+      FPOP_DIV  = (1<<SOFTFP_DIV), // 'd'
+      FPOP_MULEX= (1<<SOFTFP_MULEX), // 'M' expanding multiply (from the specific precision to higher precision)
+      FPOP_SQRT = (1<<SOFTFP_SQRT), // 'S'
+      FPOP_CMP  = (1<<SOFTFP_CMP),  // 'c'
+      FPOP_CI2F = (1<<SOFTFP_CI2F), // 'f' - convert integer into float
+      FPOP_CF2I = (1<<SOFTFP_CF2I), // 'i' - convert float into integer
+      FPOP_CFUP = (1<<SOFTFP_CFUP), // 'h' - convert float into float with higher precision (H->S,S->D,D->Q)
+      FPOP_CFDN = (1<<SOFTFP_CFDN), // 'l' - convert float into float with lower precision (D->S,S->H)
+// newly added - TODO: check the whole LLVM
+      FPOP_ABS  = (1<<SOFTFP_ABS),  // 'A'
+      FPOP_PACK = (1<<SOFTFP_PACK), // 'p' - all pack/unpack operation
+      FPOP_MOV  = (1<<SOFTFP_MOV),  // 'C' - copy register to another register
+      FPOP_NEG  = (1<<SOFTFP_NEG),  // 'n' - neg
+
+      FPOP_KNOWN_MASK = FPOP_ADD | FPOP_SUB | FPOP_MUL | FPOP_DIV |
+                        FPOP_MULEX | FPOP_SQRT | FPOP_CMP | FPOP_CI2F |
+                        FPOP_CF2I | FPOP_CFUP | FPOP_CFDN | FPOP_ABS |
+                        FPOP_PACK | FPOP_MOV | FPOP_NEG
+    };
+  }
+  namespace SwarKinds {
+    enum SWARKind {
+      Infer,
+      Audio,
+      Video,
+      ALU
+    };
+  }
+
   namespace FloatABI {
     enum ABIType {
       Default, // Target-specific (either soft or hard depending on triple, etc).
diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp
index 6e3ca5c4e08a..8dee22b2b5e9 100644
--- a/llvm/lib/Analysis/ValueTracking.cpp
+++ b/llvm/lib/Analysis/ValueTracking.cpp
@@ -259,8 +259,18 @@ bool llvm::haveNoCommonBitsSet(const Value *LHS, const Value *RHS,
                                const DataLayout &DL, AssumptionCache *AC,
                                const Instruction *CxtI, const DominatorTree *DT,
                                bool UseInstrInfo) {
-  assert(LHS->getType() == RHS->getType() &&
-         "LHS and RHS should have the same type");
+  if (LHS->getType()->isVectorTy() && RHS->getType()->isVectorTy() &&
+      (LHS->getType()->getVectorIsSubword() || RHS->getType()->getVectorIsSubword())
+     ) {
+    assert( cast<VectorType>(LHS->getType())->getElementType() ==
+            cast<VectorType>(RHS->getType())->getElementType() &&
+            cast<SubwordVectorType>(LHS->getType())->getNumElements() ==
+            cast<SubwordVectorType>(RHS->getType())->getNumElements() &&
+            "Vector LHS and RHS should be the same");
+  } else {
+    assert(LHS->getType() == RHS->getType() &&
+           "LHS and RHS should have the same type");
+  }
   assert(LHS->getType()->isIntOrIntVectorTy() &&
          "LHS and RHS should be integers");
   // Look for an inverted mask: (X & ~M) op (Y & M).
diff --git a/llvm/lib/AsmParser/LLLexer.cpp b/llvm/lib/AsmParser/LLLexer.cpp
index 4f72c6f9921a..cf251260823b 100644
--- a/llvm/lib/AsmParser/LLLexer.cpp
+++ b/llvm/lib/AsmParser/LLLexer.cpp
@@ -728,6 +728,8 @@ lltok::Kind LLLexer::LexIdentifier() {
   KEYWORD(xchg); KEYWORD(nand); KEYWORD(max); KEYWORD(min); KEYWORD(umax);
   KEYWORD(umin);
 
+  KEYWORD(subword);
+  KEYWORD(in);
   KEYWORD(vscale);
   KEYWORD(x);
   KEYWORD(blockaddress);
diff --git a/llvm/lib/AsmParser/LLParser.cpp b/llvm/lib/AsmParser/LLParser.cpp
index 799cb03c8c8c..e75596c8216b 100644
--- a/llvm/lib/AsmParser/LLParser.cpp
+++ b/llvm/lib/AsmParser/LLParser.cpp
@@ -1410,6 +1410,19 @@ static inline GlobalValue *createGlobalFwdRef(Module *M, PointerType *PTy) {
 Value *LLParser::checkValidVariableType(LocTy Loc, const Twine &Name, Type *Ty,
                                         Value *Val, bool IsCall) {
   Type *ValTy = Val->getType();
+
+  if (isa<SubwordVectorType>(ValTy) && isa<SubwordVectorType>(Ty)) do {
+    SubwordVectorType *SubValTy = cast<SubwordVectorType>(ValTy);
+    SubwordVectorType *SubTy = cast<SubwordVectorType>(Ty);
+    if (SubValTy->getBasicType()!=SubTy->getBasicType()) break;
+    if (SubValTy->getElementType()!=SubTy->getElementType()) break;
+    if (SubValTy->getNumElements()!=SubTy->getNumElements()) break;
+    if (SubValTy->getPacking()!=SubTy->getPacking()) break;
+    if (SubValTy->getSigned()!=SubTy->getSigned()) break;
+    /* all is the same ... */
+    return Val;
+  } while (0);
+
   if (ValTy == Ty)
     return Val;
   // For calls, we also allow opaque pointers.
@@ -2701,8 +2714,11 @@ bool LLParser::parseStructBody(SmallVectorImpl<Type *> &Body) {
 ///     ::= '[' APSINTVAL 'x' Types ']'
 ///     ::= '<' APSINTVAL 'x' Types '>'
 ///     ::= '<' 'vscale' 'x' APSINTVAL 'x' Types '>'
+///     ::= '<' 'subword' APSINTVAL 'x' IntTypes 'in' IntTypes {*}'>' - if '*' is used, the subword has signed basic type
 bool LLParser::parseArrayVectorType(Type *&Result, bool IsVector) {
   bool Scalable = false;
+  bool Subword = false;
+  bool Signed = false;
 
   if (IsVector && Lex.getKind() == lltok::kw_vscale) {
     Lex.Lex(); // consume the 'vscale'
@@ -2712,6 +2728,12 @@ bool LLParser::parseArrayVectorType(Type *&Result, bool IsVector) {
     Scalable = true;
   }
 
+  // subword vector
+  if (IsVector && Lex.getKind() == lltok::kw_subword) {
+    Lex.Lex(); // consume the 'subword'
+    Subword = true;
+  }
+
   if (Lex.getKind() != lltok::APSInt || Lex.getAPSIntVal().isSigned() ||
       Lex.getAPSIntVal().getBitWidth() > 64)
     return tokError("expected number in address space");
@@ -2728,6 +2750,31 @@ bool LLParser::parseArrayVectorType(Type *&Result, bool IsVector) {
   if (parseType(EltTy))
     return true;
 
+  uint64_t PackSize = 0;
+  Type *BasTy = nullptr;
+  if (Subword) { // < subword PackSz x EltTy in BasTy > -> parse 'PackSz inreg BasTy'
+    //LocTy PackSzLoc = Lex.getLoc();
+    if (Lex.getKind() != lltok::APSInt || Lex.getAPSIntVal().isSigned() ||
+        Lex.getAPSIntVal().getBitWidth() > 64)
+      return tokError("expected number as packsize");
+    //SizeLoc = Lex.getLoc();
+    PackSize = Lex.getAPSIntVal().getZExtValue();
+    Lex.Lex();
+    if (Size == 0)
+      return error(SizeLoc, "zero packsize in subword is illegal");
+
+    if (parseToken(lltok::kw_in, "expected 'in' after packsize"))
+        return true;
+
+    //TypeLoc = Lex.getLoc();
+    if (parseType(BasTy)) return true;
+
+    if (Lex.getKind() == lltok::star) {
+      Signed = true;
+      Lex.Lex();
+    }
+  }
+
   if (parseToken(IsVector ? lltok::greater : lltok::rsquare,
                  "expected end of sequential type"))
     return true;
@@ -2737,9 +2784,13 @@ bool LLParser::parseArrayVectorType(Type *&Result, bool IsVector) {
       return error(SizeLoc, "zero element vector is illegal");
     if ((unsigned)Size != Size)
       return error(SizeLoc, "size too large for vector");
-    if (!VectorType::isValidElementType(EltTy))
-      return error(TypeLoc, "invalid vector element type");
-    Result = VectorType::get(EltTy, unsigned(Size), Scalable);
+    if (Subword && EltTy->isIntegerTy()) {
+      Result = VectorType::get(EltTy, unsigned(Size), BasTy, unsigned(PackSize), Signed);
+    } else {
+      if (!VectorType::isValidElementType(EltTy))
+        return error(TypeLoc, "invalid vector element type");
+      Result = VectorType::get(EltTy, unsigned(Size), Scalable);
+    }
   } else {
     if (!ArrayType::isValidElementType(EltTy))
       return error(TypeLoc, "invalid array element type");
diff --git a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
index d5e366c21f7d..497c188bbed9 100644
--- a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
+++ b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
@@ -1907,16 +1907,25 @@ Error BitcodeReader::parseTypeTableBody() {
       ResultTy = ArrayType::get(ResultTy, Record[0]);
       break;
     case bitc::TYPE_CODE_VECTOR:    // VECTOR: [numelts, eltty] or
-                                    //         [numelts, eltty, scalable]
-      if (Record.size() < 2)
+                                    //         [numelts, eltty, scalable] or
+                                    //         [numelts, eltty, packsz, basty, BTsigned]
+      if (Record.size() < 2 || Record.size()==4 || Record.size()>5)
         return error("Invalid record");
       if (Record[0] == 0)
         return error("Invalid vector length");
       ResultTy = getTypeByID(Record[1]);
       if (!ResultTy || !StructType::isValidElementType(ResultTy))
         return error("Invalid type");
-      bool Scalable = Record.size() > 2 ? Record[2] : false;
-      ResultTy = VectorType::get(ResultTy, Record[0], Scalable);
+      if (Record.size()>3) { // SWAR subword vector
+        unsigned bid = Record[3];
+        Type *BasTy = getTypeByID(bid);
+        bool BTsigned = Record.size() > 4 ? Record[4] : false;
+        ResultTy = VectorType::get(ResultTy, Record[0], BasTy,
+                                   Record[2], BTsigned);
+      } else { // Scalable vector
+        bool Scalable = Record.size() > 2 ? Record[2] : false;
+        ResultTy = VectorType::get(ResultTy, Record[0], Scalable);
+      }
       break;
     }
 
@@ -3804,9 +3813,23 @@ Error BitcodeReader::typeCheckLoadStoreInst(Type *ValType, Type *PtrType) {
   if (!isa<PointerType>(PtrType))
     return error("Load/Store operand is not a pointer type");
 
-  if (!cast<PointerType>(PtrType)->isOpaqueOrPointeeTypeMatches(ValType))
-    return error("Explicit load/store type does not match pointee "
-                 "type of pointer operand");
+  bool chck = true;
+  if (PtrType->getNumContainedTypes()>0) {
+    Type *pct = PtrType->getContainedType(0);
+    if (isa<SubwordVectorType>(pct) && isa<IntegerType>(ValType)) {
+      SubwordVectorType *svt = cast<SubwordVectorType>(pct);
+      if (svt->getBasicType()==ValType) chck = false; /* basic of subwordvectortype(pointed by ptrtype) is the same as valtype */
+    } else if (isa<IntegerType>(pct) && isa<SubwordVectorType>(ValType)) {
+      SubwordVectorType *svt = cast<SubwordVectorType>(ValType);
+      if (pct==svt->getBasicType()) chck = false; /* basic of valtype(subwordvectortype) is the same as pointed valtype */
+    }
+  }
+
+  if (chck) {
+    if (!cast<PointerType>(PtrType)->isOpaqueOrPointeeTypeMatches(ValType))
+      return error("Explicit load/store type does not match pointee "
+                   "type of pointer operand");
+  }
   if (!PointerType::isLoadableOrStorableType(ValType))
     return error("Cannot load/store from pointer");
   return Error::success();
@@ -4055,7 +4078,7 @@ Error BitcodeReader::parseFunctionBody(Function *F) {
       unsigned OpNum = 0;
       Value *LHS, *RHS;
       if (getValueTypePair(Record, OpNum, NextValueNo, LHS) ||
-          popValue(Record, OpNum, NextValueNo, LHS->getType(), RHS) ||
+          getValueTypePair(Record, OpNum, NextValueNo, RHS) ||
           OpNum+1 > Record.size())
         return error("Invalid record");
 
@@ -4311,8 +4334,13 @@ Error BitcodeReader::parseFunctionBody(Function *F) {
         return error("Invalid record");
       if (!Vec->getType()->isVectorTy())
         return error("Invalid type for value");
-      if (popValue(Record, OpNum, NextValueNo,
-                   cast<VectorType>(Vec->getType())->getElementType(), Elt) ||
+      bool pv = popValue(Record, OpNum, NextValueNo,
+                   cast<VectorType>(Vec->getType())->getElementType(), Elt);
+      if (pv && isa<SubwordVectorType>(Vec->getType())) {
+        pv = popValue(Record, OpNum, NextValueNo,
+                   cast<SubwordVectorType>(Vec->getType())->getBasicType(), Elt);
+      }
+      if (pv ||
           getValueTypePair(Record, OpNum, NextValueNo, Idx))
         return error("Invalid record");
       I = InsertElementInst::Create(Vec, Elt, Idx);
@@ -4346,10 +4374,15 @@ Error BitcodeReader::parseFunctionBody(Function *F) {
 
       unsigned OpNum = 0;
       Value *LHS, *RHS;
+#if 0
       if (getValueTypePair(Record, OpNum, NextValueNo, LHS) ||
           popValue(Record, OpNum, NextValueNo, LHS->getType(), RHS))
         return error("Invalid record");
-
+#else
+      if (getValueTypePair(Record, OpNum, NextValueNo, LHS) ||
+          getValueTypePair(Record, OpNum, NextValueNo, RHS))
+        return error("Invalid record");
+#endif
       if (OpNum >= Record.size())
         return error(
             "Invalid record: operand number exceeded available operands");
diff --git a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
index 0a202c376981..4473b9ebd996 100644
--- a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
+++ b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
@@ -1005,15 +1005,25 @@ void ModuleBitcodeWriter::writeTypeTable() {
       break;
     }
     case Type::FixedVectorTyID:
-    case Type::ScalableVectorTyID: {
+    case Type::ScalableVectorTyID:
+    case Type::SubwordVectorTyID: {
       VectorType *VT = cast<VectorType>(T);
       // VECTOR [numelts, eltty] or
-      //        [numelts, eltty, scalable]
+      //        [numelts, eltty, scalable] or
+      //        [numelts, eltty, packsz, basty, btsign]
       Code = bitc::TYPE_CODE_VECTOR;
       TypeVals.push_back(VT->getElementCount().getKnownMinValue());
       TypeVals.push_back(VE.getTypeID(VT->getElementType()));
-      if (isa<ScalableVectorType>(VT))
+      if (isa<ScalableVectorType>(VT)) {
         TypeVals.push_back(true);
+      } else if (isa<SubwordVectorType>(VT)) {
+        SubwordVectorType *SubVT = cast<SubwordVectorType>(VT);
+        TypeVals.push_back(SubVT->getPacking());
+        Type *BT = SubVT->getBasicType();
+        TypeVals.push_back(VE.getTypeID(BT));
+        TypeVals.push_back(SubVT->getSigned());
+        //AbbrevToUse=0;
+      }
       break;
     }
     }
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index d92b23f56e4d..d77022688d9c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -137,9 +137,9 @@ private:
 
   void ExpandFPLibCall(SDNode *Node, RTLIB::Libcall LC,
                        SmallVectorImpl<SDValue> &Results);
-  void ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
-                       RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
-                       RTLIB::Libcall Call_F128,
+  void ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F16,
+                       RTLIB::Libcall Call_F32, RTLIB::Libcall Call_F64,
+                       RTLIB::Libcall Call_F80, RTLIB::Libcall Call_F128,
                        RTLIB::Libcall Call_PPCF128,
                        SmallVectorImpl<SDValue> &Results);
   SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
@@ -148,7 +148,7 @@ private:
                            RTLIB::Libcall Call_I32,
                            RTLIB::Libcall Call_I64,
                            RTLIB::Libcall Call_I128);
-  void ExpandArgFPLibCall(SDNode *Node,
+  void ExpandArgFPLibCall(SDNode *Node, RTLIB::Libcall Call_F16,
                           RTLIB::Libcall Call_F32, RTLIB::Libcall Call_F64,
                           RTLIB::Libcall Call_F80, RTLIB::Libcall Call_F128,
                           RTLIB::Libcall Call_PPCF128,
@@ -967,16 +967,28 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
 
 #ifndef NDEBUG
   for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
-    assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
-             TargetLowering::TypeLegal &&
+    assert((TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
+             TargetLowering::TypeLegal || 
+            TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
+             TargetLowering::TypePromoteInteger) &&
            "Unexpected illegal type!");
 
-  for (const SDValue &Op : Node->op_values())
+  for (const SDValue &Op : Node->op_values()) {
+    if (TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) !=
+              TargetLowering::TypeLegal &&
+        TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) !=
+              TargetLowering::TypePromoteInteger &&
+            Op.getOpcode() != ISD::TargetConstant &&
+            Op.getOpcode() != ISD::Register) {
+    }
     assert((TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) ==
               TargetLowering::TypeLegal ||
+            TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) ==
+              TargetLowering::TypePromoteInteger ||
             Op.getOpcode() == ISD::TargetConstant ||
             Op.getOpcode() == ISD::Register) &&
             "Unexpected illegal type!");
+  }
 #endif
 
   // Figure out the correct action; the way to query this varies by opcode
@@ -2065,13 +2077,14 @@ void SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
 
 /// Expand the node to a libcall based on the result type.
 void SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
+                                           RTLIB::Libcall Call_F16,
                                            RTLIB::Libcall Call_F32,
                                            RTLIB::Libcall Call_F64,
                                            RTLIB::Libcall Call_F80,
                                            RTLIB::Libcall Call_F128,
                                            RTLIB::Libcall Call_PPCF128,
                                            SmallVectorImpl<SDValue> &Results) {
-  RTLIB::Libcall LC = RTLIB::getFPLibCall(Node->getSimpleValueType(0),
+  RTLIB::Libcall LC = RTLIB::getFPLibCall(Node->getSimpleValueType(0), Call_F16,
                                           Call_F32, Call_F64, Call_F80,
                                           Call_F128, Call_PPCF128);
   ExpandFPLibCall(Node, LC, Results);
@@ -2098,6 +2111,7 @@ SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
 /// Expand the node to a libcall based on first argument type (for instance
 /// lround and its variant).
 void SelectionDAGLegalize::ExpandArgFPLibCall(SDNode* Node,
+                                            RTLIB::Libcall Call_F16,
                                             RTLIB::Libcall Call_F32,
                                             RTLIB::Libcall Call_F64,
                                             RTLIB::Libcall Call_F80,
@@ -2105,7 +2119,7 @@ void SelectionDAGLegalize::ExpandArgFPLibCall(SDNode* Node,
                                             RTLIB::Libcall Call_PPCF128,
                                             SmallVectorImpl<SDValue> &Results) {
   EVT InVT = Node->getOperand(Node->isStrictFPOpcode() ? 1 : 0).getValueType();
-  RTLIB::Libcall LC = RTLIB::getFPLibCall(InVT.getSimpleVT(),
+  RTLIB::Libcall LC = RTLIB::getFPLibCall(InVT.getSimpleVT(), Call_F16,
                                           Call_F32, Call_F64, Call_F80,
                                           Call_F128, Call_PPCF128);
   ExpandFPLibCall(Node, LC, Results);
@@ -3924,36 +3938,36 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
   }
   case ISD::FMINNUM:
   case ISD::STRICT_FMINNUM:
-    ExpandFPLibCall(Node, RTLIB::FMIN_F32, RTLIB::FMIN_F64,
+    ExpandFPLibCall(Node, RTLIB::FMIN_F16, RTLIB::FMIN_F32, RTLIB::FMIN_F64,
                     RTLIB::FMIN_F80, RTLIB::FMIN_F128,
                     RTLIB::FMIN_PPCF128, Results);
     break;
   case ISD::FMAXNUM:
   case ISD::STRICT_FMAXNUM:
-    ExpandFPLibCall(Node, RTLIB::FMAX_F32, RTLIB::FMAX_F64,
+    ExpandFPLibCall(Node, RTLIB::FMAX_F16, RTLIB::FMAX_F32, RTLIB::FMAX_F64,
                     RTLIB::FMAX_F80, RTLIB::FMAX_F128,
                     RTLIB::FMAX_PPCF128, Results);
     break;
   case ISD::FSQRT:
   case ISD::STRICT_FSQRT:
-    ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
+    ExpandFPLibCall(Node, RTLIB::SQRT_F16, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
                     RTLIB::SQRT_F80, RTLIB::SQRT_F128,
                     RTLIB::SQRT_PPCF128, Results);
     break;
   case ISD::FCBRT:
-    ExpandFPLibCall(Node, RTLIB::CBRT_F32, RTLIB::CBRT_F64,
+    ExpandFPLibCall(Node, RTLIB::CBRT_F16, RTLIB::CBRT_F32, RTLIB::CBRT_F64,
                     RTLIB::CBRT_F80, RTLIB::CBRT_F128,
                     RTLIB::CBRT_PPCF128, Results);
     break;
   case ISD::FSIN:
   case ISD::STRICT_FSIN:
-    ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
+    ExpandFPLibCall(Node, RTLIB::SIN_F16, RTLIB::SIN_F32, RTLIB::SIN_F64,
                     RTLIB::SIN_F80, RTLIB::SIN_F128,
                     RTLIB::SIN_PPCF128, Results);
     break;
   case ISD::FCOS:
   case ISD::STRICT_FCOS:
-    ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
+    ExpandFPLibCall(Node, RTLIB::COS_F16, RTLIB::COS_F32, RTLIB::COS_F64,
                     RTLIB::COS_F80, RTLIB::COS_F128,
                     RTLIB::COS_PPCF128, Results);
     break;
@@ -3963,56 +3977,61 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
     break;
   case ISD::FLOG:
   case ISD::STRICT_FLOG:
-    ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64, RTLIB::LOG_F80,
+    ExpandFPLibCall(Node, RTLIB::LOG_F16, RTLIB::LOG_F32,
+                    RTLIB::LOG_F64, RTLIB::LOG_F80,
                     RTLIB::LOG_F128, RTLIB::LOG_PPCF128, Results);
     break;
   case ISD::FLOG2:
   case ISD::STRICT_FLOG2:
-    ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64, RTLIB::LOG2_F80,
+    ExpandFPLibCall(Node, RTLIB::LOG2_F16, RTLIB::LOG2_F32,
+                    RTLIB::LOG2_F64, RTLIB::LOG2_F80,
                     RTLIB::LOG2_F128, RTLIB::LOG2_PPCF128, Results);
     break;
   case ISD::FLOG10:
   case ISD::STRICT_FLOG10:
-    ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64, RTLIB::LOG10_F80,
+    ExpandFPLibCall(Node, RTLIB::LOG10_F16, RTLIB::LOG10_F32,
+                    RTLIB::LOG10_F64, RTLIB::LOG10_F80,
                     RTLIB::LOG10_F128, RTLIB::LOG10_PPCF128, Results);
     break;
   case ISD::FEXP:
   case ISD::STRICT_FEXP:
-    ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64, RTLIB::EXP_F80,
+    ExpandFPLibCall(Node, RTLIB::EXP_F16, RTLIB::EXP_F32,
+                    RTLIB::EXP_F64, RTLIB::EXP_F80,
                     RTLIB::EXP_F128, RTLIB::EXP_PPCF128, Results);
     break;
   case ISD::FEXP2:
   case ISD::STRICT_FEXP2:
-    ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64, RTLIB::EXP2_F80,
+    ExpandFPLibCall(Node, RTLIB::EXP2_F16, RTLIB::EXP2_F32,
+                    RTLIB::EXP2_F64, RTLIB::EXP2_F80,
                     RTLIB::EXP2_F128, RTLIB::EXP2_PPCF128, Results);
     break;
   case ISD::FTRUNC:
   case ISD::STRICT_FTRUNC:
-    ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
+    ExpandFPLibCall(Node, RTLIB::TRUNC_F16, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
                     RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
                     RTLIB::TRUNC_PPCF128, Results);
     break;
   case ISD::FFLOOR:
   case ISD::STRICT_FFLOOR:
-    ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
+    ExpandFPLibCall(Node, RTLIB::FLOOR_F16, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
                     RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
                     RTLIB::FLOOR_PPCF128, Results);
     break;
   case ISD::FCEIL:
   case ISD::STRICT_FCEIL:
-    ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
+    ExpandFPLibCall(Node, RTLIB::CEIL_F16, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
                     RTLIB::CEIL_F80, RTLIB::CEIL_F128,
                     RTLIB::CEIL_PPCF128, Results);
     break;
   case ISD::FRINT:
   case ISD::STRICT_FRINT:
-    ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
+    ExpandFPLibCall(Node, RTLIB::RINT_F16, RTLIB::RINT_F32, RTLIB::RINT_F64,
                     RTLIB::RINT_F80, RTLIB::RINT_F128,
                     RTLIB::RINT_PPCF128, Results);
     break;
   case ISD::FNEARBYINT:
   case ISD::STRICT_FNEARBYINT:
-    ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
+    ExpandFPLibCall(Node, RTLIB::NEARBYINT_F16, RTLIB::NEARBYINT_F32,
                     RTLIB::NEARBYINT_F64,
                     RTLIB::NEARBYINT_F80,
                     RTLIB::NEARBYINT_F128,
@@ -4020,7 +4039,7 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
     break;
   case ISD::FROUND:
   case ISD::STRICT_FROUND:
-    ExpandFPLibCall(Node, RTLIB::ROUND_F32,
+    ExpandFPLibCall(Node, RTLIB::ROUND_F16, RTLIB::ROUND_F32,
                     RTLIB::ROUND_F64,
                     RTLIB::ROUND_F80,
                     RTLIB::ROUND_F128,
@@ -4028,7 +4047,7 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
     break;
   case ISD::FROUNDEVEN:
   case ISD::STRICT_FROUNDEVEN:
-    ExpandFPLibCall(Node, RTLIB::ROUNDEVEN_F32,
+    ExpandFPLibCall(Node, RTLIB::ROUNDEVEN_F16, RTLIB::ROUNDEVEN_F32,
                     RTLIB::ROUNDEVEN_F64,
                     RTLIB::ROUNDEVEN_F80,
                     RTLIB::ROUNDEVEN_F128,
@@ -4064,64 +4083,65 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
   }
   case ISD::FPOW:
   case ISD::STRICT_FPOW:
-    ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
+    ExpandFPLibCall(Node, RTLIB::POW_F16, RTLIB::POW_F32,
+                    RTLIB::POW_F64, RTLIB::POW_F80,
                     RTLIB::POW_F128, RTLIB::POW_PPCF128, Results);
     break;
   case ISD::LROUND:
   case ISD::STRICT_LROUND:
-    ExpandArgFPLibCall(Node, RTLIB::LROUND_F32,
+    ExpandArgFPLibCall(Node, RTLIB::LROUND_F16, RTLIB::LROUND_F32,
                        RTLIB::LROUND_F64, RTLIB::LROUND_F80,
                        RTLIB::LROUND_F128,
                        RTLIB::LROUND_PPCF128, Results);
     break;
   case ISD::LLROUND:
   case ISD::STRICT_LLROUND:
-    ExpandArgFPLibCall(Node, RTLIB::LLROUND_F32,
+    ExpandArgFPLibCall(Node, RTLIB::LLROUND_F16, RTLIB::LLROUND_F32,
                        RTLIB::LLROUND_F64, RTLIB::LLROUND_F80,
                        RTLIB::LLROUND_F128,
                        RTLIB::LLROUND_PPCF128, Results);
     break;
   case ISD::LRINT:
   case ISD::STRICT_LRINT:
-    ExpandArgFPLibCall(Node, RTLIB::LRINT_F32,
+    ExpandArgFPLibCall(Node, RTLIB::LRINT_F16, RTLIB::LRINT_F32,
                        RTLIB::LRINT_F64, RTLIB::LRINT_F80,
                        RTLIB::LRINT_F128,
                        RTLIB::LRINT_PPCF128, Results);
     break;
   case ISD::LLRINT:
   case ISD::STRICT_LLRINT:
-    ExpandArgFPLibCall(Node, RTLIB::LLRINT_F32,
+    ExpandArgFPLibCall(Node, RTLIB::LLRINT_F16, RTLIB::LLRINT_F32,
                        RTLIB::LLRINT_F64, RTLIB::LLRINT_F80,
                        RTLIB::LLRINT_F128,
                        RTLIB::LLRINT_PPCF128, Results);
     break;
   case ISD::FDIV:
   case ISD::STRICT_FDIV:
-    ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
+    ExpandFPLibCall(Node, RTLIB::DIV_F16, RTLIB::DIV_F32, RTLIB::DIV_F64,
                     RTLIB::DIV_F80, RTLIB::DIV_F128,
                     RTLIB::DIV_PPCF128, Results);
     break;
   case ISD::FREM:
   case ISD::STRICT_FREM:
-    ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
+    ExpandFPLibCall(Node, RTLIB::REM_F16, RTLIB::REM_F32, RTLIB::REM_F64,
                     RTLIB::REM_F80, RTLIB::REM_F128,
                     RTLIB::REM_PPCF128, Results);
     break;
   case ISD::FMA:
   case ISD::STRICT_FMA:
-    ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
+    ExpandFPLibCall(Node, RTLIB::FMA_F16, RTLIB::FMA_F32, RTLIB::FMA_F64,
                     RTLIB::FMA_F80, RTLIB::FMA_F128,
                     RTLIB::FMA_PPCF128, Results);
     break;
   case ISD::FADD:
   case ISD::STRICT_FADD:
-    ExpandFPLibCall(Node, RTLIB::ADD_F32, RTLIB::ADD_F64,
+    ExpandFPLibCall(Node, RTLIB::ADD_F16, RTLIB::ADD_F32, RTLIB::ADD_F64,
                     RTLIB::ADD_F80, RTLIB::ADD_F128,
                     RTLIB::ADD_PPCF128, Results);
     break;
   case ISD::FMUL:
   case ISD::STRICT_FMUL:
-    ExpandFPLibCall(Node, RTLIB::MUL_F32, RTLIB::MUL_F64,
+    ExpandFPLibCall(Node, RTLIB::MUL_F16, RTLIB::MUL_F32, RTLIB::MUL_F64,
                     RTLIB::MUL_F80, RTLIB::MUL_F128,
                     RTLIB::MUL_PPCF128, Results);
     break;
@@ -4283,7 +4303,7 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
   }
   case ISD::FSUB:
   case ISD::STRICT_FSUB:
-    ExpandFPLibCall(Node, RTLIB::SUB_F32, RTLIB::SUB_F64,
+    ExpandFPLibCall(Node, RTLIB::SUB_F16, RTLIB::SUB_F32, RTLIB::SUB_F64,
                     RTLIB::SUB_F80, RTLIB::SUB_F128,
                     RTLIB::SUB_PPCF128, Results);
     break;
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index 3553f9ec16c2..4376f0144b9f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -30,12 +30,14 @@ using namespace llvm;
 /// FIXME: This is a local version of RTLIB::getFPLibCall that should be
 ///        refactored away (see RTLIB::getPOWI for an example).
 static RTLIB::Libcall GetFPLibCall(EVT VT,
+                                   RTLIB::Libcall Call_F16,
                                    RTLIB::Libcall Call_F32,
                                    RTLIB::Libcall Call_F64,
                                    RTLIB::Libcall Call_F80,
                                    RTLIB::Libcall Call_F128,
                                    RTLIB::Libcall Call_PPCF128) {
   return
+    VT == MVT::f16 ? Call_F16 :
     VT == MVT::f32 ? Call_F32 :
     VT == MVT::f64 ? Call_F64 :
     VT == MVT::f80 ? Call_F80 :
@@ -266,6 +268,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FABS(SDNode *N) {
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_FMINNUM(SDNode *N) {
   return SoftenFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
+                                               RTLIB::FMIN_F16,
                                                RTLIB::FMIN_F32,
                                                RTLIB::FMIN_F64,
                                                RTLIB::FMIN_F80,
@@ -275,6 +278,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FMINNUM(SDNode *N) {
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_FMAXNUM(SDNode *N) {
   return SoftenFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
+                                               RTLIB::FMAX_F16,
                                                RTLIB::FMAX_F32,
                                                RTLIB::FMAX_F64,
                                                RTLIB::FMAX_F80,
@@ -284,6 +288,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FMAXNUM(SDNode *N) {
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_FADD(SDNode *N) {
   return SoftenFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
+                                               RTLIB::ADD_F16,
                                                RTLIB::ADD_F32,
                                                RTLIB::ADD_F64,
                                                RTLIB::ADD_F80,
@@ -293,6 +298,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FADD(SDNode *N) {
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_FCBRT(SDNode *N) {
   return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+                                           RTLIB::CBRT_F16,
                                            RTLIB::CBRT_F32,
                                            RTLIB::CBRT_F64,
                                            RTLIB::CBRT_F80,
@@ -302,6 +308,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FCBRT(SDNode *N) {
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_FCEIL(SDNode *N) {
   return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+                                              RTLIB::CEIL_F16,
                                               RTLIB::CEIL_F32,
                                               RTLIB::CEIL_F64,
                                               RTLIB::CEIL_F80,
@@ -359,6 +366,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN(SDNode *N) {
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_FCOS(SDNode *N) {
   return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+                                              RTLIB::COS_F16,
                                               RTLIB::COS_F32,
                                               RTLIB::COS_F64,
                                               RTLIB::COS_F80,
@@ -368,6 +376,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FCOS(SDNode *N) {
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_FDIV(SDNode *N) {
   return SoftenFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
+                                               RTLIB::DIV_F16,
                                                RTLIB::DIV_F32,
                                                RTLIB::DIV_F64,
                                                RTLIB::DIV_F80,
@@ -377,6 +386,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FDIV(SDNode *N) {
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_FEXP(SDNode *N) {
   return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+                                              RTLIB::EXP_F16,
                                               RTLIB::EXP_F32,
                                               RTLIB::EXP_F64,
                                               RTLIB::EXP_F80,
@@ -386,6 +396,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FEXP(SDNode *N) {
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_FEXP2(SDNode *N) {
   return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+                                              RTLIB::EXP2_F16,
                                               RTLIB::EXP2_F32,
                                               RTLIB::EXP2_F64,
                                               RTLIB::EXP2_F80,
@@ -395,6 +406,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FEXP2(SDNode *N) {
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_FFLOOR(SDNode *N) {
   return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+                                              RTLIB::FLOOR_F16,
                                               RTLIB::FLOOR_F32,
                                               RTLIB::FLOOR_F64,
                                               RTLIB::FLOOR_F80,
@@ -404,6 +416,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FFLOOR(SDNode *N) {
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG(SDNode *N) {
   return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+                                              RTLIB::LOG_F16,
                                               RTLIB::LOG_F32,
                                               RTLIB::LOG_F64,
                                               RTLIB::LOG_F80,
@@ -413,6 +426,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG(SDNode *N) {
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG2(SDNode *N) {
   return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+                                              RTLIB::LOG2_F16,
                                               RTLIB::LOG2_F32,
                                               RTLIB::LOG2_F64,
                                               RTLIB::LOG2_F80,
@@ -422,6 +436,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG2(SDNode *N) {
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG10(SDNode *N) {
   return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+                                              RTLIB::LOG10_F16,
                                               RTLIB::LOG10_F32,
                                               RTLIB::LOG10_F64,
                                               RTLIB::LOG10_F80,
@@ -444,6 +459,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FMA(SDNode *N) {
   CallOptions.setTypeListBeforeSoften(OpsVT, N->getValueType(0), true);
   std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG,
                                                     GetFPLibCall(N->getValueType(0),
+                                                                 RTLIB::FMA_F16,
                                                                  RTLIB::FMA_F32,
                                                                  RTLIB::FMA_F64,
                                                                  RTLIB::FMA_F80,
@@ -457,6 +473,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FMA(SDNode *N) {
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_FMUL(SDNode *N) {
   return SoftenFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
+                                               RTLIB::MUL_F16,
                                                RTLIB::MUL_F32,
                                                RTLIB::MUL_F64,
                                                RTLIB::MUL_F80,
@@ -466,6 +483,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FMUL(SDNode *N) {
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_FNEARBYINT(SDNode *N) {
   return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+                                              RTLIB::NEARBYINT_F16,
                                               RTLIB::NEARBYINT_F32,
                                               RTLIB::NEARBYINT_F64,
                                               RTLIB::NEARBYINT_F80,
@@ -563,6 +581,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FP_ROUND(SDNode *N) {
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_FPOW(SDNode *N) {
   return SoftenFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
+                                               RTLIB::POW_F16,
                                                RTLIB::POW_F32,
                                                RTLIB::POW_F64,
                                                RTLIB::POW_F80,
@@ -611,6 +630,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FPOWI(SDNode *N) {
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_FREM(SDNode *N) {
   return SoftenFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
+                                               RTLIB::REM_F16,
                                                RTLIB::REM_F32,
                                                RTLIB::REM_F64,
                                                RTLIB::REM_F80,
@@ -620,6 +640,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FREM(SDNode *N) {
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_FRINT(SDNode *N) {
   return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+                                              RTLIB::RINT_F16,
                                               RTLIB::RINT_F32,
                                               RTLIB::RINT_F64,
                                               RTLIB::RINT_F80,
@@ -629,6 +650,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FRINT(SDNode *N) {
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_FROUND(SDNode *N) {
   return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+                                              RTLIB::ROUND_F16,
                                               RTLIB::ROUND_F32,
                                               RTLIB::ROUND_F64,
                                               RTLIB::ROUND_F80,
@@ -638,6 +660,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FROUND(SDNode *N) {
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_FROUNDEVEN(SDNode *N) {
   return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+                                              RTLIB::ROUNDEVEN_F16,
                                               RTLIB::ROUNDEVEN_F32,
                                               RTLIB::ROUNDEVEN_F64,
                                               RTLIB::ROUNDEVEN_F80,
@@ -647,6 +670,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FROUNDEVEN(SDNode *N) {
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_FSIN(SDNode *N) {
   return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+                                              RTLIB::SIN_F16,
                                               RTLIB::SIN_F32,
                                               RTLIB::SIN_F64,
                                               RTLIB::SIN_F80,
@@ -656,6 +680,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FSIN(SDNode *N) {
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_FSQRT(SDNode *N) {
   return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+                                              RTLIB::SQRT_F16,
                                               RTLIB::SQRT_F32,
                                               RTLIB::SQRT_F64,
                                               RTLIB::SQRT_F80,
@@ -665,6 +690,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FSQRT(SDNode *N) {
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_FSUB(SDNode *N) {
   return SoftenFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
+                                               RTLIB::SUB_F16,
                                                RTLIB::SUB_F32,
                                                RTLIB::SUB_F64,
                                                RTLIB::SUB_F80,
@@ -674,6 +700,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FSUB(SDNode *N) {
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_FTRUNC(SDNode *N) {
   return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+                                              RTLIB::TRUNC_F16,
                                               RTLIB::TRUNC_F32,
                                               RTLIB::TRUNC_F64,
                                               RTLIB::TRUNC_F80,
@@ -823,6 +850,7 @@ bool DAGTypeLegalizer::SoftenFloatOperand(SDNode *N, unsigned OpNo) {
   case ISD::FP_TO_FP16:  // Same as FP_ROUND for softening purposes
   case ISD::STRICT_FP_ROUND:
   case ISD::FP_ROUND:    Res = SoftenFloatOp_FP_ROUND(N); break;
+  case ISD::FP_EXTEND:   Res = SoftenFloatOp_FP_EXTEND(N); break;
   case ISD::STRICT_FP_TO_SINT:
   case ISD::STRICT_FP_TO_UINT:
   case ISD::FP_TO_SINT:
@@ -897,6 +925,35 @@ SDValue DAGTypeLegalizer::SoftenFloatOp_FP_ROUND(SDNode *N) {
   return Tmp.first;
 }
 
+SDValue DAGTypeLegalizer::SoftenFloatOp_FP_EXTEND(SDNode *N) {
+  // We actually deal with the partially-softened FP_TO_FP16 node too, which
+  // returns an i16 so doesn't meet the constraints necessary for FP_ROUND.
+  assert(N->getOpcode() == ISD::FP_EXTEND || N->getOpcode()==ISD::STRICT_FP_EXTEND);
+
+  bool IsStrict = N->isStrictFPOpcode();
+  SDValue Op = N->getOperand(IsStrict ? 1 : 0);
+  EVT SVT = Op.getValueType();
+  EVT FloatRVT = N->getValueType(0);
+  //EVT FloatRVT = N->getOpcode() == ISD::FP_TO_FP16 ? MVT::f16 : RVT;
+
+  RTLIB::Libcall LC = RTLIB::getFPEXT(SVT, FloatRVT);
+  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND libcall");
+
+  SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
+  Op = GetSoftenedFloat(Op);
+  TargetLowering::MakeLibCallOptions CallOptions;
+  CallOptions.setTypeListBeforeSoften(SVT, FloatRVT, true);
+  std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, FloatRVT, Op,
+                                                    CallOptions, SDLoc(N),
+                                                    Chain);
+  if (IsStrict) {
+    ReplaceValueWith(SDValue(N, 1), Tmp.second);
+    ReplaceValueWith(SDValue(N, 0), Tmp.first);
+    return SDValue();
+  }
+  return Tmp.first;
+}
+
 SDValue DAGTypeLegalizer::SoftenFloatOp_BR_CC(SDNode *N) {
   SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
   ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
@@ -1117,6 +1174,7 @@ SDValue DAGTypeLegalizer::SoftenFloatOp_Unary(SDNode *N, RTLIB::Libcall LC) {
 SDValue DAGTypeLegalizer::SoftenFloatOp_LROUND(SDNode *N) {
   EVT OpVT = N->getOperand(N->isStrictFPOpcode() ? 1 : 0).getValueType();
   return SoftenFloatOp_Unary(N, GetFPLibCall(OpVT,
+                                             RTLIB::LROUND_F16,
                                              RTLIB::LROUND_F32,
                                              RTLIB::LROUND_F64,
                                              RTLIB::LROUND_F80,
@@ -1127,6 +1185,7 @@ SDValue DAGTypeLegalizer::SoftenFloatOp_LROUND(SDNode *N) {
 SDValue DAGTypeLegalizer::SoftenFloatOp_LLROUND(SDNode *N) {
   EVT OpVT = N->getOperand(N->isStrictFPOpcode() ? 1 : 0).getValueType();
   return SoftenFloatOp_Unary(N, GetFPLibCall(OpVT,
+                                             RTLIB::LLROUND_F16,
                                              RTLIB::LLROUND_F32,
                                              RTLIB::LLROUND_F64,
                                              RTLIB::LLROUND_F80,
@@ -1137,6 +1196,7 @@ SDValue DAGTypeLegalizer::SoftenFloatOp_LLROUND(SDNode *N) {
 SDValue DAGTypeLegalizer::SoftenFloatOp_LRINT(SDNode *N) {
   EVT OpVT = N->getOperand(N->isStrictFPOpcode() ? 1 : 0).getValueType();
   return SoftenFloatOp_Unary(N, GetFPLibCall(OpVT,
+                                             RTLIB::LRINT_F16,
                                              RTLIB::LRINT_F32,
                                              RTLIB::LRINT_F64,
                                              RTLIB::LRINT_F80,
@@ -1147,6 +1207,7 @@ SDValue DAGTypeLegalizer::SoftenFloatOp_LRINT(SDNode *N) {
 SDValue DAGTypeLegalizer::SoftenFloatOp_LLRINT(SDNode *N) {
   EVT OpVT = N->getOperand(N->isStrictFPOpcode() ? 1 : 0).getValueType();
   return SoftenFloatOp_Unary(N, GetFPLibCall(OpVT,
+                                             RTLIB::LLRINT_F16,
                                              RTLIB::LLRINT_F32,
                                              RTLIB::LLRINT_F64,
                                              RTLIB::LLRINT_F80,
@@ -1321,7 +1382,7 @@ void DAGTypeLegalizer::ExpandFloatRes_FABS(SDNode *N, SDValue &Lo,
 
 void DAGTypeLegalizer::ExpandFloatRes_FMINNUM(SDNode *N, SDValue &Lo,
                                               SDValue &Hi) {
-  ExpandFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
+  ExpandFloatRes_Binary(N, GetFPLibCall(N->getValueType(0), RTLIB::FMIN_F16,
                                        RTLIB::FMIN_F32, RTLIB::FMIN_F64,
                                        RTLIB::FMIN_F80, RTLIB::FMIN_F128,
                                        RTLIB::FMIN_PPCF128), Lo, Hi);
@@ -1329,7 +1390,7 @@ void DAGTypeLegalizer::ExpandFloatRes_FMINNUM(SDNode *N, SDValue &Lo,
 
 void DAGTypeLegalizer::ExpandFloatRes_FMAXNUM(SDNode *N, SDValue &Lo,
                                               SDValue &Hi) {
-  ExpandFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
+  ExpandFloatRes_Binary(N, GetFPLibCall(N->getValueType(0), RTLIB::FMAX_F16,
                                         RTLIB::FMAX_F32, RTLIB::FMAX_F64,
                                         RTLIB::FMAX_F80, RTLIB::FMAX_F128,
                                         RTLIB::FMAX_PPCF128), Lo, Hi);
@@ -1337,7 +1398,7 @@ void DAGTypeLegalizer::ExpandFloatRes_FMAXNUM(SDNode *N, SDValue &Lo,
 
 void DAGTypeLegalizer::ExpandFloatRes_FADD(SDNode *N, SDValue &Lo,
                                            SDValue &Hi) {
-  ExpandFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
+  ExpandFloatRes_Binary(N, GetFPLibCall(N->getValueType(0), RTLIB::ADD_F16,
                                         RTLIB::ADD_F32, RTLIB::ADD_F64,
                                         RTLIB::ADD_F80, RTLIB::ADD_F128,
                                         RTLIB::ADD_PPCF128), Lo, Hi);
@@ -1345,7 +1406,8 @@ void DAGTypeLegalizer::ExpandFloatRes_FADD(SDNode *N, SDValue &Lo,
 
 void DAGTypeLegalizer::ExpandFloatRes_FCBRT(SDNode *N, SDValue &Lo,
                                             SDValue &Hi) {
-  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0), RTLIB::CBRT_F32,
+  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+                                       RTLIB::CBRT_F16, RTLIB::CBRT_F32,
                                        RTLIB::CBRT_F64, RTLIB::CBRT_F80,
                                        RTLIB::CBRT_F128,
                                        RTLIB::CBRT_PPCF128), Lo, Hi);
@@ -1353,7 +1415,7 @@ void DAGTypeLegalizer::ExpandFloatRes_FCBRT(SDNode *N, SDValue &Lo,
 
 void DAGTypeLegalizer::ExpandFloatRes_FCEIL(SDNode *N,
                                             SDValue &Lo, SDValue &Hi) {
-  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0), RTLIB::CEIL_F16,
                                        RTLIB::CEIL_F32, RTLIB::CEIL_F64,
                                        RTLIB::CEIL_F80, RTLIB::CEIL_F128,
                                        RTLIB::CEIL_PPCF128), Lo, Hi);
@@ -1361,7 +1423,7 @@ void DAGTypeLegalizer::ExpandFloatRes_FCEIL(SDNode *N,
 
 void DAGTypeLegalizer::ExpandFloatRes_FCOPYSIGN(SDNode *N,
                                                 SDValue &Lo, SDValue &Hi) {
-  ExpandFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
+  ExpandFloatRes_Binary(N, GetFPLibCall(N->getValueType(0), RTLIB::COPYSIGN_F16,
                                         RTLIB::COPYSIGN_F32,
                                         RTLIB::COPYSIGN_F64,
                                         RTLIB::COPYSIGN_F80,
@@ -1371,7 +1433,7 @@ void DAGTypeLegalizer::ExpandFloatRes_FCOPYSIGN(SDNode *N,
 
 void DAGTypeLegalizer::ExpandFloatRes_FCOS(SDNode *N,
                                            SDValue &Lo, SDValue &Hi) {
-  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0), RTLIB::COS_F16,
                                        RTLIB::COS_F32, RTLIB::COS_F64,
                                        RTLIB::COS_F80, RTLIB::COS_F128,
                                        RTLIB::COS_PPCF128), Lo, Hi);
@@ -1379,7 +1441,7 @@ void DAGTypeLegalizer::ExpandFloatRes_FCOS(SDNode *N,
 
 void DAGTypeLegalizer::ExpandFloatRes_FDIV(SDNode *N, SDValue &Lo,
                                            SDValue &Hi) {
-  ExpandFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
+  ExpandFloatRes_Binary(N, GetFPLibCall(N->getValueType(0), RTLIB::DIV_F16,
                                         RTLIB::DIV_F32,
                                         RTLIB::DIV_F64,
                                         RTLIB::DIV_F80,
@@ -1389,7 +1451,7 @@ void DAGTypeLegalizer::ExpandFloatRes_FDIV(SDNode *N, SDValue &Lo,
 
 void DAGTypeLegalizer::ExpandFloatRes_FEXP(SDNode *N,
                                            SDValue &Lo, SDValue &Hi) {
-  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0), RTLIB::EXP_F16,
                                        RTLIB::EXP_F32, RTLIB::EXP_F64,
                                        RTLIB::EXP_F80, RTLIB::EXP_F128,
                                        RTLIB::EXP_PPCF128), Lo, Hi);
@@ -1397,7 +1459,7 @@ void DAGTypeLegalizer::ExpandFloatRes_FEXP(SDNode *N,
 
 void DAGTypeLegalizer::ExpandFloatRes_FEXP2(SDNode *N,
                                             SDValue &Lo, SDValue &Hi) {
-  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0), RTLIB::EXP2_F16,
                                        RTLIB::EXP2_F32, RTLIB::EXP2_F64,
                                        RTLIB::EXP2_F80, RTLIB::EXP2_F128,
                                        RTLIB::EXP2_PPCF128), Lo, Hi);
@@ -1405,7 +1467,7 @@ void DAGTypeLegalizer::ExpandFloatRes_FEXP2(SDNode *N,
 
 void DAGTypeLegalizer::ExpandFloatRes_FFLOOR(SDNode *N,
                                              SDValue &Lo, SDValue &Hi) {
-  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0), RTLIB::FLOOR_F16,
                                        RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
                                        RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
                                        RTLIB::FLOOR_PPCF128), Lo, Hi);
@@ -1413,7 +1475,7 @@ void DAGTypeLegalizer::ExpandFloatRes_FFLOOR(SDNode *N,
 
 void DAGTypeLegalizer::ExpandFloatRes_FLOG(SDNode *N,
                                            SDValue &Lo, SDValue &Hi) {
-  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0), RTLIB::LOG_F16,
                                        RTLIB::LOG_F32, RTLIB::LOG_F64,
                                        RTLIB::LOG_F80, RTLIB::LOG_F128,
                                        RTLIB::LOG_PPCF128), Lo, Hi);
@@ -1421,7 +1483,7 @@ void DAGTypeLegalizer::ExpandFloatRes_FLOG(SDNode *N,
 
 void DAGTypeLegalizer::ExpandFloatRes_FLOG2(SDNode *N,
                                             SDValue &Lo, SDValue &Hi) {
-  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0), RTLIB::LOG2_F16,
                                        RTLIB::LOG2_F32, RTLIB::LOG2_F64,
                                        RTLIB::LOG2_F80, RTLIB::LOG2_F128,
                                        RTLIB::LOG2_PPCF128), Lo, Hi);
@@ -1429,7 +1491,7 @@ void DAGTypeLegalizer::ExpandFloatRes_FLOG2(SDNode *N,
 
 void DAGTypeLegalizer::ExpandFloatRes_FLOG10(SDNode *N,
                                              SDValue &Lo, SDValue &Hi) {
-  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0), RTLIB::LOG10_F16,
                                        RTLIB::LOG10_F32, RTLIB::LOG10_F64,
                                        RTLIB::LOG10_F80, RTLIB::LOG10_F128,
                                        RTLIB::LOG10_PPCF128), Lo, Hi);
@@ -1444,6 +1506,7 @@ void DAGTypeLegalizer::ExpandFloatRes_FMA(SDNode *N, SDValue &Lo,
   SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
   TargetLowering::MakeLibCallOptions CallOptions;
   std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
+                                                   RTLIB::FMA_F16,
                                                    RTLIB::FMA_F32,
                                                    RTLIB::FMA_F64,
                                                    RTLIB::FMA_F80,
@@ -1459,6 +1522,7 @@ void DAGTypeLegalizer::ExpandFloatRes_FMA(SDNode *N, SDValue &Lo,
 void DAGTypeLegalizer::ExpandFloatRes_FMUL(SDNode *N, SDValue &Lo,
                                            SDValue &Hi) {
   ExpandFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
+                                                   RTLIB::MUL_F16,
                                                    RTLIB::MUL_F32,
                                                    RTLIB::MUL_F64,
                                                    RTLIB::MUL_F80,
@@ -1469,6 +1533,7 @@ void DAGTypeLegalizer::ExpandFloatRes_FMUL(SDNode *N, SDValue &Lo,
 void DAGTypeLegalizer::ExpandFloatRes_FNEARBYINT(SDNode *N,
                                                  SDValue &Lo, SDValue &Hi) {
   ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+                                       RTLIB::NEARBYINT_F16,
                                        RTLIB::NEARBYINT_F32,
                                        RTLIB::NEARBYINT_F64,
                                        RTLIB::NEARBYINT_F80,
@@ -1515,7 +1580,7 @@ void DAGTypeLegalizer::ExpandFloatRes_FP_EXTEND(SDNode *N, SDValue &Lo,
 
 void DAGTypeLegalizer::ExpandFloatRes_FPOW(SDNode *N,
                                            SDValue &Lo, SDValue &Hi) {
-  ExpandFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
+  ExpandFloatRes_Binary(N, GetFPLibCall(N->getValueType(0), RTLIB::POW_F16,
                                         RTLIB::POW_F32, RTLIB::POW_F64,
                                         RTLIB::POW_F80, RTLIB::POW_F128,
                                         RTLIB::POW_PPCF128), Lo, Hi);
@@ -1539,7 +1604,7 @@ void DAGTypeLegalizer::ExpandFloatRes_FREEZE(SDNode *N,
 
 void DAGTypeLegalizer::ExpandFloatRes_FREM(SDNode *N,
                                            SDValue &Lo, SDValue &Hi) {
-  ExpandFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
+  ExpandFloatRes_Binary(N, GetFPLibCall(N->getValueType(0), RTLIB::REM_F16,
                                         RTLIB::REM_F32, RTLIB::REM_F64,
                                         RTLIB::REM_F80, RTLIB::REM_F128,
                                         RTLIB::REM_PPCF128), Lo, Hi);
@@ -1547,7 +1612,7 @@ void DAGTypeLegalizer::ExpandFloatRes_FREM(SDNode *N,
 
 void DAGTypeLegalizer::ExpandFloatRes_FRINT(SDNode *N,
                                             SDValue &Lo, SDValue &Hi) {
-  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0), RTLIB::RINT_F16,
                                        RTLIB::RINT_F32, RTLIB::RINT_F64,
                                        RTLIB::RINT_F80, RTLIB::RINT_F128,
                                        RTLIB::RINT_PPCF128), Lo, Hi);
@@ -1555,7 +1620,7 @@ void DAGTypeLegalizer::ExpandFloatRes_FRINT(SDNode *N,
 
 void DAGTypeLegalizer::ExpandFloatRes_FROUND(SDNode *N,
                                              SDValue &Lo, SDValue &Hi) {
-  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0), RTLIB::ROUND_F16,
                                        RTLIB::ROUND_F32,
                                        RTLIB::ROUND_F64,
                                        RTLIB::ROUND_F80,
@@ -1565,7 +1630,7 @@ void DAGTypeLegalizer::ExpandFloatRes_FROUND(SDNode *N,
 
 void DAGTypeLegalizer::ExpandFloatRes_FROUNDEVEN(SDNode *N,
                                              SDValue &Lo, SDValue &Hi) {
-  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0), RTLIB::ROUNDEVEN_F16,
                                        RTLIB::ROUNDEVEN_F32,
                                        RTLIB::ROUNDEVEN_F64,
                                        RTLIB::ROUNDEVEN_F80,
@@ -1575,7 +1640,7 @@ void DAGTypeLegalizer::ExpandFloatRes_FROUNDEVEN(SDNode *N,
 
 void DAGTypeLegalizer::ExpandFloatRes_FSIN(SDNode *N,
                                            SDValue &Lo, SDValue &Hi) {
-  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0), RTLIB::SIN_F16,
                                        RTLIB::SIN_F32, RTLIB::SIN_F64,
                                        RTLIB::SIN_F80, RTLIB::SIN_F128,
                                        RTLIB::SIN_PPCF128), Lo, Hi);
@@ -1583,7 +1648,7 @@ void DAGTypeLegalizer::ExpandFloatRes_FSIN(SDNode *N,
 
 void DAGTypeLegalizer::ExpandFloatRes_FSQRT(SDNode *N,
                                             SDValue &Lo, SDValue &Hi) {
-  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0), RTLIB::SQRT_F16,
                                        RTLIB::SQRT_F32, RTLIB::SQRT_F64,
                                        RTLIB::SQRT_F80, RTLIB::SQRT_F128,
                                        RTLIB::SQRT_PPCF128), Lo, Hi);
@@ -1591,7 +1656,7 @@ void DAGTypeLegalizer::ExpandFloatRes_FSQRT(SDNode *N,
 
 void DAGTypeLegalizer::ExpandFloatRes_FSUB(SDNode *N, SDValue &Lo,
                                            SDValue &Hi) {
-  ExpandFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
+  ExpandFloatRes_Binary(N, GetFPLibCall(N->getValueType(0), RTLIB::SUB_F16,
                                         RTLIB::SUB_F32,
                                         RTLIB::SUB_F64,
                                         RTLIB::SUB_F80,
@@ -1601,7 +1666,7 @@ void DAGTypeLegalizer::ExpandFloatRes_FSUB(SDNode *N, SDValue &Lo,
 
 void DAGTypeLegalizer::ExpandFloatRes_FTRUNC(SDNode *N,
                                              SDValue &Lo, SDValue &Hi) {
-  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
+  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0), RTLIB::TRUNC_F16,
                                        RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
                                        RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
                                        RTLIB::TRUNC_PPCF128), Lo, Hi);
@@ -1997,6 +2062,7 @@ SDValue DAGTypeLegalizer::ExpandFloatOp_LROUND(SDNode *N) {
   EVT RetVT = N->getOperand(0).getValueType();
   TargetLowering::MakeLibCallOptions CallOptions;
   return TLI.makeLibCall(DAG, GetFPLibCall(RetVT,
+                                           RTLIB::LROUND_F16,
                                            RTLIB::LROUND_F32,
                                            RTLIB::LROUND_F64,
                                            RTLIB::LROUND_F80,
@@ -2010,6 +2076,7 @@ SDValue DAGTypeLegalizer::ExpandFloatOp_LLROUND(SDNode *N) {
   EVT RetVT = N->getOperand(0).getValueType();
   TargetLowering::MakeLibCallOptions CallOptions;
   return TLI.makeLibCall(DAG, GetFPLibCall(RetVT,
+                                           RTLIB::LLROUND_F16,
                                            RTLIB::LLROUND_F32,
                                            RTLIB::LLROUND_F64,
                                            RTLIB::LLROUND_F80,
@@ -2023,6 +2090,7 @@ SDValue DAGTypeLegalizer::ExpandFloatOp_LRINT(SDNode *N) {
   EVT RetVT = N->getOperand(0).getValueType();
   TargetLowering::MakeLibCallOptions CallOptions;
   return TLI.makeLibCall(DAG, GetFPLibCall(RetVT,
+                                           RTLIB::LRINT_F16,
                                            RTLIB::LRINT_F32,
                                            RTLIB::LRINT_F64,
                                            RTLIB::LRINT_F80,
@@ -2036,6 +2104,7 @@ SDValue DAGTypeLegalizer::ExpandFloatOp_LLRINT(SDNode *N) {
   EVT RetVT = N->getOperand(0).getValueType();
   TargetLowering::MakeLibCallOptions CallOptions;
   return TLI.makeLibCall(DAG, GetFPLibCall(RetVT,
+                                           RTLIB::LLRINT_F16,
                                            RTLIB::LLRINT_F32,
                                            RTLIB::LLRINT_F64,
                                            RTLIB::LLRINT_F80,
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 328e9430d635..bda3b2f386d0 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1698,15 +1698,20 @@ SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
   // type does not have a strange size (eg: it is not i1).
   EVT VecVT = N->getValueType(0);
   unsigned NumElts = VecVT.getVectorNumElements();
+  if (VecVT.isSubwordVector()) NumElts = VecVT.getSimpleVT().getSubwordPacking(); /* get number of subword elements for subword vectors */
   assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
          "Legal vector of one illegal element?");
 
   // Promote the inserted value.  The type does not need to match the
   // vector element type.  Check that any extra bits introduced will be
   // truncated away.
-  assert(N->getOperand(0).getValueSizeInBits() >=
-         N->getValueType(0).getScalarSizeInBits() &&
-         "Type of inserted value narrower than vector element type!");
+  if (VecVT.isSubwordVector()) {
+    // do not check
+  } else {
+    assert(N->getOperand(0).getValueSizeInBits() >=
+           N->getValueType(0).getScalarSizeInBits() &&
+           "Type of inserted value narrower than vector element type!");
+  }
 
   SmallVector<SDValue, 16> NewOps;
   for (unsigned i = 0; i < NumElts; ++i)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 8d17d8fc68b1..7910ae1b6d49 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -570,6 +570,7 @@ private:
   SDValue SoftenFloatOp_BITCAST(SDNode *N);
   SDValue SoftenFloatOp_BR_CC(SDNode *N);
   SDValue SoftenFloatOp_FP_ROUND(SDNode *N);
+  SDValue SoftenFloatOp_FP_EXTEND(SDNode *N);
   SDValue SoftenFloatOp_FP_TO_XINT(SDNode *N);
   SDValue SoftenFloatOp_FP_TO_XINT_SAT(SDNode *N);
   SDValue SoftenFloatOp_LROUND(SDNode *N);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index ebe3bfc4b75a..50a80532d2cc 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -183,7 +183,7 @@ bool VectorLegalizer::Run() {
        E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I) {
     // Check if the values of the nodes contain vectors. We don't need to check
     // the operands because we are going to check their values at some point.
-    HasVectors = llvm::any_of(I->values(), [](EVT T) { return T.isVector(); });
+    HasVectors = llvm::any_of(I->values(), [](EVT T) { return (T.isVector() && !T.isSubwordVector()); });
 
     // If we found a vector node we can start the legalization.
     if (HasVectors)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 2a98464425c4..7c8e625e7e2a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -945,16 +945,40 @@ static void VerifySDNode(SDNode *N) {
   case ISD::BUILD_VECTOR: {
     assert(N->getNumValues() == 1 && "Too many results!");
     assert(N->getValueType(0).isVector() && "Wrong return type!");
+    if (N->getValueType(0).isSubwordVector()) {
+      assert(N->getNumOperands() == N->getValueType(0).getSimpleVT().getSubwordPacking() &&
+           "Wrong number of operands!");
+    } else {
     assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() &&
            "Wrong number of operands!");
-    EVT EltVT = N->getValueType(0).getVectorElementType();
-    for (const SDUse &Op : N->ops()) {
-      assert((Op.getValueType() == EltVT ||
-              (EltVT.isInteger() && Op.getValueType().isInteger() &&
-               EltVT.bitsLE(Op.getValueType()))) &&
-             "Wrong operand type!");
-      assert(Op.getValueType() == N->getOperand(0).getValueType() &&
-             "Operands must all have the same type");
+    }
+    //EVT EltVT = N->getValueType(0).getVectorElementType();
+    //for (const SDUse &Op : N->ops()) {
+      //assert((Op.getValueType() == EltVT ||
+              //(EltVT.isInteger() && Op.getValueType().isInteger() &&
+               //EltVT.bitsLE(Op.getValueType()))) &&
+             //"Wrong operand type!");
+      //assert(Op.getValueType() == N->getOperand(0).getValueType() &&
+             //"Operands must all have the same type");
+
+    if (N->getValueType(0).isSubwordVector()) { /* build subword packed type */
+      EVT EltVT = N->getValueType(0).getVectorElementType(); /* output element type */
+      assert(EltVT.isInteger() && "Only integer result is allowed");
+      for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) {
+        assert(I->getValueType().isInteger() && "Only integer operand types are allowed");
+      }
+
+    } else {
+      EVT EltVT = N->getValueType(0).getVectorElementType(); /* output element type */
+      for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) {
+        assert((I->getValueType() == EltVT ||
+               (EltVT.isInteger() && I->getValueType().isInteger() &&
+                EltVT.bitsLE(I->getValueType()))) &&
+              "Wrong operand type!");
+
+        assert(I->getValueType() == N->getOperand(0).getValueType() &&
+               "Operands must all have the same type");
+      }
     }
     break;
   }
@@ -1291,12 +1315,14 @@ SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT) {
   EVT OpVT = Op.getValueType();
   assert(VT.isInteger() && OpVT.isInteger() &&
          "Cannot getZeroExtendInReg FP types");
+  if (!VT.isSubwordVector() && !OpVT.isSubwordVector()) {
   assert(VT.isVector() == OpVT.isVector() &&
          "getZeroExtendInReg type should be vector iff the operand "
          "type is vector!");
   assert((!VT.isVector() ||
           VT.getVectorElementCount() == OpVT.getVectorElementCount()) &&
          "Vector element counts must match in getZeroExtendInReg");
+  }
   assert(VT.bitsLE(OpVT) && "Not extending!");
   if (OpVT == VT)
     return Op;
@@ -1365,7 +1391,6 @@ SDValue SelectionDAG::getConstant(const ConstantInt &Val, const SDLoc &DL,
 
   EVT EltVT = VT.getScalarType();
   const ConstantInt *Elt = &Val;
-
   // In some cases the vector type is legal but the element type is illegal and
   // needs to be promoted, for example v8i8 on ARM.  In this case, promote the
   // inserted value (the type does not need to match the vector element type).
@@ -1460,11 +1485,13 @@ SDValue SelectionDAG::getConstant(const ConstantInt &Val, const SDLoc &DL,
   }
 
   SDValue Result(N, 0);
-  if (VT.isScalableVector())
+  if (VT.isSubwordVector()) { // vector is a subword type
+    Result = getNode(ISD::BITCAST, DL, VT);
+  } else if (VT.isScalableVector()) {
     Result = getSplatVector(VT, DL, Result);
-  else if (VT.isVector())
+  } else if (VT.isVector()) {
     Result = getSplatBuildVector(VT, DL, Result);
-
+  }
   return Result;
 }
 
@@ -2548,6 +2575,9 @@ bool SelectionDAG::isSplatValue(SDValue V, const APInt &DemandedElts,
   case ISD::EXTRACT_SUBVECTOR: {
     // Offset the demanded elts by the subvector index.
     SDValue Src = V.getOperand(0);
+    // should we support subword vectors ?
+    if (Src.getValueType().isSubwordVector())
+      return false;
     // We don't support scalable vectors at the moment.
     if (Src.getValueType().isScalableVector())
       return false;
@@ -4503,8 +4533,13 @@ static SDValue FoldBUILD_VECTOR(const SDLoc &DL, EVT VT,
   assert(NumOps != 0 && "Can't build an empty vector!");
   assert(!VT.isScalableVector() &&
          "BUILD_VECTOR cannot be used with scalable types");
+  if (VT.isSubwordVector()) {
+    assert(VT.getSimpleVT().getSubwordPacking() == (unsigned)NumOps &&
+          "Incorrect element count in BUILD_VECTOR for a subword!");
+  } else {
   assert(VT.getVectorNumElements() == (unsigned)NumOps &&
          "Incorrect element count in BUILD_VECTOR!");
+  }
 
   // BUILD_VECTOR of UNDEFs is UNDEF.
   if (llvm::all_of(Ops, [](SDValue Op) { return Op.isUndef(); }))
@@ -4884,14 +4919,18 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
   case ISD::SIGN_EXTEND:
     assert(VT.isInteger() && Operand.getValueType().isInteger() &&
            "Invalid SIGN_EXTEND!");
+    if (!VT.isSubwordVector() && !Operand.getValueType().isSubwordVector()) {
     assert(VT.isVector() == Operand.getValueType().isVector() &&
            "SIGN_EXTEND result type type should be vector iff the operand "
            "type is vector!");
+    }
     if (Operand.getValueType() == VT) return Operand;   // noop extension
+    if (!VT.isSubwordVector() && !Operand.getValueType().isSubwordVector()) {
     assert((!VT.isVector() ||
             VT.getVectorElementCount() ==
                 Operand.getValueType().getVectorElementCount()) &&
            "Vector element count mismatch!");
+    }
     assert(Operand.getValueType().bitsLT(VT) &&
            "Invalid sext node, dst < src!");
     if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND)
@@ -4903,14 +4942,18 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
   case ISD::ZERO_EXTEND:
     assert(VT.isInteger() && Operand.getValueType().isInteger() &&
            "Invalid ZERO_EXTEND!");
+    if (!VT.isSubwordVector() && !Operand.getValueType().isSubwordVector()) {
     assert(VT.isVector() == Operand.getValueType().isVector() &&
            "ZERO_EXTEND result type type should be vector iff the operand "
            "type is vector!");
+    }
     if (Operand.getValueType() == VT) return Operand;   // noop extension
+    if (!VT.isSubwordVector() && !Operand.getValueType().isSubwordVector()) {
     assert((!VT.isVector() ||
             VT.getVectorElementCount() ==
                 Operand.getValueType().getVectorElementCount()) &&
            "Vector element count mismatch!");
+    }
     assert(Operand.getValueType().bitsLT(VT) &&
            "Invalid zext node, dst < src!");
     if (OpOpcode == ISD::ZERO_EXTEND)   // (zext (zext x)) -> (zext x)
@@ -4922,14 +4965,18 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
   case ISD::ANY_EXTEND:
     assert(VT.isInteger() && Operand.getValueType().isInteger() &&
            "Invalid ANY_EXTEND!");
+    if (!VT.isSubwordVector() && !Operand.getValueType().isSubwordVector()) {
     assert(VT.isVector() == Operand.getValueType().isVector() &&
            "ANY_EXTEND result type type should be vector iff the operand "
            "type is vector!");
+    }
     if (Operand.getValueType() == VT) return Operand;   // noop extension
+    if (!VT.isSubwordVector() && !Operand.getValueType().isSubwordVector()) {
     assert((!VT.isVector() ||
             VT.getVectorElementCount() ==
                 Operand.getValueType().getVectorElementCount()) &&
            "Vector element count mismatch!");
+    }
     assert(Operand.getValueType().bitsLT(VT) &&
            "Invalid anyext node, dst < src!");
 
@@ -4952,14 +4999,18 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
   case ISD::TRUNCATE:
     assert(VT.isInteger() && Operand.getValueType().isInteger() &&
            "Invalid TRUNCATE!");
+    if (!VT.isSubwordVector() && !Operand.getValueType().isSubwordVector()) {
     assert(VT.isVector() == Operand.getValueType().isVector() &&
            "TRUNCATE result type type should be vector iff the operand "
            "type is vector!");
+    }
     if (Operand.getValueType() == VT) return Operand;   // noop truncate
+    if (!VT.isSubwordVector() && !Operand.getValueType().isSubwordVector()) {
     assert((!VT.isVector() ||
             VT.getVectorElementCount() ==
                 Operand.getValueType().getVectorElementCount()) &&
            "Vector element count mismatch!");
+    }
     assert(Operand.getValueType().bitsGT(VT) &&
            "Invalid truncate node, src < dst!");
     if (OpOpcode == ISD::TRUNCATE)
@@ -5598,11 +5649,25 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
     break;
   case ISD::OR:
   case ISD::XOR:
+    assert(VT.isInteger() && "This operator does not apply to FP types!");
+    assert(N1.getValueType() == N2.getValueType() &&
+           N1.getValueType() == VT && "Binary operator types must match!");
+    // (X ^|+- 0) -> X.  This commonly occurs when legalizing i64 values, so
+    // it's worth handling here.
+    if (N2C && N2C->isNullValue())
+      return N1;
+    break;
   case ISD::ADD:
   case ISD::SUB:
     assert(VT.isInteger() && "This operator does not apply to FP types!");
-    assert(N1.getValueType() == N2.getValueType() &&
+    if ((N1.getValueType().isSubwordVector() && N1.getValueType().isVector()) || (N1.getValueType().isVector() && N2.getValueType().isSubwordVector())) { // for vector-subword vector
+      assert(//N1.getValueType().getVectorElementType()==N2.getValueType().getVectorElementType() &&
+         N1.getValueType().getVectorNumElements()==N2.getValueType().getVectorNumElements() &&
+         "Binary operator types must have the same size!");
+    } else {
+      assert(N1.getValueType() == N2.getValueType() &&
            N1.getValueType() == VT && "Binary operator types must match!");
+    }
     // (X ^|+- 0) -> X.  This commonly occurs when legalizing i64 values, so
     // it's worth handling here.
     if (N2C && N2C->isNullValue())
@@ -5613,8 +5678,14 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
     break;
   case ISD::MUL:
     assert(VT.isInteger() && "This operator does not apply to FP types!");
+    if ((N1.getValueType().isSubwordVector() && N1.getValueType().isVector()) || (N1.getValueType().isVector() && N2.getValueType().isSubwordVector())) { // for vector-subword vector
+      assert(//N1.getValueType().getVectorElementType()==N2.getValueType().getVectorElementType() &&
+         N1.getValueType().getVectorNumElements()==N2.getValueType().getVectorNumElements() &&
+         "Binary operator types must have the same size!");
+    } else {
     assert(N1.getValueType() == N2.getValueType() &&
            N1.getValueType() == VT && "Binary operator types must match!");
+    }
     if (VT.isVector() && VT.getVectorElementType() == MVT::i1)
       return getNode(ISD::AND, DL, VT, N1, N2);
     if (N2C && (N1.getOpcode() == ISD::VSCALE) && Flags.hasNoSignedWrap()) {
@@ -5795,10 +5866,12 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
     break;
   }
   case ISD::EXTRACT_VECTOR_ELT:
-    assert(VT.getSizeInBits() >= N1.getValueType().getScalarSizeInBits() &&
+    if (N1.getValueType().isSubwordVector()) {
+    } else {
+      assert(VT.getSizeInBits() >= N1.getValueType().getScalarSizeInBits() &&
            "The result of EXTRACT_VECTOR_ELT must be at least as wide as the \
              element type of the vector.");
-
+    }
     // Extract from an undefined value or using an undefined index is undefined.
     if (N1.isUndef() || N2.isUndef())
       return getUNDEF(VT);
@@ -6074,6 +6147,17 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
   }
   case ISD::SETCC: {
     assert(VT.isInteger() && "SETCC result type must be an integer!");
+
+    if (N1.getValueType() != N2.getValueType()) {
+      unsigned n1bw = N1.getValueType().getSizeInBits();
+      unsigned n2bw = N2.getValueType().getSizeInBits();
+      if (n1bw<n2bw) {
+        N1 = getNode(ISD::ZERO_EXTEND, DL, N2.getValueType(), N1);
+      } else {
+        N2 = getNode(ISD::ZERO_EXTEND, DL, N1.getValueType(), N2);
+      }
+    }
+
     assert(N1.getValueType() == N2.getValueType() &&
            "SETCC operands must have the same type!");
     assert(VT.isVector() == N1.getValueType().isVector() &&
@@ -7388,12 +7472,14 @@ SDValue SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
            "Should only be an extending load, not truncating!");
     assert(VT.isInteger() == MemVT.isInteger() &&
            "Cannot convert from FP to Int or Int -> FP!");
+    if (!VT.isSubwordVector() && !MemVT.isSubwordVector()) {
     assert(VT.isVector() == MemVT.isVector() &&
            "Cannot use an ext load to convert to or from a vector!");
     assert((!VT.isVector() ||
             VT.getVectorElementCount() == MemVT.getVectorElementCount()) &&
            "Cannot use an ext load to change the number of vector elements!");
   }
+  }
 
   bool Indexed = AM != ISD::UNINDEXED;
   assert((Indexed || Offset.isUndef()) && "Unindexed load with an offset!");
@@ -7559,11 +7645,13 @@ SDValue SelectionDAG::getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val,
          "Should only be a truncating store, not extending!");
   assert(VT.isInteger() == SVT.isInteger() &&
          "Can't do FP-INT conversion!");
+  if (!VT.isSubwordVector() && !SVT.isSubwordVector()) {
   assert(VT.isVector() == SVT.isVector() &&
          "Cannot use trunc store to convert to or from a vector!");
   assert((!VT.isVector() ||
           VT.getVectorElementCount() == SVT.getVectorElementCount()) &&
          "Cannot use trunc store to change the number of vector elements!");
+  }
 
   SDVTList VTs = getVTList(MVT::Other);
   SDValue Undef = getUNDEF(Ptr.getValueType());
@@ -9752,6 +9840,10 @@ const EVT *SDNode::getValueTypeList(EVT VT) {
     sys::SmartScopedLock<true> Lock(*VTMutex);
     return &(*EVTs->insert(VT).first);
   }
+  if (VT.isSubwordVector()) {
+//std::raise(SIGINT);
+//    return EVT::getSubwordVT(llvm::LLVMContext(), MVT::vswp32, VT.getSubwordElmBitWidth(), VT.getSubwordPacking());
+  }
   assert(VT.getSimpleVT() < MVT::VALUETYPE_SIZE && "Value type out of range!");
   return &SimpleVTArray->VTs[VT.getSimpleVT().SimpleTy];
 }
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index a08548393979..b432d087dfa3 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -172,7 +172,7 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL,
                                                    PartVT, ValueVT, CC))
     return Val;
 
-  if (ValueVT.isVector())
+  if (ValueVT.isVector() && !ValueVT.isSubwordVector())
     return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT, V,
                                   CC);
 
@@ -483,7 +483,7 @@ static void getCopyToParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val,
   EVT ValueVT = Val.getValueType();
 
   // Handle the vector case separately.
-  if (ValueVT.isVector())
+  if (ValueVT.isVector() && !ValueVT.isSubwordVector())
     return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V,
                                 CallConv);
 
@@ -494,7 +494,7 @@ static void getCopyToParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val,
 
   if (NumParts == 0)
     return;
-
+  if (!ValueVT.isSubwordVector())
   assert(!ValueVT.isVector() && "Vector case handled elsewhere");
   EVT PartEVT = PartVT;
   if (PartEVT == ValueVT) {
@@ -1626,8 +1626,11 @@ SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
         Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
       else
         Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
-
-      if (isa<ScalableVectorType>(VecTy))
+      if (isa<SubwordVectorType>(VecTy)) {
+        SmallVector<SDValue, 16> Ops;
+        Ops.assign(cast<SubwordVectorType>(VecTy)->getNumElements(), Op);
+        return NodeMap[V] = DAG.getBuildVector(VT, getCurSDLoc(), Ops);
+      } else if (isa<ScalableVectorType>(VecTy))
         return NodeMap[V] = DAG.getSplatVector(VT, getCurSDLoc(), Op);
       else {
         SmallVector<SDValue, 16> Ops;
@@ -4127,13 +4130,34 @@ void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
                             DAG.getConstant(Offsets[i], dl, PtrVT),
                             Flags);
 
-    SDValue L = DAG.getLoad(MemVTs[i], dl, Root, A,
-                            MachinePointerInfo(SV, Offsets[i]), Alignment,
-                            MMOFlags, AAInfo, Ranges);
-    Chains[ChainI] = L.getValue(1);
+    SDValue L;
+
+    if (ValueVTs[i].isSubwordVector()) {
+      L = DAG.getLoad(ValueVTs[i], dl, Root, A,
+                              MachinePointerInfo(SV, Offsets[i]), Alignment,
+                              MMOFlags, AAInfo, Ranges);
+
+      if (MemVTs[i].isInteger() &&
+          MemVTs[i].getSimpleVT()==ValueVTs[i].getVectorElementType().getSimpleVT()) { /* all subword vectors are placed */
+
+      } else {
+
+      }
+
+      Chains[ChainI] = L.getValue(1);
+
+    } else {
+
+      L = DAG.getLoad(MemVTs[i], dl, Root, A,
+                              MachinePointerInfo(SV, Offsets[i]), Alignment,
+                              MMOFlags, AAInfo, Ranges);
+
+      Chains[ChainI] = L.getValue(1);
+
+      if (MemVTs[i] != ValueVTs[i])
+        L = DAG.getZExtOrTrunc(L, dl, ValueVTs[i]);
+    }
 
-    if (MemVTs[i] != ValueVTs[i])
-      L = DAG.getZExtOrTrunc(L, dl, ValueVTs[i]);
 
     Values[i] = L;
   }
@@ -4271,12 +4295,29 @@ void SelectionDAGBuilder::visitStore(const StoreInst &I) {
     SDValue Add =
         DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(Offsets[i]), dl, Flags);
     SDValue Val = SDValue(Src.getNode(), Src.getResNo() + i);
-    if (MemVTs[i] != ValueVTs[i])
-      Val = DAG.getPtrExtOrTrunc(Val, dl, MemVTs[i]);
-    SDValue St =
-        DAG.getStore(Root, dl, Val, Add, MachinePointerInfo(PtrV, Offsets[i]),
-                     Alignment, MMOFlags, AAInfo);
-    Chains[ChainI] = St;
+
+    if (ValueVTs[i].isSubwordVector()) {
+
+      if (MemVTs[i].isInteger() &&
+          MemVTs[i].getSimpleVT()==ValueVTs[i].getVectorElementType().getSimpleVT()) { /* all subword vectors are placed */
+
+      } else {
+        Val = DAG.getPtrExtOrTrunc(Val, dl, MemVTs[i]);
+      }
+
+      SDValue St =
+          DAG.getStore(Root, dl, Val, Add, MachinePointerInfo(PtrV, Offsets[i]),
+                       Alignment, MMOFlags, AAInfo);
+      Chains[ChainI] = St;
+
+    } else {
+      if (MemVTs[i] != ValueVTs[i])
+        Val = DAG.getPtrExtOrTrunc(Val, dl, MemVTs[i]);
+      SDValue St =
+          DAG.getStore(Root, dl, Val, Add, MachinePointerInfo(PtrV, Offsets[i]),
+                       Alignment, MMOFlags, AAInfo);
+      Chains[ChainI] = St;
+    }
   }
 
   SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 7f80ce37e28a..5b9ce7743642 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -301,7 +301,8 @@ void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
   // not supporting it. We can update this code when libgcc provides such
   // functions.
 
-  assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128)
+  assert((VT == MVT::f16 || VT == MVT::f32 || VT == MVT::f64 ||
+          VT == MVT::f128 || VT == MVT::ppcf128)
          && "Unsupported setcc type!");
 
   // Expand into one or more soft-fp libcall(s).
@@ -310,37 +311,43 @@ void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
   switch (CCCode) {
   case ISD::SETEQ:
   case ISD::SETOEQ:
-    LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
+    LC1 = (VT == MVT::f16) ? RTLIB::OEQ_F16 :
+          (VT == MVT::f32) ? RTLIB::OEQ_F32 :
           (VT == MVT::f64) ? RTLIB::OEQ_F64 :
           (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128;
     break;
   case ISD::SETNE:
   case ISD::SETUNE:
-    LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
+    LC1 = (VT == MVT::f16) ? RTLIB::UNE_F16 :
+          (VT == MVT::f32) ? RTLIB::UNE_F32 :
           (VT == MVT::f64) ? RTLIB::UNE_F64 :
           (VT == MVT::f128) ? RTLIB::UNE_F128 : RTLIB::UNE_PPCF128;
     break;
   case ISD::SETGE:
   case ISD::SETOGE:
-    LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
+    LC1 = (VT == MVT::f16) ? RTLIB::OGE_F16 :
+          (VT == MVT::f32) ? RTLIB::OGE_F32 :
           (VT == MVT::f64) ? RTLIB::OGE_F64 :
           (VT == MVT::f128) ? RTLIB::OGE_F128 : RTLIB::OGE_PPCF128;
     break;
   case ISD::SETLT:
   case ISD::SETOLT:
-    LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
+    LC1 = (VT == MVT::f16) ? RTLIB::OLT_F16 :
+          (VT == MVT::f32) ? RTLIB::OLT_F32 :
           (VT == MVT::f64) ? RTLIB::OLT_F64 :
           (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128;
     break;
   case ISD::SETLE:
   case ISD::SETOLE:
-    LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
+    LC1 = (VT == MVT::f16) ? RTLIB::OLE_F16 :
+          (VT == MVT::f32) ? RTLIB::OLE_F32 :
           (VT == MVT::f64) ? RTLIB::OLE_F64 :
           (VT == MVT::f128) ? RTLIB::OLE_F128 : RTLIB::OLE_PPCF128;
     break;
   case ISD::SETGT:
   case ISD::SETOGT:
-    LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
+    LC1 = (VT == MVT::f16) ? RTLIB::OGT_F16 :
+          (VT == MVT::f32) ? RTLIB::OGT_F32 :
           (VT == MVT::f64) ? RTLIB::OGT_F64 :
           (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128;
     break;
@@ -348,7 +355,8 @@ void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
     ShouldInvertCC = true;
     LLVM_FALLTHROUGH;
   case ISD::SETUO:
-    LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
+    LC1 = (VT == MVT::f16) ? RTLIB::UO_F16 :
+          (VT == MVT::f32) ? RTLIB::UO_F32 :
           (VT == MVT::f64) ? RTLIB::UO_F64 :
           (VT == MVT::f128) ? RTLIB::UO_F128 : RTLIB::UO_PPCF128;
     break;
@@ -357,10 +365,12 @@ void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
     ShouldInvertCC = true;
     LLVM_FALLTHROUGH;
   case ISD::SETUEQ:
-    LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
+    LC1 = (VT == MVT::f16) ? RTLIB::UO_F16 :
+          (VT == MVT::f32) ? RTLIB::UO_F32 :
           (VT == MVT::f64) ? RTLIB::UO_F64 :
           (VT == MVT::f128) ? RTLIB::UO_F128 : RTLIB::UO_PPCF128;
-    LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
+    LC2 = (VT == MVT::f16) ? RTLIB::OEQ_F16 :
+          (VT == MVT::f32) ? RTLIB::OEQ_F32 :
           (VT == MVT::f64) ? RTLIB::OEQ_F64 :
           (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128;
     break;
@@ -369,22 +379,26 @@ void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
     ShouldInvertCC = true;
     switch (CCCode) {
     case ISD::SETULT:
-      LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
+      LC1 = (VT == MVT::f16) ? RTLIB::OGE_F16 :
+            (VT == MVT::f32) ? RTLIB::OGE_F32 :
             (VT == MVT::f64) ? RTLIB::OGE_F64 :
             (VT == MVT::f128) ? RTLIB::OGE_F128 : RTLIB::OGE_PPCF128;
       break;
     case ISD::SETULE:
-      LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
+      LC1 = (VT == MVT::f16) ? RTLIB::OGT_F16 :
+            (VT == MVT::f32) ? RTLIB::OGT_F32 :
             (VT == MVT::f64) ? RTLIB::OGT_F64 :
             (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128;
       break;
     case ISD::SETUGT:
-      LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
+      LC1 = (VT == MVT::f16) ? RTLIB::OLE_F16 :
+            (VT == MVT::f32) ? RTLIB::OLE_F32 :
             (VT == MVT::f64) ? RTLIB::OLE_F64 :
             (VT == MVT::f128) ? RTLIB::OLE_F128 : RTLIB::OLE_PPCF128;
       break;
     case ISD::SETUGE:
-      LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
+      LC1 = (VT == MVT::f16) ? RTLIB::OLT_F16 :
+            (VT == MVT::f32) ? RTLIB::OLT_F32 :
             (VT == MVT::f64) ? RTLIB::OLT_F64 :
             (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128;
       break;
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index 3c5dd29036db..d1fa74e5440a 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -214,12 +214,14 @@ void TargetLoweringBase::InitLibcalls(const Triple &TT) {
 /// GetFPLibCall - Helper to return the right libcall for the given floating
 /// point type, or UNKNOWN_LIBCALL if there is none.
 RTLIB::Libcall RTLIB::getFPLibCall(EVT VT,
+                                   RTLIB::Libcall Call_F16,
                                    RTLIB::Libcall Call_F32,
                                    RTLIB::Libcall Call_F64,
                                    RTLIB::Libcall Call_F80,
                                    RTLIB::Libcall Call_F128,
                                    RTLIB::Libcall Call_PPCF128) {
   return
+    VT == MVT::f16 ? Call_F16 :
     VT == MVT::f32 ? Call_F32 :
     VT == MVT::f64 ? Call_F64 :
     VT == MVT::f80 ? Call_F80 :
@@ -300,6 +302,8 @@ RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
 /// UNKNOWN_LIBCALL if there is none.
 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
   if (OpVT == MVT::f16) {
+    if (RetVT == MVT::i16)
+      return FPTOSINT_F16_I16;
     if (RetVT == MVT::i32)
       return FPTOSINT_F16_I32;
     if (RetVT == MVT::i64)
@@ -349,6 +353,8 @@ RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
 /// UNKNOWN_LIBCALL if there is none.
 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
   if (OpVT == MVT::f16) {
+    if (RetVT == MVT::i16)
+      return FPTOUINT_F16_I16;
     if (RetVT == MVT::i32)
       return FPTOUINT_F16_I32;
     if (RetVT == MVT::i64)
@@ -487,7 +493,7 @@ RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
 }
 
 RTLIB::Libcall RTLIB::getPOWI(EVT RetVT) {
-  return getFPLibCall(RetVT, POWI_F32, POWI_F64, POWI_F80, POWI_F128,
+  return getFPLibCall(RetVT, POWI_F16, POWI_F32, POWI_F64, POWI_F80, POWI_F128,
                       POWI_PPCF128);
 }
 
@@ -660,30 +666,37 @@ RTLIB::Libcall RTLIB::getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
 /// InitCmpLibcallCCs - Set default comparison libcall CC.
 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
   memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
+  CCs[RTLIB::OEQ_F16] = ISD::SETEQ;
   CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
   CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
   CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
   CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;
+  CCs[RTLIB::UNE_F16] = ISD::SETNE;
   CCs[RTLIB::UNE_F32] = ISD::SETNE;
   CCs[RTLIB::UNE_F64] = ISD::SETNE;
   CCs[RTLIB::UNE_F128] = ISD::SETNE;
   CCs[RTLIB::UNE_PPCF128] = ISD::SETNE;
+  CCs[RTLIB::OGE_F16] = ISD::SETGE;
   CCs[RTLIB::OGE_F32] = ISD::SETGE;
   CCs[RTLIB::OGE_F64] = ISD::SETGE;
   CCs[RTLIB::OGE_F128] = ISD::SETGE;
   CCs[RTLIB::OGE_PPCF128] = ISD::SETGE;
+  CCs[RTLIB::OLT_F16] = ISD::SETLT;
   CCs[RTLIB::OLT_F32] = ISD::SETLT;
   CCs[RTLIB::OLT_F64] = ISD::SETLT;
   CCs[RTLIB::OLT_F128] = ISD::SETLT;
   CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
+  CCs[RTLIB::OLE_F16] = ISD::SETLE;
   CCs[RTLIB::OLE_F32] = ISD::SETLE;
   CCs[RTLIB::OLE_F64] = ISD::SETLE;
   CCs[RTLIB::OLE_F128] = ISD::SETLE;
   CCs[RTLIB::OLE_PPCF128] = ISD::SETLE;
+  CCs[RTLIB::OGT_F16] = ISD::SETGT;
   CCs[RTLIB::OGT_F32] = ISD::SETGT;
   CCs[RTLIB::OGT_F64] = ISD::SETGT;
   CCs[RTLIB::OGT_F128] = ISD::SETGT;
   CCs[RTLIB::OGT_PPCF128] = ISD::SETGT;
+  CCs[RTLIB::UO_F16] = ISD::SETNE;
   CCs[RTLIB::UO_F32] = ISD::SETNE;
   CCs[RTLIB::UO_F64] = ISD::SETNE;
   CCs[RTLIB::UO_F128] = ISD::SETNE;
@@ -1370,6 +1383,8 @@ void TargetLoweringBase::computeRegisterProperties(
   // Decide how to handle f16. If the target does not have native f16 support,
   // promote it to f32, because there are no f16 library calls (except for
   // conversions).
+  // The f16 library calls have been added. For partial soft float (when f16 is
+  // not legal but f32 is legal type) there are not all operations supported.
   if (!isTypeLegal(MVT::f16)) {
     // Allow targets to control how we legalize half.
     if (softPromoteHalfType()) {
diff --git a/llvm/lib/CodeGen/ValueTypes.cpp b/llvm/lib/CodeGen/ValueTypes.cpp
index 4876b9e23717..185975718d9d 100644
--- a/llvm/lib/CodeGen/ValueTypes.cpp
+++ b/llvm/lib/CodeGen/ValueTypes.cpp
@@ -76,6 +76,14 @@ bool EVT::isExtendedVector() const {
   return LLVMTy->isVectorTy();
 }
 
+bool EVT::isExtendedSubword() const {
+  assert(isExtended() && "Type is not extended!");
+  if (LLVMTy->isVectorTy()) {
+    return LLVMTy->getVectorIsSubword();
+  }
+  return false;
+}
+
 bool EVT::isExtended16BitVector() const {
   return isExtendedVector() && getExtendedSizeInBits() == 16;
 }
@@ -172,6 +180,24 @@ std::string EVT::getEVTString() const {
   case MVT::Untyped:   return "Untyped";
   case MVT::funcref:   return "funcref";
   case MVT::externref: return "externref";
+
+  case MVT::vswp32i1:  return "vswp32i1";
+  case MVT::vswp32i2:  return "vswp32i2";
+  case MVT::vswp32i3:  return "vswp32i3";
+  case MVT::vswp32i4:  return "vswp32i4";
+  case MVT::vswp32i8:  return "vswp32i8";
+  case MVT::vswp32i16: return "vswp32i16";
+  case MVT::vswp64i1:  return "vswp64i1";
+  case MVT::vswp64i2:  return "vswp64i2";
+  case MVT::vswp64i3:  return "vswp64i3";
+  case MVT::vswp64i4:  return "vswp64i4";
+  case MVT::vswp64i8:  return "vswp64i8";
+  case MVT::vswp64i16: return "vswp64i16";
+  case MVT::vswp64i32: return "vswp64i32";
+
+  //case MVT::vswp32:  //return "vswp32";
+  //case MVT::vswp64:  //return "vswp64";
+    //return ("vswp32i" + utostr(ElmBitWidth) + "x" + utostr(Packing));
   }
 }
 
@@ -517,6 +543,39 @@ Type *EVT::getTypeForEVT(LLVMContext &Context) const {
   case MVT::nxv8f64:
     return ScalableVectorType::get(Type::getDoubleTy(Context), 8);
   case MVT::Metadata: return Type::getMetadataTy(Context);
+
+  /* return type for basic vector of packed elements - TODO: now it returns vector with one subword element (the second argument !) */
+//  case MVT::vswp32:
+//    return SubwordVectorType::get( Type::getIntNTy(Context, ElmBitWidth), 1, Type::getInt32Ty(Context), Packing, false);
+//  case MVT::vswp64:
+//    return SubwordVectorType::get(Type::getIntNTy(Context, ElmBitWidth), 1, Type::getInt64Ty(Context), Packing, false);
+  case MVT::vswp32i1:
+    return SubwordVectorType::get(Type::getIntNTy(Context, 1), 1, Type::getInt32Ty(Context), 32, false);
+  case MVT::vswp32i2:
+    return SubwordVectorType::get(Type::getIntNTy(Context, 2), 1, Type::getInt32Ty(Context), 16, false);
+  case MVT::vswp32i3:
+    return SubwordVectorType::get(Type::getIntNTy(Context, 3), 1, Type::getInt32Ty(Context), 10, false);
+  case MVT::vswp32i4:
+    return SubwordVectorType::get(Type::getIntNTy(Context, 4), 1, Type::getInt32Ty(Context), 8, false);
+  case MVT::vswp32i8:
+    return SubwordVectorType::get(Type::getIntNTy(Context, 8), 1, Type::getInt32Ty(Context), 4, false);
+  case MVT::vswp32i16:
+    return SubwordVectorType::get(Type::getIntNTy(Context, 16), 1, Type::getInt32Ty(Context), 2, false);
+  case MVT::vswp64i1:
+    return SubwordVectorType::get(Type::getIntNTy(Context, 1), 1, Type::getInt64Ty(Context), 64, false);
+  case MVT::vswp64i2:
+    return SubwordVectorType::get(Type::getIntNTy(Context, 2), 1, Type::getInt64Ty(Context), 32, false);
+  case MVT::vswp64i3:
+    return SubwordVectorType::get(Type::getIntNTy(Context, 3), 1, Type::getInt64Ty(Context), 21, false);
+  case MVT::vswp64i4:
+    return SubwordVectorType::get(Type::getIntNTy(Context, 4), 1, Type::getInt64Ty(Context), 16, false);
+  case MVT::vswp64i8:
+    return SubwordVectorType::get(Type::getIntNTy(Context, 8), 1, Type::getInt64Ty(Context), 8, false);
+  case MVT::vswp64i16:
+    return SubwordVectorType::get(Type::getIntNTy(Context, 16), 1, Type::getInt64Ty(Context), 4, false);
+  case MVT::vswp64i32:
+    return SubwordVectorType::get(Type::getIntNTy(Context, 32), 1, Type::getInt64Ty(Context), 2, false);
+
   }
 }
 
@@ -549,6 +608,35 @@ MVT MVT::getVT(Type *Ty, bool HandleUnknown){
       getVT(VTy->getElementType(), /*HandleUnknown=*/ false),
             VTy->getElementCount());
   }
+  case Type::SubwordVectorTyID: {
+    VectorType *VTy = cast <VectorType>(Ty);
+    unsigned elmSz = VTy->getElementType()->getIntegerBitWidth();
+    SubwordVectorType *SubVTy = cast <SubwordVectorType>(Ty);
+    if (SubVTy->getBasicType()->getIntegerBitWidth()==64) {
+      switch (elmSz) {
+        case 1: return MVT(MVT::vswp64i1);
+        case 2: return MVT(MVT::vswp64i2);
+        case 3: return MVT(MVT::vswp64i3);
+        case 4: return MVT(MVT::vswp64i4);
+        case 8: return MVT(MVT::vswp64i8);
+        case 16: return MVT(MVT::vswp64i16);
+        case 32: return MVT(MVT::vswp64i32);
+        default: llvm_unreachable("Unsupported subword type in i64!");
+      }
+      //return MVT(MVT::vswp64);
+    } else {
+      switch (elmSz) {
+        case 1: return MVT(MVT::vswp32i1);
+        case 2: return MVT(MVT::vswp32i2);
+        case 3: return MVT(MVT::vswp32i3);
+        case 4: return MVT(MVT::vswp32i4);
+        case 8: return MVT(MVT::vswp32i8);
+        case 16: return MVT(MVT::vswp32i16);
+        default: llvm_unreachable("Unsupported subword type in i32!");
+      }
+      //return MVT(MVT::vswp32);
+    }
+  }
   }
 }
 
@@ -568,5 +656,17 @@ EVT EVT::getEVT(Type *Ty, bool HandleUnknown){
                        getEVT(VTy->getElementType(), /*HandleUnknown=*/ false),
                        VTy->getElementCount());
   }
+  case Type::SubwordVectorTyID: {
+    SubwordVectorType *SubVTy = cast<SubwordVectorType>(Ty);
+    if (SubVTy->getBasicType()->getIntegerBitWidth()==64) {
+      return getSubwordVT(Ty->getContext(), MVT::i64, /*SubVTy->getElementCount(), */
+                          SubVTy->getElementType()->getIntegerBitWidth(),
+                          SubVTy->getPacking());
+    } else {
+      return getSubwordVT(Ty->getContext(), MVT::i32, /*SubVTy->getElementCount(), */
+                          SubVTy->getElementType()->getIntegerBitWidth(),
+                          SubVTy->getPacking());
+    }
+  }
   }
 }
diff --git a/llvm/lib/ExecutionEngine/ExecutionEngine.cpp b/llvm/lib/ExecutionEngine/ExecutionEngine.cpp
index c8bbf0bcdfda..673fc079341c 100644
--- a/llvm/lib/ExecutionEngine/ExecutionEngine.cpp
+++ b/llvm/lib/ExecutionEngine/ExecutionEngine.cpp
@@ -618,6 +618,9 @@ GenericValue ExecutionEngine::getConstantValue(const Constant *C) {
       case Type::ScalableVectorTyID:
         report_fatal_error(
             "Scalable vector support not yet implemented in ExecutionEngine");
+      case Type::SubwordVectorTyID:
+        report_fatal_error(
+            "Subword vector support not yet implemented in ExecutionEngine");
       case Type::FixedVectorTyID:
         // if the whole vector is 'undef' just reserve memory for the value.
         auto *VTy = cast<FixedVectorType>(C->getType());
@@ -911,6 +914,9 @@ GenericValue ExecutionEngine::getConstantValue(const Constant *C) {
   case Type::ScalableVectorTyID:
     report_fatal_error(
         "Scalable vector support not yet implemented in ExecutionEngine");
+  case Type::SubwordVectorTyID:
+    report_fatal_error(
+        "Subword vector support not yet implemented in ExecutionEngine");
   case Type::FixedVectorTyID: {
     unsigned elemNum;
     Type* ElemTy;
@@ -1056,6 +1062,9 @@ void ExecutionEngine::StoreValueToMemory(const GenericValue &Val,
       }
     }
     break;
+  case Type::SubwordVectorTyID:
+    report_fatal_error(
+        "Subword vector support not yet implemented in ExecutionEngine");
   }
 
   if (sys::IsLittleEndianHost != getDataLayout().isLittleEndian())
@@ -1096,6 +1105,9 @@ void ExecutionEngine::LoadValueFromMemory(GenericValue &Result,
   case Type::ScalableVectorTyID:
     report_fatal_error(
         "Scalable vector support not yet implemented in ExecutionEngine");
+  case Type::SubwordVectorTyID:
+    report_fatal_error(
+        "Subword vector support not yet implemented in ExecutionEngine");
   case Type::FixedVectorTyID: {
     auto *VT = cast<FixedVectorType>(Ty);
     Type *ElemT = VT->getElementType();
diff --git a/llvm/lib/ExecutionEngine/Interpreter/Execution.cpp b/llvm/lib/ExecutionEngine/Interpreter/Execution.cpp
index 770fc9349083..3b45fcc070f7 100644
--- a/llvm/lib/ExecutionEngine/Interpreter/Execution.cpp
+++ b/llvm/lib/ExecutionEngine/Interpreter/Execution.cpp
@@ -170,6 +170,10 @@ static void executeFRemInst(GenericValue &Dest, GenericValue Src1,
       break;
 
 #define IMPLEMENT_VECTOR_INTEGER_ICMP(OP, TY)                                  \
+  case Type::SubwordVectorTyID:                                                \
+    report_fatal_error(                                                        \
+        "Subword vector support not yet implemented");                         \
+    break;                                                                     \
   case Type::FixedVectorTyID:                                                  \
   case Type::ScalableVectorTyID: {                                             \
     assert(Src1.AggregateVal.size() == Src2.AggregateVal.size());              \
@@ -369,6 +373,10 @@ void Interpreter::visitICmpInst(ICmpInst &I) {
   break;
 
 #define IMPLEMENT_VECTOR_FCMP(OP)                                              \
+  case Type::SubwordVectorTyID:                                                \
+    report_fatal_error(                                                        \
+        "Subword vector support not yet implemented");                         \
+    break;                                                                     \
   case Type::FixedVectorTyID:                                                  \
   case Type::ScalableVectorTyID:                                               \
     if (cast<VectorType>(Ty)->getElementType()->isFloatTy()) {                 \
@@ -1955,6 +1963,7 @@ void Interpreter::visitExtractValueInst(ExtractValueInst &I) {
     case Type::ArrayTyID:
     case Type::StructTyID:
     case Type::FixedVectorTyID:
+    case Type::SubwordVectorTyID:
     case Type::ScalableVectorTyID:
       Dest.AggregateVal = pSrc->AggregateVal;
     break;
@@ -2003,6 +2012,7 @@ void Interpreter::visitInsertValueInst(InsertValueInst &I) {
     case Type::ArrayTyID:
     case Type::StructTyID:
     case Type::FixedVectorTyID:
+    case Type::SubwordVectorTyID:
     case Type::ScalableVectorTyID:
       pDest->AggregateVal = Src2.AggregateVal;
     break;
diff --git a/llvm/lib/IR/AsmWriter.cpp b/llvm/lib/IR/AsmWriter.cpp
index 69e2d85e58fe..7f3532f15d20 100644
--- a/llvm/lib/IR/AsmWriter.cpp
+++ b/llvm/lib/IR/AsmWriter.cpp
@@ -606,14 +606,26 @@ void TypePrinting::print(Type *Ty, raw_ostream &OS) {
     return;
   }
   case Type::FixedVectorTyID:
-  case Type::ScalableVectorTyID: {
+  case Type::ScalableVectorTyID:
+  case Type::SubwordVectorTyID: {
     VectorType *PTy = cast<VectorType>(Ty);
     ElementCount EC = PTy->getElementCount();
     OS << "<";
-    if (EC.isScalable())
-      OS << "vscale x ";
-    OS << EC.getKnownMinValue() << " x ";
-    print(PTy->getElementType(), OS);
+    if (isa<SubwordVectorType>(PTy)) {
+      SubwordVectorType *SubTy = cast<SubwordVectorType>(Ty);
+      OS << "subword ";
+      OS << " " << SubTy->getPacking() << " x ";
+      print(PTy->getElementType(), OS);
+      OS << " in ";
+      print(SubTy->getBasicType(), OS);
+      if (SubTy->getSigned())
+        OS << " *";
+    } else {
+      if (EC.isScalable())
+        OS << "vscale x ";
+      OS << EC.getKnownMinValue() << " x ";
+      print(PTy->getElementType(), OS);
+    }
     OS << '>';
     return;
   }
diff --git a/llvm/lib/IR/ConstantFold.cpp b/llvm/lib/IR/ConstantFold.cpp
index e1e28d1230b0..2f96399b29b4 100644
--- a/llvm/lib/IR/ConstantFold.cpp
+++ b/llvm/lib/IR/ConstantFold.cpp
@@ -140,9 +140,11 @@ static Constant *FoldBitCast(Constant *V, Type *DestTy) {
   // and dest type have the same size (otherwise its an illegal cast).
   if (VectorType *DestPTy = dyn_cast<VectorType>(DestTy)) {
     if (VectorType *SrcTy = dyn_cast<VectorType>(V->getType())) {
-      assert(DestPTy->getPrimitiveSizeInBits() ==
-                 SrcTy->getPrimitiveSizeInBits() &&
-             "Not cast between same sized vectors!");
+      if (!DestPTy->getVectorIsSubword() && !SrcTy->getVectorIsSubword()) {
+        assert(DestPTy->getPrimitiveSizeInBits() ==
+                    SrcTy->getPrimitiveSizeInBits() &&
+               "Not cast between same sized vectors!");
+      }
       SrcTy = nullptr;
       // First, check for null.  Undef is already handled.
       if (isa<ConstantAggregateZero>(V))
@@ -400,6 +402,10 @@ Constant *llvm::ConstantFoldCastInstruction(unsigned opc, Constant *V,
     }
   }
 
+  if (DestTy->getTypeID() == Type::SubwordVectorTyID) {
+    return nullptr;
+  }
+
   // If the cast operand is a constant vector, perform the cast by
   // operating on each element. In the cast of bitcasts, the element
   // count may be mismatched; don't attempt to handle that here.
diff --git a/llvm/lib/IR/Constants.cpp b/llvm/lib/IR/Constants.cpp
index 6c75085a6678..1f396afde403 100644
--- a/llvm/lib/IR/Constants.cpp
+++ b/llvm/lib/IR/Constants.cpp
@@ -378,6 +378,10 @@ Constant *Constant::getNullValue(Type *Ty) {
     return ConstantAggregateZero::get(Ty);
   case Type::TokenTyID:
     return ConstantTokenNone::get(Ty->getContext());
+
+  case Type::SubwordVectorTyID:
+    return ConstantAggregateZero::get(Ty);
+
   default:
     // Function, Label, or Opaque type?
     llvm_unreachable("Cannot create a null constant of that type!");
@@ -1247,9 +1251,12 @@ ConstantAggregate::ConstantAggregate(Type *T, ValueTy VT,
   if (auto *ST = dyn_cast<StructType>(T)) {
     if (ST->isOpaque())
       return;
-    for (unsigned I = 0, E = V.size(); I != E; ++I)
-      assert(V[I]->getType() == ST->getTypeAtIndex(I) &&
+    if (!T->getVectorIsSubword()) {
+      for (unsigned I = 0, E = V.size(); I != E; ++I) {
+        assert(V[I]->getType() == ST->getTypeAtIndex(I) &&
              "Initializer for struct element doesn't match!");
+      }
+    }
   }
 }
 
@@ -1978,7 +1985,8 @@ Constant *ConstantExpr::getCast(unsigned oc, Constant *C, Type *Ty,
   Instruction::CastOps opc = Instruction::CastOps(oc);
   assert(Instruction::isCast(opc) && "opcode out of range");
   assert(C && Ty && "Null arguments to getCast");
-  assert(CastInst::castIsValid(opc, C, Ty) && "Invalid constantexpr cast!");
+  if (!Ty->getVectorIsSubword())
+    assert(CastInst::castIsValid(opc, C, Ty) && "Invalid constantexpr cast!");
 
   switch (opc) {
   default:
@@ -2288,8 +2296,18 @@ Constant *ConstantExpr::get(unsigned Opcode, Constant *C1, Constant *C2,
   // Check the operands for consistency first.
   assert(Instruction::isBinaryOp(Opcode) &&
          "Invalid opcode in binary constant expression");
-  assert(C1->getType() == C2->getType() &&
-         "Operand types in binary constant expression should match");
+
+  if (C1->getType()->getVectorIsSubword() || C2->getType()->getVectorIsSubword()) {
+    if (!C1->getType()->isVectorTy() || !C2->getType()->isVectorTy()) {
+      assert(false &&
+             "Operand types (SWAR) are not vectors");
+    }
+
+  } else {
+    // Check the operands for consistency first.
+    assert(C1->getType() == C2->getType() &&
+           "Operand types in binary constant expression should match");
+  }
 
 #ifndef NDEBUG
   switch (Opcode) {
@@ -2563,8 +2581,17 @@ Constant *ConstantExpr::getInsertElement(Constant *Val, Constant *Elt,
                                          Constant *Idx, Type *OnlyIfReducedTy) {
   assert(Val->getType()->isVectorTy() &&
          "Tried to create insertelement operation on non-vector type!");
-  assert(Elt->getType() == cast<VectorType>(Val->getType())->getElementType() &&
-         "Insertelement types must match!");
+
+  if (Val->getType()->getVectorIsSubword()) {
+    // Subword vectors allow integer value or vector element type.
+    if (!Elt->getType()->isIntegerTy() &&
+        Elt->getType() != cast<SubwordVectorType>(Val->getType())->getElementType())
+      return nullptr;
+  } else {
+
+    assert((Elt->getType() == cast<VectorType>(Val->getType())->getElementType()) &&
+           "Insertelement types must match!");
+  }
   assert(Idx->getType()->isIntegerTy() &&
          "Insertelement index must be i32 type!");
 
diff --git a/llvm/lib/IR/Core.cpp b/llvm/lib/IR/Core.cpp
index 8a7060c148c9..36dc1aefbe18 100644
--- a/llvm/lib/IR/Core.cpp
+++ b/llvm/lib/IR/Core.cpp
@@ -532,6 +532,8 @@ LLVMTypeKind LLVMGetTypeKind(LLVMTypeRef Ty) {
     return LLVMTokenTypeKind;
   case Type::ScalableVectorTyID:
     return LLVMScalableVectorTypeKind;
+  case Type::SubwordVectorTyID:
+    return LLVMSubwordVectorTypeKind;
   }
   llvm_unreachable("Unhandled TypeID.");
 }
diff --git a/llvm/lib/IR/DIBuilder.cpp b/llvm/lib/IR/DIBuilder.cpp
index 61d3b5e69e9e..d49ea828f2e3 100644
--- a/llvm/lib/IR/DIBuilder.cpp
+++ b/llvm/lib/IR/DIBuilder.cpp
@@ -574,6 +574,21 @@ DICompositeType *DIBuilder::createVectorType(uint64_t Size,
   return R;
 }
 
+/* subword type is an array type with flag Subword and set strip_size */
+/* Ty = BaseType */
+/* ESize = element size */
+/* ECount = number of element */
+DICompositeType *DIBuilder::createSubwordType(uint64_t ESize, uint64_t ECount,
+                                              DIType *Ty,
+                                              DINodeArray Subscripts) {
+
+  auto *R = DICompositeType::get(VMContext, dwarf::DW_TAG_array_type, "",
+                                 nullptr, 0, nullptr, Ty, ESize*ECount, ESize, 0,
+                                 DINode::FlagSubword, Subscripts, 0, nullptr);
+  trackIfUnresolved(R);
+  return R;
+}
+
 DISubprogram *DIBuilder::createArtificialSubprogram(DISubprogram *SP) {
   auto NewSP = SP->cloneWithFlags(SP->getFlags() | DINode::FlagArtificial);
   return MDNode::replaceWithDistinct(std::move(NewSP));
diff --git a/llvm/lib/IR/DataLayout.cpp b/llvm/lib/IR/DataLayout.cpp
index ecd74449dc38..7b626aa43ab8 100644
--- a/llvm/lib/IR/DataLayout.cpp
+++ b/llvm/lib/IR/DataLayout.cpp
@@ -791,6 +791,7 @@ Align DataLayout::getAlignment(Type *Ty, bool abi_or_pref) const {
   }
   case Type::X86_MMXTyID:
   case Type::FixedVectorTyID:
+  case Type::SubwordVectorTyID:
   case Type::ScalableVectorTyID: {
     unsigned BitWidth = getTypeSizeInBits(Ty).getKnownMinSize();
     auto I = findAlignmentLowerBound(VECTOR_ALIGN, BitWidth);
diff --git a/llvm/lib/IR/Instructions.cpp b/llvm/lib/IR/Instructions.cpp
index 5b01c70dec8d..c9881aa45911 100644
--- a/llvm/lib/IR/Instructions.cpp
+++ b/llvm/lib/IR/Instructions.cpp
@@ -492,10 +492,18 @@ void CallInst::init(FunctionType *FTy, Value *Func, ArrayRef<Value *> Args,
           (FTy->isVarArg() && Args.size() > FTy->getNumParams())) &&
          "Calling a function with bad signature!");
 
-  for (unsigned i = 0; i != Args.size(); ++i)
-    assert((i >= FTy->getNumParams() ||
+  for (unsigned i = 0; i != Args.size(); ++i) {
+    // for subword types the function can has the same type or a type equal to the basic type of the subword type
+//    if (Args[i]->getType()->getVectorIsSubword()) {
+//      assert((i >= FTy->getNumParams() ||
+//            FTy->getParamType(i) == cast<SubwordVectorType>(Args[i]->getType())->getBasicType()) &&
+//           "Calling a function with a bad signature!");
+//    } else {
+      assert((i >= FTy->getNumParams() ||
             FTy->getParamType(i) == Args[i]->getType()) &&
            "Calling a function with a bad signature!");
+//    }
+  }
 #endif
 
   // Set operands in order of their index to match use-list-order
@@ -1477,9 +1485,17 @@ void StoreInst::AssertOK() {
   assert(getOperand(0) && getOperand(1) && "Both operands must be non-null!");
   assert(getOperand(1)->getType()->isPointerTy() &&
          "Ptr must have pointer type!");
-  assert(cast<PointerType>(getOperand(1)->getType())
-             ->isOpaqueOrPointeeTypeMatches(getOperand(0)->getType()) &&
-         "Ptr must be a pointer to Val type!");
+  if ((getOperand(0)->getType()->isVectorTy() && getOperand(0)->getType()->getVectorIsSubword()) ||
+      (cast<PointerType>(getOperand(1)->getType())->getElementType()->isVectorTy() &&
+       cast<PointerType>(getOperand(1)->getType())->getElementType()->getVectorIsSubword()) ) {
+
+    /* TODO : check storing subword to i32 or i32 to subword */
+
+  } else {
+    PointerType *ptp = cast<PointerType>(getOperand(1)->getType());
+    assert(ptp->isOpaqueOrPointeeTypeMatches(getOperand(0)->getType()) &&
+           "Ptr must be a pointer to Val type!");
+  }
   assert(!(isAtomic() && getAlignment() == 0) &&
          "Alignment required for atomic store");
 }
@@ -1895,13 +1911,25 @@ InsertElementInst::InsertElementInst(Value *Vec, Value *Elt, Value *Index,
 bool InsertElementInst::isValidOperands(const Value *Vec, const Value *Elt,
                                         const Value *Index) {
   if (!Vec->getType()->isVectorTy())
-    return false;   // First operand of insertelement must be vector type.
-
-  if (Elt->getType() != cast<VectorType>(Vec->getType())->getElementType())
-    return false;// Second operand of insertelement must be vector element type.
+    return false;   // First operand of insertelement must be vector type (can be subword vector type).
 
   if (!Index->getType()->isIntegerTy())
     return false;  // Third operand of insertelement must be i32.
+
+  if (isa<SubwordVectorType>(Vec->getType())) {
+    SubwordVectorType *subVec = cast<SubwordVectorType>(Vec->getType());
+    // Subword vectors allow integer value or vector element type.
+    if (Elt->getType()->isIntegerTy()) return true;
+    if (isa<SubwordVectorType>(Elt->getType())) {
+      SubwordVectorType *subElt = cast<SubwordVectorType>(Elt->getType());
+      if (subVec->getElementType()->getPrimitiveSizeInBits()==subElt->getElementType()->getPrimitiveSizeInBits() && subElt->getNumElements()==1) return true;
+    }
+    return false;
+  } else {
+    if (Elt->getType() != cast<VectorType>(Vec->getType())->getElementType())
+      return false;// Second operand of insertelement must be vector element type.
+  }
+
   return true;
 }
 
@@ -2474,6 +2502,13 @@ BinaryOperator::BinaryOperator(BinaryOps iType, Value *S1, Value *S2,
                 OperandTraits<BinaryOperator>::op_begin(this),
                 OperandTraits<BinaryOperator>::operands(this),
                 InsertBefore) {
+  SubwordOp = false;
+  if (S1->getType()->isVectorTy() && S2->getType()->isVectorTy()) {
+    if (isa<SubwordVectorType>(S1->getType()) && isa<SubwordVectorType>(S2->getType())) {
+      SubwordOp = true;
+    }
+  }
+
   Op<0>() = S1;
   Op<1>() = S2;
   setName(Name);
@@ -2487,6 +2522,13 @@ BinaryOperator::BinaryOperator(BinaryOps iType, Value *S1, Value *S2,
                 OperandTraits<BinaryOperator>::op_begin(this),
                 OperandTraits<BinaryOperator>::operands(this),
                 InsertAtEnd) {
+  SubwordOp = false;
+  if (S1->getType()->isVectorTy() && S2->getType()->isVectorTy()) {
+    if (isa<SubwordVectorType>(S1->getType()) && isa<SubwordVectorType>(S2->getType())) {
+      SubwordOp = true;
+    }
+  }
+
   Op<0>() = S1;
   Op<1>() = S2;
   setName(Name);
@@ -2496,14 +2538,23 @@ BinaryOperator::BinaryOperator(BinaryOps iType, Value *S1, Value *S2,
 void BinaryOperator::AssertOK() {
   Value *LHS = getOperand(0), *RHS = getOperand(1);
   (void)LHS; (void)RHS; // Silence warnings.
-  assert(LHS->getType() == RHS->getType() &&
-         "Binary operator operand types must match!");
+
+  if (!SubwordOp) {  /* BinaryOperator with Subword operands allows different types */
+    assert(LHS->getType() == RHS->getType() &&
+           "Binary operator operand types must match!");
+  }
 #ifndef NDEBUG
   switch (getOpcode()) {
   case Add: case Sub:
   case Mul:
-    assert(getType() == LHS->getType() &&
-           "Arithmetic operation should return same type as operands!");
+    if (SubwordOp) {
+      // TODO: result type should be the largest one
+      assert((getType() == LHS->getType() || getType() == RHS->getType()) &&
+            "Arithmetic operation should return same type as operands!");
+    } else {
+      assert(getType() == LHS->getType() &&
+            "Arithmetic operation should return same type as operands!");
+    }
     assert(getType()->isIntOrIntVectorTy() &&
            "Tried to create an integer operation on a non-integer type!");
     break;
@@ -2564,8 +2615,39 @@ void BinaryOperator::AssertOK() {
 BinaryOperator *BinaryOperator::Create(BinaryOps Op, Value *S1, Value *S2,
                                        const Twine &Name,
                                        Instruction *InsertBefore) {
-  assert(S1->getType() == S2->getType() &&
+  // allow binary operator between two subword vectors or one subword and one normal/fixed vector for initialization
+  if (isa<SubwordVectorType>(S1->getType()) || isa<SubwordVectorType>(S2->getType())) {
+
+    if (isa<SubwordVectorType>(S1->getType()) && isa<SubwordVectorType>(S2->getType())) {    // S1 and S2 both are a subword vector
+      SubwordVectorType *subVec1 = cast<SubwordVectorType>(S1->getType());
+      SubwordVectorType *subVec2 = cast<SubwordVectorType>(S2->getType());
+
+      unsigned s1sz = subVec1->getScalarSizeInBits();
+      unsigned s2sz = subVec2->getScalarSizeInBits();
+
+      assert(subVec1->getPacking() == subVec2->getPacking() &&
+         "Cannot create binary operator when subword operands have different packing!");
+
+      Type *ResType = (s2sz>s1sz) ? S2->getType() : S1->getType();
+      return new BinaryOperator(Op, S1, S2, ResType, Name, InsertBefore);
+    }
+
+    if ((isa<SubwordVectorType>(S1->getType()) &&
+         isa<FixedVectorType>(S2->getType())) ||
+        (isa<FixedVectorType>(S1->getType()) &&
+         isa<SubwordVectorType>(S2->getType()))) { // S2 is a (fixed) vector but is not a subword vector (but S1 is a subword vector)
+      assert( (cast<VectorType>(S1->getType()))->getElementType() ==
+              (cast<VectorType>(S2->getType()))->getElementType() &&
+              (cast<VectorType>(S1->getType()))->getElementCount() ==
+              (cast<VectorType>(S2->getType()))->getElementCount() &&
+              "Cannot create binary operator with two differing vectors!");
+    }
+
+  } else {
+    assert(S1->getType() == S2->getType() &&
          "Cannot create binary operator with two operands of differing type!");
+  }
+
   return new BinaryOperator(Op, S1, S2, S1->getType(), Name, InsertBefore);
 }
 
@@ -3368,6 +3450,11 @@ CastInst::castIsValid(Instruction::CastOps op, Type *SrcTy, Type *DstTy) {
   ElementCount DstEC = DstIsVec ? cast<VectorType>(DstTy)->getElementCount()
                                 : ElementCount::getFixed(0);
 
+  unsigned SrcSubwordLength = isa<SubwordVectorType>(SrcTy) ?
+    cast<SubwordVectorType>(SrcTy)->getPacking() : 100;
+  unsigned DstSubwordLength = isa<SubwordVectorType>(DstTy) ?
+    cast<SubwordVectorType>(DstTy)->getPacking() : 100;
+
   // Switch on the opcode provided
   switch (op) {
   default: return false; // This is an input error
@@ -3413,8 +3500,15 @@ CastInst::castIsValid(Instruction::CastOps op, Type *SrcTy, Type *DstTy) {
 
     // For non-pointer cases, the cast is okay if the source and destination bit
     // widths are identical.
-    if (!SrcPtrTy)
+    if (!SrcPtrTy) {
+      if (isa<SubwordVectorType>(SrcTy) && !isa<SubwordVectorType>(DstTy)) { // source is a subword, destination is not
+        return (DstTy->getScalarSizeInBits() == cast<SubwordVectorType>(SrcTy)->getBasicType()->getScalarSizeInBits());
+      }
+      if (isa<SubwordVectorType>(DstTy) && !isa<SubwordVectorType>(SrcTy)) { // destination is a subword, source is not
+        return (SrcTy->getScalarSizeInBits() == cast<SubwordVectorType>(DstTy)->getBasicType()->getScalarSizeInBits());
+      }
       return SrcTy->getPrimitiveSizeInBits() == DstTy->getPrimitiveSizeInBits();
+    }
 
     // If both are pointers then the address spaces must match.
     if (SrcPtrTy->getAddressSpace() != DstPtrTy->getAddressSpace())
diff --git a/llvm/lib/IR/Type.cpp b/llvm/lib/IR/Type.cpp
index a21998976066..6c9558e2c922 100644
--- a/llvm/lib/IR/Type.cpp
+++ b/llvm/lib/IR/Type.cpp
@@ -146,6 +146,11 @@ TypeSize Type::getPrimitiveSizeInBits() const {
     assert(!ETS.isScalable() && "Vector type should have fixed-width elements");
     return {ETS.getFixedSize() * EC.getKnownMinValue(), EC.isScalable()};
   }
+  case Type::SubwordVectorTyID: {
+    const SubwordVectorType *SubVTy = cast<SubwordVectorType>(this);
+    unsigned wsz = SubVTy->getElementType()->getScalarSizeInBits();
+      return TypeSize::Fixed(wsz); /* return always size of the basic type */
+  }
   default: return TypeSize::Fixed(0);
   }
 }
@@ -176,6 +181,9 @@ bool Type::isSizedDerivedType(SmallPtrSetImpl<Type*> *Visited) const {
   if (auto *VTy = dyn_cast<VectorType>(this))
     return VTy->getElementType()->isSized(Visited);
 
+  if (auto *STy = dyn_cast<SubwordVectorType>(this))
+    return STy->getBasicType()->isSized(Visited);
+
   return cast<StructType>(this)->isSized(Visited);
 }
 
@@ -643,6 +651,13 @@ bool VectorType::isValidElementType(Type *ElemTy) {
          ElemTy->isPointerTy();
 }
 
+/* subword specific VectorType - array of Subwords */
+VectorType *VectorType::get(Type *ElementType, unsigned NumElms,
+                            Type *BasicType, unsigned PckSz, bool Sign) {
+  return SubwordVectorType::get(ElementType, NumElms, BasicType, PckSz, Sign);
+}
+
+
 //===----------------------------------------------------------------------===//
 //                        FixedVectorType Implementation
 //===----------------------------------------------------------------------===//
@@ -686,6 +701,24 @@ ScalableVectorType *ScalableVectorType::get(Type *ElementType,
   return cast<ScalableVectorType>(Entry);
 }
 
+//===----------------------------------------------------------------------===//
+//                       SubwordVectorType Implementation
+//===----------------------------------------------------------------------===//
+SubwordVectorType *SubwordVectorType::get(Type *ElementType, unsigned NumElms,
+                                          Type *BasicType, unsigned PckSz,
+                                          bool Sign) {
+  assert(isa<IntegerType>(ElementType) && isa<IntegerType>(BasicType) &&
+         "Both Basic Element types must be an integer type.");
+  /* use maximal packing if PckSz==0 */
+  if (PckSz==0) {
+    PckSz = cast<IntegerType>(BasicType)->getBitWidth() / cast<IntegerType>(ElementType)->getBitWidth();
+  }
+  LLVMContextImpl *pImpl = ElementType->getContext().pImpl;
+  SubwordVectorType *Entry = new (pImpl->Alloc) SubwordVectorType(ElementType,
+                                              NumElms, BasicType, PckSz, Sign);
+  return cast<SubwordVectorType>(Entry);
+}
+
 //===----------------------------------------------------------------------===//
 //                         PointerType Implementation
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index 758205a39eb3..69760746bdfb 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -3054,10 +3054,17 @@ void Verifier::visitCallBase(CallBase &Call) {
            "Incorrect number of arguments passed to called function!", Call);
 
   // Verify that all arguments to the call match the function type.
-  for (unsigned i = 0, e = FTy->getNumParams(); i != e; ++i)
-    Assert(Call.getArgOperand(i)->getType() == FTy->getParamType(i),
+  for (unsigned i = 0, e = FTy->getNumParams(); i != e; ++i) {
+//    if (isa<SubwordVectorType>(Call.getArgOperand(i)->getType())) {
+//      SubwordVectorType *vty = cast<SubwordVectorType>(Call.getArgOperand(i)->getType());
+//      Assert(vty->getBasicType() == FTy->getParamType(i),
+//             "Call parameter type does not match function signature!",
+//            Call.getArgOperand(i), FTy->getParamType(i), Call);
+//    } else
+      Assert(Call.getArgOperand(i)->getType() == FTy->getParamType(i),
            "Call parameter type does not match function signature!",
            Call.getArgOperand(i), FTy->getParamType(i), Call);
+  }
 
   AttributeList Attrs = Call.getAttributes();
 
@@ -3471,8 +3478,10 @@ void Verifier::visitUnaryOperator(UnaryOperator &U) {
 /// of the same type!
 ///
 void Verifier::visitBinaryOperator(BinaryOperator &B) {
-  Assert(B.getOperand(0)->getType() == B.getOperand(1)->getType(),
-         "Both operands to a binary operator are not of the same type!", &B);
+  if (!B.isSubwordOp()) {
+    Assert(B.getOperand(0)->getType() == B.getOperand(1)->getType(),
+           "Both operands to a binary operator are not of the same type!", &B);
+  }
 
   switch (B.getOpcode()) {
   // Check that integer arithmetic operators are only used with
@@ -3486,10 +3495,17 @@ void Verifier::visitBinaryOperator(BinaryOperator &B) {
   case Instruction::URem:
     Assert(B.getType()->isIntOrIntVectorTy(),
            "Integer arithmetic operators only work with integral types!", &B);
-    Assert(B.getType() == B.getOperand(0)->getType(),
-           "Integer arithmetic operators must have same type "
-           "for operands and result!",
-           &B);
+    if (B.isSubwordOp()) {
+      Assert(B.getType() == B.getOperand(0)->getType() || B.getType() == B.getOperand(1)->getType(),
+             "Integer (subword) arithmetic operators must have same type "
+             "for result and one of operands!",
+             &B);
+    } else {
+      Assert(B.getType() == B.getOperand(0)->getType(),
+             "Integer arithmetic operators must have same type "
+             "for operands and result!",
+             &B);
+    }
     break;
   // Check that floating-point arithmetic operators are only used with
   // floating-point operands.
@@ -3536,11 +3552,13 @@ void Verifier::visitICmpInst(ICmpInst &IC) {
   // Check that the operands are the same type
   Type *Op0Ty = IC.getOperand(0)->getType();
   Type *Op1Ty = IC.getOperand(1)->getType();
-  Assert(Op0Ty == Op1Ty,
-         "Both operands to ICmp instruction are not of the same type!", &IC);
+  //Assert(Op0Ty == Op1Ty,
+         //"Both operands to ICmp instruction are not of the same type!", &IC);
   // Check that the operands are the right type
   Assert(Op0Ty->isIntOrIntVectorTy() || Op0Ty->isPtrOrPtrVectorTy(),
          "Invalid operand types for ICmp instruction", &IC);
+  Assert(Op1Ty->isIntOrIntVectorTy() || Op1Ty->isPtrOrPtrVectorTy(),
+         "Invalid second operand types for ICmp instruction", &IC);
   // Check that the predicate is valid.
   Assert(IC.isIntPredicate(),
          "Invalid predicate in ICmp instruction!", &IC);
@@ -3720,8 +3738,29 @@ void Verifier::visitStoreInst(StoreInst &SI) {
   PointerType *PTy = dyn_cast<PointerType>(SI.getOperand(1)->getType());
   Assert(PTy, "Store operand must be a pointer.", &SI);
   Type *ElTy = SI.getOperand(0)->getType();
-  Assert(PTy->isOpaqueOrPointeeTypeMatches(ElTy),
+
+  if (isa<SubwordVectorType>(PTy->getElementType())) {
+    SubwordVectorType *pvt = cast<SubwordVectorType>(PTy->getElementType());
+
+    if (isa<SubwordVectorType>(ElTy)) { // both are subwords
+      Assert(ElTy == pvt,
+        "Stored value does not match pointer operand subword type!", pvt, ElTy);
+    } else {
+      Assert(ElTy == pvt->getBasicType(),
+        "Stored value does not match pointer operand subword basic type!", pvt->getBasicType(), ElTy);
+    }
+
+  } else if (isa<SubwordVectorType>(ElTy)) { // destination is a subword but source is not
+    SubwordVectorType *pvt = cast<SubwordVectorType>(ElTy);
+    Assert(pvt->getBasicType() == SI.getOperand(0)->getType(),
+      "Stored value does not match pointer operand subword basic type!", pvt->getBasicType(), SI.getOperand(0)->getType());
+
+  } else {
+//    Assert(ElTy == SI.getOperand(0)->getType(),
+     Assert(PTy->isOpaqueOrPointeeTypeMatches(ElTy),
          "Stored value type does not match pointer operand type!", &SI, ElTy);
+  }
+
   Assert(SI.getAlignment() <= Value::MaximumAlignment,
          "huge alignment values are unsupported", &SI);
   Assert(ElTy->isSized(), "storing unsized types is not allowed", &SI);
diff --git a/llvm/lib/Linker/IRMover.cpp b/llvm/lib/Linker/IRMover.cpp
index 7bc6f0585921..c444065f271e 100644
--- a/llvm/lib/Linker/IRMover.cpp
+++ b/llvm/lib/Linker/IRMover.cpp
@@ -300,6 +300,7 @@ Type *TypeMapTy::get(Type *Ty, SmallPtrSet<StructType *, 8> &Visited) {
                                    cast<ArrayType>(Ty)->getNumElements());
   case Type::ScalableVectorTyID:
   case Type::FixedVectorTyID:
+  case Type::SubwordVectorTyID: /* TODO: check if it has correct behaviour for the subword type */
     return *Entry = VectorType::get(ElementTypes[0],
                                     cast<VectorType>(Ty)->getElementCount());
   case Type::PointerTyID:
diff --git a/llvm/lib/Support/Triple.cpp b/llvm/lib/Support/Triple.cpp
index 88311546354b..98f830fd467d 100644
--- a/llvm/lib/Support/Triple.cpp
+++ b/llvm/lib/Support/Triple.cpp
@@ -176,6 +176,7 @@ StringRef Triple::getVendorTypeName(VendorType Kind) {
   case Myriad: return "myriad";
   case NVIDIA: return "nvidia";
   case OpenEmbedded: return "oe";
+  case Daiteq: return "daiteq";
   case PC: return "pc";
   case SCEI: return "scei";
   case SUSE: return "suse";
@@ -497,6 +498,7 @@ static Triple::VendorType parseVendor(StringRef VendorName) {
     .Case("mesa", Triple::Mesa)
     .Case("suse", Triple::SUSE)
     .Case("oe", Triple::OpenEmbedded)
+    .Case("daiteq", Triple::Daiteq)
     .Default(Triple::UnknownVendor);
 }
 
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 87496e0b9330..980f6bacd329 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -901,6 +901,16 @@ static MCRegister convertFPR64ToFPR32(MCRegister Reg) {
   return Reg - RISCV::F0_D + RISCV::F0_F;
 }
 
+static MCRegister convertFPR64ToFPR16V2(MCRegister Reg) {
+  assert(Reg >= RISCV::F0_D && Reg <= RISCV::F31_D && "Invalid register");
+  return Reg - RISCV::F0_D + RISCV::F0_PH;
+}
+
+static MCRegister convertFPR64ToFPR32V2(MCRegister Reg) {
+  assert(Reg >= RISCV::F0_D && Reg <= RISCV::F31_D && "Invalid register");
+  return Reg - RISCV::F0_D + RISCV::F0_PS;
+}
+
 static MCRegister convertVRToVRMx(const MCRegisterInfo &RI, MCRegister Reg,
                                   unsigned Kind) {
   unsigned RegClassID;
@@ -942,6 +952,17 @@ unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
     Op.Reg.RegNum = convertFPR64ToFPR16(Reg);
     return Match_Success;
   }
+
+  if (IsRegFPR64 && Kind == MCK_FPR16V2) {
+    Op.Reg.RegNum = convertFPR64ToFPR16V2(Reg);
+    return Match_Success;
+  }
+
+  if (IsRegFPR64 && Kind == MCK_FPR32V2) {
+    Op.Reg.RegNum = convertFPR64ToFPR32V2(Reg);
+    return Match_Success;
+  }
+
   // As the parser couldn't differentiate an VRM2/VRM4/VRM8 from an VR, coerce
   // the register from VR to VRM2/VRM4/VRM8 if necessary.
   if (IsRegVR && (Kind == MCK_VRM2 || Kind == MCK_VRM4 || Kind == MCK_VRM8)) {
@@ -2044,7 +2065,7 @@ bool RISCVAsmParser::parseDirectiveAttribute() {
     clearFeatureBits(RISCV::FeatureStdExtC, "c");
     clearFeatureBits(RISCV::FeatureStdExtB, "experimental-b");
     clearFeatureBits(RISCV::FeatureStdExtV, "experimental-v");
-    clearFeatureBits(RISCV::FeatureExtZfh, "experimental-zfh");
+    clearFeatureBits(RISCV::FeatureExtZfh, "zfh");
     clearFeatureBits(RISCV::FeatureExtZba, "experimental-zba");
     clearFeatureBits(RISCV::FeatureExtZbb, "experimental-zbb");
     clearFeatureBits(RISCV::FeatureExtZbc, "experimental-zbc");
@@ -2058,7 +2079,9 @@ bool RISCVAsmParser::parseDirectiveAttribute() {
     clearFeatureBits(RISCV::FeatureExtZbt, "experimental-zbt");
     clearFeatureBits(RISCV::FeatureExtZvamo, "experimental-zvamo");
     clearFeatureBits(RISCV::FeatureStdExtZvlsseg, "experimental-zvlsseg");
-
+    clearFeatureBits(RISCV::FeatureExtXfph, "x-fph");
+    clearFeatureBits(RISCV::FeatureExtXfps, "x-fps");
+    clearFeatureBits(RISCV::FeatureExtXswar, "x-swar");
     while (!Arch.empty()) {
       bool DropFirst = true;
       if (Arch[0] == 'i')
@@ -2113,11 +2136,17 @@ bool RISCVAsmParser::parseDirectiveAttribute() {
         else if (Ext == "zbt")
           setFeatureBits(RISCV::FeatureExtZbt, "experimental-zbt");
         else if (Ext == "zfh")
-          setFeatureBits(RISCV::FeatureExtZfh, "experimental-zfh");
+          setFeatureBits(RISCV::FeatureExtZfh, "zfh");
         else if (Ext == "zvamo")
           setFeatureBits(RISCV::FeatureExtZvamo, "experimental-zvamo");
         else if (Ext == "zvlsseg")
           setFeatureBits(RISCV::FeatureStdExtZvlsseg, "experimental-zvlsseg");
+        else if (Ext == "x-fph")
+          setFeatureBits(RISCV::FeatureExtXfph, "x-fph");
+        else if (Ext == "x-fps")
+          setFeatureBits(RISCV::FeatureExtXfps, "x-fps");
+        else if (Ext == "x-swar")
+          setFeatureBits(RISCV::FeatureExtXswar, "x-swar");
         else
           return Error(ValueExprLoc, "bad arch string " + Ext);
         Arch = Arch.drop_until([](char c) { return ::isdigit(c) || c == '_'; });
@@ -2165,7 +2194,7 @@ bool RISCVAsmParser::parseDirectiveAttribute() {
       if (getFeatureBits(RISCV::FeatureStdExtV))
         formalArchStr = (Twine(formalArchStr) + "_v0p10").str();
       if (getFeatureBits(RISCV::FeatureExtZfh))
-        formalArchStr = (Twine(formalArchStr) + "_zfh0p1").str();
+        formalArchStr = (Twine(formalArchStr) + "_zfh1p0").str();
       if (getFeatureBits(RISCV::FeatureExtZba))
         formalArchStr = (Twine(formalArchStr) + "_zba0p93").str();
       if (getFeatureBits(RISCV::FeatureExtZbb))
@@ -2192,6 +2221,12 @@ bool RISCVAsmParser::parseDirectiveAttribute() {
         formalArchStr = (Twine(formalArchStr) + "_zvamo0p10").str();
       if (getFeatureBits(RISCV::FeatureStdExtZvlsseg))
         formalArchStr = (Twine(formalArchStr) + "_zvlsseg0p10").str();
+      if (getFeatureBits(RISCV::FeatureExtXfph))
+        formalArchStr = (Twine(formalArchStr) + "_x-fph1p0").str();
+      if (getFeatureBits(RISCV::FeatureExtXfps))
+        formalArchStr = (Twine(formalArchStr) + "_x-fps1p0").str();
+      if (getFeatureBits(RISCV::FeatureExtXswar))
+        formalArchStr = (Twine(formalArchStr) + "_x-swar1p0").str();
 
       getTargetStreamer().emitTextAttribute(Tag, formalArchStr);
     }
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 504a78d91f32..1a45c5a50a7c 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -75,6 +75,23 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeSWARRRegisterClass(MCInst &Inst, uint64_t RegNo,
+                                             uint64_t Address,
+                                             const void *Decoder) {
+  const FeatureBitset &FeatureBits =
+      static_cast<const MCDisassembler *>(Decoder)
+          ->getSubtargetInfo()
+          .getFeatureBits();
+  bool IsRV32E = FeatureBits[RISCV::FeatureRV32E];
+
+  if (RegNo >= 32 || (IsRV32E && RegNo >= 16))
+    return MCDisassembler::Fail;
+
+  MCRegister Reg = RISCV::X0 + RegNo;
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint64_t RegNo,
                                              uint64_t Address,
                                              const void *Decoder) {
@@ -130,6 +147,28 @@ static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint64_t RegNo,
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeFPR16V2RegisterClass(MCInst &Inst, uint64_t RegNo,
+                                               uint64_t Address,
+                                               const void *Decoder) {
+  if (RegNo >= 32)
+    return MCDisassembler::Fail;
+
+  MCRegister Reg = RISCV::F0_PH + RegNo;
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeFPR32V2RegisterClass(MCInst &Inst, uint64_t RegNo,
+                                               uint64_t Address,
+                                               const void *Decoder) {
+  if (RegNo >= 32)
+    return MCDisassembler::Fail;
+
+  MCRegister Reg = RISCV::F0_PS + RegNo;
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint64_t RegNo,
                                                uint64_t Address,
                                                const void *Decoder) {
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
index 13c4b84aa300..a491ebe62941 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -65,7 +65,7 @@ void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
   if (STI.hasFeature(RISCV::FeatureStdExtV))
     Arch += "_v0p10";
   if (STI.hasFeature(RISCV::FeatureExtZfh))
-    Arch += "_zfh0p1";
+    Arch += "_zfh1p0";
   if (STI.hasFeature(RISCV::FeatureExtZba))
     Arch += "_zba0p93";
   if (STI.hasFeature(RISCV::FeatureExtZbb))
@@ -93,6 +93,13 @@ void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
   if (STI.hasFeature(RISCV::FeatureStdExtZvlsseg))
     Arch += "_zvlsseg0p10";
 
+  if (STI.hasFeature(RISCV::FeatureExtXfph))
+    Arch += "_x-fph1p0";
+  if (STI.hasFeature(RISCV::FeatureExtXfps))
+    Arch += "_x-fps1p0";
+  if (STI.hasFeature(RISCV::FeatureExtXswar))
+    Arch += "_x-swar1p0";
+
   emitTextAttribute(RISCVAttrs::ARCH, Arch);
 }
 
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 52e8d8cdc774..8b357a76d051 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -35,20 +35,43 @@ def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
 
 def FeatureStdExtD
     : SubtargetFeature<"d", "HasStdExtD", "true",
-                       "'D' (Double-Precision Floating-Point)",
-                       [FeatureStdExtF]>;
+                       "'D' (Double-Precision Floating-Point)">; //, [FeatureStdExtF]>; /* do not enable F extension automatically */
 def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
                            AssemblerPredicate<(all_of FeatureStdExtD),
                            "'D' (Double-Precision Floating-Point)">;
 
 def FeatureExtZfh
-    : SubtargetFeature<"experimental-zfh", "HasStdExtZfh", "true",
-                       "'Zfh' (Half-Precision Floating-Point)",
-                       [FeatureStdExtF]>;
+    : SubtargetFeature<"zfh", "HasStdExtZfh", "true",
+                       "'Zfh' (Half-Precision Floating-Point)">; //, [FeatureStdExtF]>; /* do not enable F extension automatically */
 def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
                              AssemblerPredicate<(all_of FeatureExtZfh),
                              "'Zfh' (Half-Precision Floating-Point)">;
 
+def FeatureExtXfph
+    : SubtargetFeature<"x-fph", "HasDaiExtXfph", "true",
+                       "'x-fph' (Packed Half-Precision Floating-Point)", [FeatureExtZfh]>;
+def HasDaiExtXfph : Predicate<"Subtarget->hasDaiExtXfph()">,
+                             AssemblerPredicate<(all_of FeatureExtXfph),
+                             "'x-fph' (Packed Half-Precision Floating-Point)">;
+
+def FeatureExtXfps
+    : SubtargetFeature<"x-fps", "HasDaiExtXfps", "true",
+                       "'x-fps' (Packed Single-Precision Floating-Point)",[FeatureStdExtF]>;
+def HasDaiExtXfps : Predicate<"Subtarget->hasDaiExtXfps()">,
+                             AssemblerPredicate<(all_of FeatureExtXfps),
+                             "'x-fps' (Packed Single-Precision Floating-Point)">;
+
+def HasStdExtDorXfps : Predicate<"Subtarget->hasStdExtD() || Subtarget->hasDaiExtXfps()">,
+                                 AssemblerPredicate<(any_of FeatureStdExtD, FeatureExtXfps),
+                           "'D' (Double-Precision Floating-Point) or 'x-fps' (Packed Single-Precision Floating-Point)">;
+
+def FeatureExtXswar
+    : SubtargetFeature<"x-swar", "HasDaiExtXswar", "true",
+                       "'x-swar' (daiteq SWAR)">;
+def HasDaiExtXswar : Predicate<"Subtarget->hasDaiExtXswar()">,
+                             AssemblerPredicate<(all_of FeatureExtXswar),
+                             "'x-swar' (daiteq SWAR)">;
+
 def FeatureStdExtC
     : SubtargetFeature<"c", "HasStdExtC", "true",
                        "'C' (Compressed Instructions)">;
@@ -219,6 +242,147 @@ foreach i = {1-31} in
 def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore",
                                           "true", "Enable save/restore.">;
 
+
+//def FeatureSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
+//                              "Use software emulation for floating point">;
+
+def FeatureSoftFADDHalf : SubtargetFeature<"soft-fops-half-fadd", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_ADD]", "true",
+           "Use software emulation for FADDh">;
+def NotSoftFADDHalf : Predicate<"!Subtarget->isSoftFPHalf(llvm::SoftFops::SOFTFP_ADD)">;
+def FeatureSoftFSUBHalf : SubtargetFeature<"soft-fops-half-fsub", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_SUB]", "true",
+           "Use software emulation for FSUBh">;
+def NotSoftFSUBHalf : Predicate<"!Subtarget->isSoftFPHalf(llvm::SoftFops::SOFTFP_SUB)">;
+def FeatureSoftFMULHalf : SubtargetFeature<"soft-fops-half-fmul", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_MUL]", "true",
+           "Use software emulation for FMULh">;
+def NotSoftFMULHalf : Predicate<"!Subtarget->isSoftFPHalf(llvm::SoftFops::SOFTFP_MUL)">;
+def FeatureSoftFDIVHalf : SubtargetFeature<"soft-fops-half-fdiv", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_DIV]", "true",
+           "Use software emulation for FDIVh">;
+def NotSoftFDIVHalf : Predicate<"!Subtarget->isSoftFPHalf(llvm::SoftFops::SOFTFP_DIV)">;
+def FeatureSoftFMULEXHalf : SubtargetFeature<"soft-fops-half-fmulex", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_MULEX]", "true",
+           "Use software emulation for FHMULS">;
+def NotSoftFMULEXHalf : Predicate<"!Subtarget->isSoftFPHalf(llvm::SoftFops::SOFTFP_MULEX)">;
+def FeatureSoftFSQRTHalf : SubtargetFeature<"soft-fops-half-fsqrt", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_SQRT]", "true",
+           "Use software emulation for FSQRTh">;
+def NotSoftFSQRTHalf : Predicate<"!Subtarget->isSoftFPHalf(llvm::SoftFops::SOFTFP_SQRT)">;
+def FeatureSoftFCMPHalf : SubtargetFeature<"soft-fops-half-fcmp", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_CMP]", "true",
+           "Use software emulation for FCMPh, FCMPEh">;
+def NotSoftFCMPHalf : Predicate<"!Subtarget->isSoftFPHalf(llvm::SoftFops::SOFTFP_CMP)">;
+def FeatureSoftFCI2FHalf : SubtargetFeature<"soft-fops-half-fci2f", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_CI2F]", "true",
+           "Use software emulation for FITOH">;
+def NotSoftFCI2FHalf : Predicate<"!Subtarget->isSoftFPHalf(llvm::SoftFops::SOFTFP_CI2F)">;
+def FeatureSoftFCF2IHalf : SubtargetFeature<"soft-fops-half-fcf2i", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_CF2I]", "true",
+           "Use software emulation for FHTOI">;
+def NotSoftFCF2IHalf : Predicate<"!Subtarget->isSoftFPHalf(llvm::SoftFops::SOFTFP_CF2I)">;
+def FeatureSoftFCFUPHalf : SubtargetFeature<"soft-fops-half-fcfup", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_CFUP]", "true",
+           "Use software emulation for FHTOS">;
+def NotSoftFCFUPHalf : Predicate<"!Subtarget->isSoftFPHalf(llvm::SoftFops::SOFTFP_CFUP)">;
+def FeatureSoftFCFDNHalf : SubtargetFeature<"soft-fops-half-fcfdn", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_CFDN]", "true",
+           "Use software emulation for FHTOS">;
+def NotSoftFCFDNHalf : Predicate<"!Subtarget->isSoftFPHalf(llvm::SoftFops::SOFTFP_CFDN)">;
+def FeatureSoftFABSHalf : SubtargetFeature<"soft-fops-half-fabs", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_ABS]", "true",
+           "Use software emulation for FABSh">;
+def NotSoftFABSHalf : Predicate<"!Subtarget->isSoftFPHalf(llvm::SoftFops::SOFTFP_ABS)">;
+def FeatureSoftFMOVHalf : SubtargetFeature<"soft-fops-half-fmov", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_MOV]", "true",
+           "Use software emulation for FMOVh">;
+def NotSoftFMOVHalf : Predicate<"!Subtarget->isSoftFPHalf(llvm::SoftFops::SOFTFP_MOV)">;
+def FeatureSoftFNEGHalf : SubtargetFeature<"soft-fops-half-fneg", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_NEG]", "true",
+           "Use software emulation for FNEGh">;
+def NotSoftFNEGHalf : Predicate<"!Subtarget->isSoftFPHalf(llvm::SoftFops::SOFTFP_NEG)">;
+
+def FeatureSoftFADDSingle : SubtargetFeature<"soft-fops-single-fadd", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_ADD]", "true",
+           "Use software emulation for FADDs">;
+def NotSoftFADDSingle : Predicate<"!Subtarget->isSoftFPSingle(llvm::SoftFops::SOFTFP_ADD)">;
+def FeatureSoftFSUBSingle : SubtargetFeature<"soft-fops-single-fsub", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_SUB]", "true",
+           "Use software emulation for FSUBs">;
+def NotSoftFSUBSingle : Predicate<"!Subtarget->isSoftFPSingle(llvm::SoftFops::SOFTFP_SUB)">;
+def FeatureSoftFMULSingle : SubtargetFeature<"soft-fops-single-fmul", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_MUL]", "true",
+           "Use software emulation for FMULs">;
+def NotSoftFMULSingle : Predicate<"!Subtarget->isSoftFPSingle(llvm::SoftFops::SOFTFP_MUL)">;
+def FeatureSoftFDIVSingle : SubtargetFeature<"soft-fops-single-fdiv", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_DIV]", "true",
+           "Use software emulation for FDIVs">;
+def NotSoftFDIVSingle : Predicate<"!Subtarget->isSoftFPSingle(llvm::SoftFops::SOFTFP_DIV)">;
+def FeatureSoftFMULEXSingle : SubtargetFeature<"soft-fops-single-fmulex", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_MULEX]", "true",
+           "Use software emulation for FSMULD">;
+def NotSoftFMULEXSingle : Predicate<"!Subtarget->isSoftFPSingle(llvm::SoftFops::SOFTFP_MULEX)">;
+def FeatureSoftFSQRTSingle : SubtargetFeature<"soft-fops-single-fsqrt", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_SQRT]", "true",
+           "Use software emulation for FSQRTs">;
+def NotSoftFSQRTSingle : Predicate<"!Subtarget->isSoftFPSingle(llvm::SoftFops::SOFTFP_SQRT)">;
+def FeatureSoftFCMPSingle : SubtargetFeature<"soft-fops-single-fcmp", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_CMP]", "true",
+           "Use software emulation for FCMPs, FCMPEs">;
+def NotSoftFCMPSingle : Predicate<"!Subtarget->isSoftFPSingle(llvm::SoftFops::SOFTFP_CMP)">;
+def FeatureSoftFCI2FSingle : SubtargetFeature<"soft-fops-single-fci2f", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_CI2F]", "true",
+           "Use software emulation for FITOS">;
+def NotSoftFCI2FSingle : Predicate<"!Subtarget->isSoftFPSingle(llvm::SoftFops::SOFTFP_CI2F)">;
+def FeatureSoftFCF2ISingle : SubtargetFeature<"soft-fops-single-fcf2i", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_CF2I]", "true",
+           "Use software emulation for FSTOI">;
+def NotSoftFCF2ISingle : Predicate<"!Subtarget->isSoftFPSingle(llvm::SoftFops::SOFTFP_CF2I)">;
+def FeatureSoftFCFUPSingle : SubtargetFeature<"soft-fops-single-fcfup", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_CFUP]", "true",
+           "Use software emulation for FSTOD">;
+def NotSoftFCFUPSingle : Predicate<"!Subtarget->isSoftFPSingle(llvm::SoftFops::SOFTFP_CFUP)">;
+def FeatureSoftFCFDNSingle : SubtargetFeature<"soft-fops-single-fcfdn", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_CFDN]", "true",
+           "Use software emulation for FSTOH">;
+def NotSoftFCFDNSingle : Predicate<"!Subtarget->isSoftFPSingle(llvm::SoftFops::SOFTFP_CFDN)">;
+def FeatureSoftFABSSingle : SubtargetFeature<"soft-fops-single-fabs", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_ABS]", "true",
+           "Use software emulation for FABSs">;
+def NotSoftFABSSingle : Predicate<"!Subtarget->isSoftFPSingle(llvm::SoftFops::SOFTFP_ABS)">;
+def FeatureSoftFMOVSingle : SubtargetFeature<"soft-fops-single-fmov", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_MOV]", "true",
+           "Use software emulation for FMOVs">;
+def NotSoftFMOVSingle : Predicate<"!Subtarget->isSoftFPSingle(llvm::SoftFops::SOFTFP_MOV)">;
+def FeatureSoftFNEGSingle : SubtargetFeature<"soft-fops-single-fneg", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_NEG]", "true",
+           "Use software emulation for FNEGs">;
+def NotSoftFNEGSingle : Predicate<"!Subtarget->isSoftFPSingle(llvm::SoftFops::SOFTFP_NEG)">;
+
+def FeatureSoftFADDDouble : SubtargetFeature<"soft-fops-double-fadd", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_ADD]", "true",
+           "Use software emulation for FADDd">;
+def NotSoftFADDDouble : Predicate<"!Subtarget->isSoftFPDouble(llvm::SoftFops::SOFTFP_ADD)">;
+def FeatureSoftFSUBDouble : SubtargetFeature<"soft-fops-double-fsub", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_SUB]", "true",
+           "Use software emulation for FSUBd">;
+def NotSoftFSUBDouble : Predicate<"!Subtarget->isSoftFPDouble(llvm::SoftFops::SOFTFP_SUB)">;
+def FeatureSoftFMULDouble : SubtargetFeature<"soft-fops-double-fmul", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_MUL]", "true",
+           "Use software emulation for FMULd">;
+def NotSoftFMULDouble : Predicate<"!Subtarget->isSoftFPDouble(llvm::SoftFops::SOFTFP_MUL)">;
+def FeatureSoftFDIVDouble : SubtargetFeature<"soft-fops-double-fdiv", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_DIV]", "true",
+           "Use software emulation for FDIVd">;
+def NotSoftFDIVDouble : Predicate<"!Subtarget->isSoftFPDouble(llvm::SoftFops::SOFTFP_DIV)">;
+def FeatureSoftFMULEXDouble : SubtargetFeature<"soft-fops-double-fmulex", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_MULEX]", "true",
+           "Use software emulation for FDMULQ">;
+def NotSoftFMULEXDouble : Predicate<"!Subtarget->isSoftFPDouble(llvm::SoftFops::SOFTFP_MULEX)">;
+def FeatureSoftFSQRTDouble : SubtargetFeature<"soft-fops-double-fsqrt", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_SQRT]", "true",
+           "Use software emulation for FSQRTd">;
+def NotSoftFSQRTDouble : Predicate<"!Subtarget->isSoftFPDouble(llvm::SoftFops::SOFTFP_SQRT)">;
+def FeatureSoftFCMPDouble : SubtargetFeature<"soft-fops-double-fcmp", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_CMP]", "true",
+           "Use software emulation for FCMPd, FCMPEd">;
+def NotSoftFCMPDouble : Predicate<"!Subtarget->isSoftFPDouble(llvm::SoftFops::SOFTFP_CMP)">;
+def FeatureSoftFCI2FDouble : SubtargetFeature<"soft-fops-double-fci2f", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_CI2F]", "true",
+           "Use software emulation for FITOD">;
+def NotSoftFCI2FDouble : Predicate<"!Subtarget->isSoftFPDouble(llvm::SoftFops::SOFTFP_CI2F)">;
+def FeatureSoftFCF2IDouble : SubtargetFeature<"soft-fops-double-fcf2i", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_CF2I]", "true",
+           "Use software emulation for FDTOI">;
+def NotSoftFCF2IDouble : Predicate<"!Subtarget->isSoftFPDouble(llvm::SoftFops::SOFTFP_CF2I)">;
+def FeatureSoftFCFUPDouble : SubtargetFeature<"soft-fops-double-fcfup", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_CFUP]", "true",
+           "Use software emulation for FDTOQ">;
+def FeatureSoftFCFDNDouble : SubtargetFeature<"soft-fops-double-fcfdn", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_CFDN]", "true",
+           "Use software emulation for FDTOS">;
+def FeatureSoftFABSDouble : SubtargetFeature<"soft-fops-double-fabs", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_ABS]", "true",
+           "Use software emulation for FABSd">;
+def FeatureSoftFMOVDouble : SubtargetFeature<"soft-fops-double-fmov", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_MOV]", "true",
+           "Use software emulation for FMOVd">;
+def FeatureSoftFNEGDouble : SubtargetFeature<"soft-fops-double-fneg", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_NEG]", "true",
+           "Use software emulation for FNEGd">;
+
+//def FeaturePackedHalf : SubtargetFeature<"enable-packedhalf", "UseFPPackedHalf", "true",
+//           "Use packed half FP type">;
+//def FeaturePackedSingle : SubtargetFeature<"enable-packedsingle", "UseFPPackedSingle", "true",
+//           "Use packed single FP type">;
+
+
+def HasStdExtFOrDOrZfh
+    : Predicate<"Subtarget->hasStdExtF() || Subtarget->hasStdExtD() || Subtarget->hasStdExtZfh()">,
+                AssemblerPredicate<(any_of FeatureStdExtF, FeatureStdExtD, FeatureExtZfh),
+                                   "'F' (Single FP Instructions) or "
+                                   "'D' (Double FP Instructions) or "
+                                   "'Zfh' (Half FP Instructions)">;
+
 //===----------------------------------------------------------------------===//
 // Named operands for CSR instructions.
 //===----------------------------------------------------------------------===//
@@ -236,6 +400,7 @@ include "RISCVInstrInfo.td"
 include "RISCVRegisterBanks.td"
 include "RISCVSchedRocket.td"
 include "RISCVSchedSiFive7.td"
+include "RISCVSchedDaiteq.td"
 
 //===----------------------------------------------------------------------===//
 // RISC-V processors supported.
@@ -244,6 +409,8 @@ include "RISCVSchedSiFive7.td"
 def : ProcessorModel<"generic-rv32", NoSchedModel, []>;
 def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
 
+def : ProcessorModel<"daiteq-rv64", DaiteqModel, [Feature64Bit]>;
+
 def : ProcessorModel<"rocket-rv32", RocketModel, []>;
 def : ProcessorModel<"rocket-rv64", RocketModel, [Feature64Bit]>;
 
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index bdf30f8eb1b3..a3c422483ef9 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -39,11 +39,13 @@ STATISTIC(RISCVNumInstrsCompressed,
 namespace {
 class RISCVAsmPrinter : public AsmPrinter {
   const MCSubtargetInfo *STI;
+  bool attrsPrinted;
 
 public:
   explicit RISCVAsmPrinter(TargetMachine &TM,
                            std::unique_ptr<MCStreamer> Streamer)
-      : AsmPrinter(TM, std::move(Streamer)), STI(TM.getMCSubtargetInfo()) {}
+      : AsmPrinter(TM, std::move(Streamer)), STI(TM.getMCSubtargetInfo()),
+        attrsPrinted(false) {}
 
   StringRef getPassName() const override { return "RISCV Assembly Printer"; }
 
@@ -171,6 +173,11 @@ bool RISCVAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
     OutStreamer->getContext().getSubtargetCopy(*TM.getMCSubtargetInfo());
   NewSTI.setFeatureBits(MF.getSubtarget().getFeatureBits());
   STI = &NewSTI;
+  if (!attrsPrinted) {
+    if (TM.getTargetTriple().isOSBinFormatELF())
+      emitAttributes();
+    attrsPrinted = true;
+  }
 
   SetupMachineFunction(MF);
   emitFunctionBody();
@@ -178,8 +185,8 @@ bool RISCVAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
 }
 
 void RISCVAsmPrinter::emitStartOfAsmFile(Module &M) {
-  if (TM.getTargetTriple().isOSBinFormatELF())
-    emitAttributes();
+//  if (TM.getTargetTriple().isOSBinFormatELF())
+//    emitAttributes();
 }
 
 void RISCVAsmPrinter::emitEndOfAsmFile(Module &M) {
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 294532011650..3f71b2dbaa33 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -90,6 +90,32 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   if (Subtarget.hasStdExtD())
     addRegisterClass(MVT::f64, &RISCV::FPR64RegClass);
 
+  if (Subtarget.hasDaiExtXfph()) {
+    addRegisterClass(MVT::v2f16, &RISCV::FPR16V2RegClass);
+    //addRegisterClass(MVT::v4f16, &RISCV::FPR64RegClass);
+  }
+  if (Subtarget.hasDaiExtXfps()) {
+    addRegisterClass(MVT::v2f32, &RISCV::FPR32V2RegClass);
+  }
+
+  if (Subtarget.hasDaiExtXswar()) {
+    addRegisterClass(MVT::vswp32i1, &RISCV::SWARRRegClass);
+    addRegisterClass(MVT::vswp32i2, &RISCV::SWARRRegClass);
+    addRegisterClass(MVT::vswp32i3, &RISCV::SWARRRegClass);
+    addRegisterClass(MVT::vswp32i4, &RISCV::SWARRRegClass);
+    addRegisterClass(MVT::vswp32i8, &RISCV::SWARRRegClass);
+    addRegisterClass(MVT::vswp32i16, &RISCV::SWARRRegClass);
+    if (XLenVT==MVT::i64) {
+      addRegisterClass(MVT::vswp64i1, &RISCV::SWARR64RegClass);
+      addRegisterClass(MVT::vswp64i2, &RISCV::SWARR64RegClass);
+      addRegisterClass(MVT::vswp64i3, &RISCV::SWARR64RegClass);
+      addRegisterClass(MVT::vswp64i4, &RISCV::SWARR64RegClass);
+      addRegisterClass(MVT::vswp64i8, &RISCV::SWARR64RegClass);
+      addRegisterClass(MVT::vswp64i16, &RISCV::SWARR64RegClass);
+      addRegisterClass(MVT::vswp64i32, &RISCV::SWARR64RegClass);
+    }
+  }
+
   static const MVT::SimpleValueType BoolVecVTs[] = {
       MVT::nxv1i1,  MVT::nxv2i1,  MVT::nxv4i1, MVT::nxv8i1,
       MVT::nxv16i1, MVT::nxv32i1, MVT::nxv64i1};
@@ -308,9 +334,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
       ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FP16_TO_FP,
       ISD::FP_TO_FP16};
 
-  if (Subtarget.hasStdExtZfh())
-    setOperationAction(ISD::BITCAST, MVT::i16, Custom);
 
+/******************************************************************************/
+/*** FP HALF PRECISION ***/
   if (Subtarget.hasStdExtZfh()) {
     setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
     setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
@@ -318,6 +344,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::LLRINT, MVT::f16, Legal);
     setOperationAction(ISD::LROUND, MVT::f16, Legal);
     setOperationAction(ISD::LLROUND, MVT::f16, Legal);
+setOperationAction(ISD::FFLOOR, MVT::f16, LibCall);
+setOperationAction(ISD::FCEIL, MVT::f16, LibCall);
     for (auto CC : FPCCToExpand)
       setCondCodeAction(CC, MVT::f16, Expand);
     setOperationAction(ISD::SELECT_CC, MVT::f16, Expand);
@@ -325,8 +353,113 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::BR_CC, MVT::f16, Expand);
     for (auto Op : FPOpToExpand)
       setOperationAction(Op, MVT::f16, Expand);
+
+    setOperationAction(ISD::BITCAST, MVT::i16, Custom);
   }
+  if (!Subtarget.hasStdExtZfh() || Subtarget.isSoftFPHalf(llvm::SoftFops::SOFTFP_ADD))
+    setOperationAction(ISD::FADD, MVT::f16, LibCall);
+  if (!Subtarget.hasStdExtZfh() || Subtarget.isSoftFPHalf(llvm::SoftFops::SOFTFP_SUB))
+    setOperationAction(ISD::FSUB, MVT::f16, LibCall);
+  if (!Subtarget.hasStdExtZfh() || Subtarget.isSoftFPHalf(llvm::SoftFops::SOFTFP_MUL))
+    setOperationAction(ISD::FMUL, MVT::f16, LibCall);
+  if (!Subtarget.hasStdExtZfh() || Subtarget.isSoftFPHalf(llvm::SoftFops::SOFTFP_DIV))
+    setOperationAction(ISD::FDIV, MVT::f16, LibCall);
+  if (!Subtarget.hasStdExtZfh() || Subtarget.isSoftFPHalf(llvm::SoftFops::SOFTFP_SQRT))
+    setOperationAction(ISD::FSQRT, MVT::f16, LibCall);
+  if (!Subtarget.hasStdExtZfh() || Subtarget.isSoftFPHalf(llvm::SoftFops::SOFTFP_CF2I)) { /* convert float to int */
+    setOperationAction(ISD::FP_TO_SINT, MVT::i32, LibCall); /* TODO: Custom for testing input type is f64 */
+    setOperationAction(ISD::FP_TO_UINT, MVT::i32, LibCall); /* TODO: Custom for testing input type is f64 */
+  }
+  if (!Subtarget.hasStdExtZfh() || Subtarget.isSoftFPHalf(llvm::SoftFops::SOFTFP_CI2F)) { /* convert int to float */
+    setOperationAction(ISD::SINT_TO_FP, MVT::f16, LibCall);
+    setOperationAction(ISD::UINT_TO_FP, MVT::f16, LibCall);
+  }
+  if (!Subtarget.hasStdExtZfh() || Subtarget.isSoftFPHalf(llvm::SoftFops::SOFTFP_NEG))
+    setOperationAction(ISD::FNEG, MVT::f16, LibCall);
+  if (!Subtarget.hasStdExtZfh() || Subtarget.isSoftFPHalf(llvm::SoftFops::SOFTFP_ABS))
+    setOperationAction(ISD::FABS, MVT::f16, LibCall);
+
+
+/******************************************************************************/
+/*** FP PACKED-HALF PRECISION ***/
+  if (Subtarget.hasDaiExtXfph()) {
+    setOperationAction(ISD::FMINNUM, MVT::v2f16, Legal);
+    setOperationAction(ISD::FMAXNUM, MVT::v2f16, Legal);
+
+    setOperationAction(ISD::LOAD, MVT::v2f16, Legal);
+    setOperationAction(ISD::STORE, MVT::v2f16, Legal);
+    //setOperationAction(ISD::BITCAST, MVT::v2f16, Custom);
+    setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom); /* use different operations for each element */
+    setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f16, Custom);  /* v2f16 = insert(v2f16, f16, const idx) */
+    setOperationAction(ISD::BUILD_VECTOR, MVT::v2f16, Custom);
+    setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f16, Custom);
+
+    setOperationAction(ISD::SELECT_CC, MVT::v2f16, Expand);
+    setOperationAction(ISD::SELECT, MVT::v2f16, Custom);
+    setOperationAction(ISD::BR_CC, MVT::v2f16, Expand);
+  }
+
+
+/******************************************************************************/
+/*** FP PACKED-SINGLE PRECISION ***/
+  if (Subtarget.hasDaiExtXfps()) {
+    setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal);
+    setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal);
+
+    setOperationAction(ISD::LOAD, MVT::v2f32, Legal);
+    setOperationAction(ISD::STORE, MVT::v2f32, Legal);
+    //setOperationAction(ISD::BITCAST, MVT::v2f32, Custom);
+    setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f32, Custom); /* use different operations for each element */
+    setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom);  /* v2f32 = insert(v2f32, f32, const idx) */
+    setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
+    setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f32, Custom);
+
+    setOperationAction(ISD::SELECT_CC, MVT::v2f32, Expand);
+    setOperationAction(ISD::SELECT, MVT::v2f32, Custom);
+    setOperationAction(ISD::BR_CC, MVT::v2f32, Expand);
+  }
+
+
+/******************************************************************************/
+/*** SWAR ***/
+  if (Subtarget.hasDaiExtXswar()) {
+    //MVT vswp = (XLenVT==MVT::i32) ? MVT::vswp32 : MVT::vswp64;
+    for (MVT VT : MVT::subword_vector_valuetypes_i32()) {
+      setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); /* use different operations for each element */
+      setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);  /* v2f32 = insert(v2f32, f32, const idx) */
+      setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
+      setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
+      setOperationAction(ISD::LOAD, VT, Legal);
+      setOperationAction(ISD::STORE, VT, Legal);
+      setOperationAction(ISD::BITCAST, VT, Legal);
+      }
+    if (XLenVT==MVT::i64) {
+      for (MVT VT : MVT::subword_vector_valuetypes_i64()) {
+        setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); /* use different operations for each element */
+        setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);  /* v2f32 = insert(v2f32, f32, const idx) */
+        setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
+        setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
+        setOperationAction(ISD::LOAD, VT, Legal);
+        setOperationAction(ISD::STORE, VT, Legal);
+        setOperationAction(ISD::BITCAST, VT, Legal);
+      }
+      for (MVT VT : MVT::subword_vector_valuetypes_i32()) {
+        setTruncStoreAction(MVT::i64, VT, Expand);
+        //setIndexedStoreAction(MVT::i64, VT, Expand);
+        setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Custom);
+        setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Custom);
+
+        setOperationAction(ISD::TRUNCATE, VT, Custom);
+        setOperationAction(ISD::BITCAST, VT, Custom);
+      }
+      setOperationAction(ISD::ANY_EXTEND, MVT::i64, Custom);
+      setOperationAction(ISD::ZERO_EXTEND, MVT::i64, Custom);
+    }
+  }
+
 
+/******************************************************************************/
+/*** FP SINGLE PRECISION ***/
   if (Subtarget.hasStdExtF()) {
     setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
     setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
@@ -334,6 +467,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::LLRINT, MVT::f32, Legal);
     setOperationAction(ISD::LROUND, MVT::f32, Legal);
     setOperationAction(ISD::LLROUND, MVT::f32, Legal);
+setOperationAction(ISD::FFLOOR, MVT::f32, LibCall);
+setOperationAction(ISD::FCEIL, MVT::f32, LibCall);
     for (auto CC : FPCCToExpand)
       setCondCodeAction(CC, MVT::f32, Expand);
     setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
@@ -343,11 +478,39 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
       setOperationAction(Op, MVT::f32, Expand);
     setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
     setTruncStoreAction(MVT::f32, MVT::f16, Expand);
-  }
+    if (Subtarget.is64Bit())
+      setOperationAction(ISD::BITCAST, MVT::i32, Custom);
 
-  if (Subtarget.hasStdExtF() && Subtarget.is64Bit())
-    setOperationAction(ISD::BITCAST, MVT::i32, Custom);
+    setOperationAction(ISD::FLT_ROUNDS_, XLenVT, Custom);
+    setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom);
+  }
 
+  if (!Subtarget.hasStdExtF() || Subtarget.isSoftFPSingle(llvm::SoftFops::SOFTFP_ADD))
+    setOperationAction(ISD::FADD, MVT::f32, LibCall);
+  if (!Subtarget.hasStdExtF() || Subtarget.isSoftFPSingle(llvm::SoftFops::SOFTFP_SUB))
+    setOperationAction(ISD::FSUB, MVT::f32, LibCall);
+  if (!Subtarget.hasStdExtF() || Subtarget.isSoftFPSingle(llvm::SoftFops::SOFTFP_MUL))
+    setOperationAction(ISD::FMUL, MVT::f32, LibCall);
+  if (!Subtarget.hasStdExtF() || Subtarget.isSoftFPSingle(llvm::SoftFops::SOFTFP_DIV))
+    setOperationAction(ISD::FDIV, MVT::f32, LibCall);
+  if (!Subtarget.hasStdExtF() || Subtarget.isSoftFPSingle(llvm::SoftFops::SOFTFP_SQRT))
+    setOperationAction(ISD::FSQRT, MVT::f32, LibCall);
+  if (!Subtarget.hasStdExtF() || Subtarget.isSoftFPSingle(llvm::SoftFops::SOFTFP_CI2F)) { /* convert int to float */
+    setOperationAction(ISD::SINT_TO_FP, MVT::f32, LibCall);
+    setOperationAction(ISD::UINT_TO_FP, MVT::f32, LibCall);
+  }
+  if (!Subtarget.hasStdExtF() || Subtarget.isSoftFPSingle(llvm::SoftFops::SOFTFP_CF2I)) { /* convert float to int */
+    setOperationAction(ISD::FP_TO_SINT, MVT::f32, LibCall); /* TODO: Custom for testing input type is f64 */
+    setOperationAction(ISD::FP_TO_UINT, MVT::f32, LibCall); /* TODO: Custom for testing input type is f64 */
+  }
+  if (!Subtarget.hasStdExtF() || Subtarget.isSoftFPSingle(llvm::SoftFops::SOFTFP_ABS))
+    setOperationAction(ISD::FABS, MVT::f32, LibCall);
+  if (!Subtarget.hasStdExtF() || Subtarget.isSoftFPSingle(llvm::SoftFops::SOFTFP_NEG))
+    setOperationAction(ISD::FNEG, MVT::f32, LibCall);
+
+
+/******************************************************************************/
+/*** FP DOUBLE PRECISION ***/
   if (Subtarget.hasStdExtD()) {
     setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
     setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
@@ -355,6 +518,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::LLRINT, MVT::f64, Legal);
     setOperationAction(ISD::LROUND, MVT::f64, Legal);
     setOperationAction(ISD::LLROUND, MVT::f64, Legal);
+setOperationAction(ISD::FFLOOR, MVT::f64, LibCall);
+setOperationAction(ISD::FCEIL, MVT::f64, LibCall);
     for (auto CC : FPCCToExpand)
       setCondCodeAction(CC, MVT::f64, Expand);
     setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
@@ -368,6 +533,33 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
     setTruncStoreAction(MVT::f64, MVT::f16, Expand);
   }
 
+  if (!Subtarget.hasStdExtD() || Subtarget.isSoftFPDouble(llvm::SoftFops::SOFTFP_ADD))
+    setOperationAction(ISD::FADD, MVT::f64, LibCall);
+  if (!Subtarget.hasStdExtD() || Subtarget.isSoftFPDouble(llvm::SoftFops::SOFTFP_SUB))
+    setOperationAction(ISD::FSUB, MVT::f64, LibCall);
+  if (!Subtarget.hasStdExtD() || Subtarget.isSoftFPDouble(llvm::SoftFops::SOFTFP_MUL))
+    setOperationAction(ISD::FMUL, MVT::f64, LibCall);
+  if (!Subtarget.hasStdExtD() || Subtarget.isSoftFPDouble(llvm::SoftFops::SOFTFP_DIV))
+    setOperationAction(ISD::FDIV, MVT::f64, LibCall);
+  if (!Subtarget.hasStdExtD() || Subtarget.isSoftFPDouble(llvm::SoftFops::SOFTFP_SQRT))
+    setOperationAction(ISD::FSQRT, MVT::f64, LibCall);
+  if (!Subtarget.hasStdExtD() || Subtarget.isSoftFPDouble(llvm::SoftFops::SOFTFP_CI2F)) { /* convert int to float */
+    setOperationAction(ISD::SINT_TO_FP, MVT::f64, LibCall);
+    setOperationAction(ISD::UINT_TO_FP, MVT::f64, LibCall);
+  }
+  if (!Subtarget.hasStdExtD() || Subtarget.isSoftFPDouble(llvm::SoftFops::SOFTFP_CF2I)) { /* convert float to int */
+    setOperationAction(ISD::FP_TO_SINT, MVT::f64, LibCall); /* TODO: Custom for testing input type is f64 */
+    setOperationAction(ISD::FP_TO_UINT, MVT::f64, LibCall); /* TODO: Custom for testing input type is f64 */
+  }
+  if (!Subtarget.hasStdExtD() || Subtarget.isSoftFPDouble(llvm::SoftFops::SOFTFP_ABS))
+    setOperationAction(ISD::FABS, MVT::f64, LibCall);
+  if (!Subtarget.hasStdExtD() || Subtarget.isSoftFPDouble(llvm::SoftFops::SOFTFP_NEG))
+    setOperationAction(ISD::FNEG, MVT::f64, LibCall);
+
+
+
+/******************************************************************************/
+/*** other settings and extensions ***/
   if (Subtarget.is64Bit()) {
     setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
     setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
@@ -375,11 +567,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
   }
 
-  if (Subtarget.hasStdExtF()) {
-    setOperationAction(ISD::FLT_ROUNDS_, XLenVT, Custom);
-    setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom);
-  }
-
   setOperationAction(ISD::GlobalAddress, XLenVT, Custom);
   setOperationAction(ISD::BlockAddress, XLenVT, Custom);
   setOperationAction(ISD::ConstantPool, XLenVT, Custom);
@@ -407,6 +594,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
 
   setBooleanContents(ZeroOrOneBooleanContent);
 
+
+/******************************************************************************/
+/*** VECTOR extension ***/
   if (Subtarget.hasStdExtV()) {
     setBooleanVectorContents(ZeroOrOneBooleanContent);
 
@@ -1010,7 +1200,9 @@ bool RISCVTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
 bool RISCVTargetLowering::hasBitPreservingFPLogic(EVT VT) const {
   return (VT == MVT::f16 && Subtarget.hasStdExtZfh()) ||
          (VT == MVT::f32 && Subtarget.hasStdExtF()) ||
-         (VT == MVT::f64 && Subtarget.hasStdExtD());
+         (VT == MVT::f64 && Subtarget.hasStdExtD()) ||
+         (VT == MVT::v2f16 && Subtarget.hasDaiExtXfph()) ||
+         (VT == MVT::v2f32 && Subtarget.hasDaiExtXfps());
 }
 
 MVT RISCVTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
@@ -1020,6 +1212,10 @@ MVT RISCVTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
   // end up using a GPR but that will be decided based on ABI.
   if (VT == MVT::f16 && Subtarget.hasStdExtF() && !Subtarget.hasStdExtZfh())
     return MVT::f32;
+  if (VT == MVT::v2f16 && Subtarget.hasDaiExtXfph())
+    return MVT::f32;
+  if (VT == MVT::v2f32 && Subtarget.hasDaiExtXfps())
+    return MVT::f64;
 
   return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
 }
@@ -1471,11 +1667,50 @@ static Optional<VIDSequence> isSimpleVIDSequence(SDValue Op) {
 static SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
                                  const RISCVSubtarget &Subtarget) {
   MVT VT = Op.getSimpleValueType();
+  SDLoc DL(Op);
+
+  if (VT==MVT::v2f16 && Op.getNumOperands()==2) { /* packed half */
+    SDValue O1 = Op.getOperand(0);
+    SDValue O2 = Op.getOperand(1);
+    if (O1.getSimpleValueType()==MVT::f16 && O2.getSimpleValueType()==MVT::f16) {
+      SDValue V2Out = DAG.getNode(RISCVISD::MVLL_SINGLE2PACK_PH, DL, MVT::v2f16, O1, O2);
+      return V2Out;
+    }
+  }
+  if (VT==MVT::v2f32 && Op.getNumOperands()==2) { /* packed half */
+    SDValue O1 = Op.getOperand(0);
+    SDValue O2 = Op.getOperand(1);
+    if (O1.getSimpleValueType()==MVT::f32 && O2.getSimpleValueType()==MVT::f32) {
+      SDValue V2Out = DAG.getNode(RISCVISD::MVLL_SINGLE2PACK_PS, DL, MVT::v2f32, O1, O2);
+      return V2Out;
+    }
+  }
+
+  if (VT.isSubwordVector()) { /* build SWAR vector from constants (or variables ?) */
+    unsigned num = Op.getNumOperands();
+    uint64_t val = 0;
+    // only constant - compute in compile time
+    unsigned ebw = VT.getSubwordElmBitWidth();
+    uint64_t elmMask = ((1<<ebw)-1);
+
+    // step 1 - compute the value - TODO: repair for signed subword types
+    for(unsigned n=0;n<num;++n) {
+      ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Op.getOperand(n));
+      assert(Const && "Element for subword vector is not a constant.");
+      if (!Const) return SDValue(); /* not all constants ... TODO: process */
+      uint64_t cv = Op.getConstantOperandVal(n);
+      val = val | ((cv & elmMask)<<(ebw*n));
+    }
+    // create and return the output value
+    MVT IntVT = (VT.getSizeInBits() == 32) ? MVT::i32 : MVT::i64;
+    SDValue out = DAG.getNode(ISD::BITCAST, DL, VT, DAG.getConstant(val, DL, IntVT));
+    return out;
+  }
+
   assert(VT.isFixedLengthVector() && "Unexpected vector!");
 
   MVT ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget);
 
-  SDLoc DL(Op);
   SDValue Mask, VL;
   std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
 
@@ -1829,6 +2064,79 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
   unsigned NumElts = VT.getVectorNumElements();
   ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
 
+  //
+  if (VT==MVT::v2f16) {
+
+    ArrayRef<int> AM = SVN->getMask();
+    unsigned VecLen = AM.size();
+    if (VecLen!=2) {
+      fprintf(stderr,">RB< VectorShuffle for %u elements is not supported\n", VecLen);
+      return SDValue();
+    }
+    bool oneop = true;
+    if (AM[0]>1 || AM[1]>1) oneop = false;
+
+    EVT inVT1 = Op.getOperand(0).getValueType();
+
+    if (oneop) {
+      if (AM[0]==1 && AM[1]==0) { /* FSWAP => MOVVLU */
+        return DAG.getNode(RISCVISD::MVLUPH, DL, MVT::v2f16, Op.getOperand(0), Op.getOperand(0));
+      } else {
+        return SDValue();
+      }
+    } else {
+      EVT inVT2 = Op.getOperand(1).getValueType();
+
+      if (AM[0]==0 && AM[1]==2) { /* MOVVUU */
+        return DAG.getNode(RISCVISD::MVUUPH, DL, MVT::v2f16, Op.getOperand(0), Op.getOperand(1));
+      } else if (AM[0]==1 && AM[1]==3) { /* MOVVLL */
+        return DAG.getNode(RISCVISD::MVLLPH, DL, MVT::v2f16, Op.getOperand(0), Op.getOperand(1));
+      } else if (AM[0]==0 && AM[1]==3) { /* MOVVUL */
+        return DAG.getNode(RISCVISD::MVULPH, DL, MVT::v2f16, Op.getOperand(0), Op.getOperand(1));
+      } else if (AM[0]==1 && AM[1]==2) { /* MOVVLU */
+        return DAG.getNode(RISCVISD::MVLUPH, DL, MVT::v2f16, Op.getOperand(0), Op.getOperand(1));
+      } else {
+        return SDValue();
+      }
+    }
+
+  } else if (VT==MVT::v2f32) {
+
+    ArrayRef<int> AM = SVN->getMask();
+    unsigned VecLen = AM.size();
+    if (VecLen!=2) {
+      fprintf(stderr,">RB< VectorShuffle for %u elements is not supported\n", VecLen);
+      return SDValue();
+    }
+    bool oneop = true;
+    if (AM[0]>1 || AM[1]>1) oneop = false;
+
+    EVT inVT1 = Op.getOperand(0).getValueType();
+
+    if (oneop) {
+      if (AM[0]==1 && AM[1]==0) { /* FSWAP */
+        return DAG.getNode(RISCVISD::MVLUPS, DL, MVT::v2f32, Op.getOperand(0), Op.getOperand(0));
+      } else {
+        return SDValue();
+      }
+    } else {
+      EVT inVT2 = Op.getOperand(1).getValueType();
+
+      if (AM[0]==0 && AM[1]==2) { /* MOVVUU */
+        return DAG.getNode(RISCVISD::MVUUPS, DL, MVT::v2f32, Op.getOperand(0), Op.getOperand(1));
+      } else if (AM[0]==1 && AM[1]==3) { /* MOVVLL */
+        return DAG.getNode(RISCVISD::MVLLPS, DL, MVT::v2f32, Op.getOperand(0), Op.getOperand(1));
+      } else if (AM[0]==0 && AM[1]==3) { /* MOVVUL */
+        return DAG.getNode(RISCVISD::MVULPS, DL, MVT::v2f32, Op.getOperand(0), Op.getOperand(1));
+      } else if (AM[0]==1 && AM[1]==2) { /* MOVVLU */
+        return DAG.getNode(RISCVISD::MVLUPS, DL, MVT::v2f32, Op.getOperand(0), Op.getOperand(1));
+      } else {
+        return SDValue();
+      }
+    }
+
+  }
+
   MVT ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget);
 
   SDValue TrueMask, VL;
@@ -2123,6 +2431,30 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
     SDValue Op0 = Op.getOperand(0);
     EVT Op0VT = Op0.getValueType();
     MVT XLenVT = Subtarget.getXLenVT();
+
+    if (Subtarget.hasDaiExtXswar()) { /* i32/i64<->swar */
+      if (VT.isSubwordVector() && Op0VT.isScalarInteger()) { /* bitcast i32/i64 -> subword */
+        unsigned outbw = VT.getSizeInBits();
+        unsigned inbw = Op0VT.getSizeInBits();
+        unsigned Xbw = XLenVT.getSizeInBits();
+        if (inbw==outbw) {
+          return SDValue();
+        }
+        // if outbw != Xbw (should be only for swar vector packed in i32 on RV64(i64))
+        // the output is extracted as subreg
+        if (outbw<Xbw) {
+        }
+        return SDValue();
+      } else if (VT.isScalarInteger() && Op0VT.isSubwordVector()) { /* bitcast i32/i64 -> subword */
+        unsigned outbw = Op0VT.getSizeInBits();
+        unsigned Xbw = XLenVT.getSizeInBits();
+        if (outbw<Xbw) {
+//          return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, VT, Op0, DAG.getTargetConstant(0, DL, XLenVT)), 0);
+                         //DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),
+        }
+        return SDValue();
+      }
+    }
     if (VT.isFixedLengthVector()) {
       // We can handle fixed length vector bitcasts with a simple replacement
       // in isel.
@@ -2198,6 +2530,17 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
   case ISD::TRUNCATE: {
     SDLoc DL(Op);
     MVT VT = Op.getSimpleValueType();
+
+    SDValue Src = Op.getOperand(0);
+    MVT SrcVT = Src.getSimpleValueType();
+
+    // truncate i64->vswp32iX, maybe vswp64iX->vswp32iX should be possible
+    if (SrcVT==MVT::i64 && VT.isSubwordVector()) {
+      MVT intVT = VT.getVectorElementType();
+      SDValue tint = DAG.getNode(ISD::TRUNCATE, DL, intVT, Src);
+      return DAG.getNode(ISD::BITCAST, DL, VT, tint);
+    }
+    
     // Only custom-lower vector truncates
     if (!VT.isVector())
       return Op;
@@ -2211,8 +2554,6 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
     // truncate by one power of two at a time.
     MVT DstEltVT = VT.getVectorElementType();
 
-    SDValue Src = Op.getOperand(0);
-    MVT SrcVT = Src.getSimpleValueType();
     MVT SrcEltVT = SrcVT.getVectorElementType();
 
     assert(DstEltVT.bitsLT(SrcEltVT) &&
@@ -2245,11 +2586,26 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
     return Result;
   }
   case ISD::ANY_EXTEND:
-  case ISD::ZERO_EXTEND:
+  case ISD::ZERO_EXTEND: {
+    SDLoc DL(Op);
+    MVT VT = Op.getSimpleValueType();
+
+    SDValue Src = Op.getOperand(0);
+    MVT SrcVT = Src.getSimpleValueType();
+
+    if (VT==MVT::i64) {
+      if (SrcVT.isSubwordVector()) {
+        MVT intVT = SrcVT.getVectorElementType();
+        SDValue tint = DAG.getNode(ISD::BITCAST, DL, intVT, Src);
+        return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, tint);
+      }
+      return SDValue();
+    }
     if (Op.getOperand(0).getValueType().isVector() &&
         Op.getOperand(0).getValueType().getVectorElementType() == MVT::i1)
       return lowerVectorMaskExt(Op, DAG, /*ExtVal*/ 1);
     return lowerFixedLengthVectorExtendToRVV(Op, DAG, RISCVISD::VZEXT_VL);
+  }
   case ISD::SIGN_EXTEND:
     if (Op.getOperand(0).getValueType().isVector() &&
         Op.getOperand(0).getValueType().getVectorElementType() == MVT::i1)
@@ -2376,6 +2732,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
       return convertFromScalableVector(VT, Round, DAG, Subtarget);
     return Round;
   }
+
   case ISD::FP_TO_SINT:
   case ISD::FP_TO_UINT:
   case ISD::SINT_TO_FP:
@@ -2526,12 +2883,30 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
     return Vec;
   }
   case ISD::LOAD:
+    if (Subtarget.hasDaiExtXfph() && Op.getValueType()==MVT::v2f16) {
+      return lowerXfphLoad(Op, DAG);
+    }
+    if (Subtarget.hasDaiExtXfps() && Op.getValueType()==MVT::v2f32) {
+      return lowerXfpsLoad(Op, DAG);
+    }
+    if (Subtarget.getXLenVT()==MVT::i64 && Op.getValueType().isSubwordVector() && Op.getValueType().getSizeInBits()==32) { // only vswp32iX ?
+      return lowerXswar32Load(Op, DAG);
+    }
     if (auto V = expandUnalignedRVVLoad(Op, DAG))
       return V;
     if (Op.getValueType().isFixedLengthVector())
       return lowerFixedLengthVectorLoadToRVV(Op, DAG);
     return Op;
   case ISD::STORE:
+    if (Subtarget.hasDaiExtXfph() && Op.getOperand(1).getValueType()==MVT::v2f16) {
+      return lowerXfphStore(Op, DAG);
+    }
+    if (Subtarget.hasDaiExtXfps() && Op.getOperand(1).getValueType()==MVT::v2f32) {
+      return lowerXfpsStore(Op, DAG);
+    }
+    if (Subtarget.hasDaiExtXswar() && Op.getOperand(1).getValueType().isSubwordVector()) {
+      return lowerXswar32Store(Op, DAG);
+    }
     if (auto V = expandUnalignedRVVStore(Op, DAG))
       return V;
     if (Op.getOperand(1).getValueType().isFixedLengthVector())
@@ -3342,6 +3717,110 @@ SDValue RISCVTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
   SDValue Val = Op.getOperand(1);
   SDValue Idx = Op.getOperand(2);
 
+  MVT XLenVT = Subtarget.getXLenVT();
+
+  if (VecVT==MVT::v2f16 && Val.getSimpleValueType()==MVT::f16) {
+    MVT XLenVT = Subtarget.getXLenVT();
+    uint64_t idx = Op->getConstantOperandVal(2);
+
+    SDValue IVal = DAG.getNode(RISCVISD::FMV_X_ANYEXTH, DL, XLenVT, Val);
+    SDValue V2Val = DAG.getNode(RISCVISD::FMV_PH_X_RV64, DL, MVT::v2f16, IVal);
+    if (idx==1) { // insert to lower half
+      SDValue V2Out = DAG.getNode(RISCVISD::MVULPH, DL, MVT::v2f16, Vec, V2Val);
+      return V2Out;
+    } else {      // insert to upper half
+      SDValue V2Out = DAG.getNode(RISCVISD::MVLLPH, DL, MVT::v2f16, V2Val, Vec);
+      return V2Out;
+    }
+  }
+
+  if (VecVT==MVT::v2f32 && Val.getSimpleValueType()==MVT::f32) {
+    MVT XLenVT = Subtarget.getXLenVT();
+    uint64_t idx = Op->getConstantOperandVal(2);
+
+    SDValue IVal = DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, XLenVT, Val);
+    SDValue V2Val = DAG.getNode(RISCVISD::FMV_PS_X_RV64, DL, MVT::v2f32, IVal);
+    if (idx==1) { // insert to lower half
+      SDValue V2Out = DAG.getNode(RISCVISD::MVULPS, DL, MVT::v2f32, Vec, V2Val);
+      return V2Out;
+    } else {      // insert to upper half
+      SDValue V2Out = DAG.getNode(RISCVISD::MVLLPS, DL, MVT::v2f32, V2Val, Vec);
+      return V2Out;
+    }
+  }
+
+  if (VecVT.isSubwordVector()) {
+    unsigned NumElts = VecVT.getSubwordPacking(); // number of elements in the basic type
+    EVT inVT1 = Vec.getValueType();
+    EVT inVT2 = Val.getValueType();
+
+
+    assert(VecVT == inVT1.getSimpleVT()); /* the output type is the same as the input type */
+    unsigned inbw = inVT1.getSizeInBits();
+    unsigned inebw = inVT1.getSimpleVT().getSubwordElmBitWidth();
+    unsigned outbw = VecVT.getSizeInBits();
+
+
+    // Basic Type of VecVT is either MVT::i32 or MVT::i64
+    MVT packType = (outbw==32) ? MVT::i32 : MVT::i64;
+    SDValue shift, valmask, remmask;
+
+    ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Op.getOperand(2));
+    if (Const) { /* index is constant */
+      uint64_t idx = Op->getConstantOperandVal(2);
+      unsigned c_shift = inebw*idx;
+      uint64_t c_valMask = ((1<<inebw)-1)<<c_shift;
+      uint64_t c_remMask = ~c_valMask;
+
+      shift = DAG.getConstant(c_shift, DL, packType); // XLenVT
+      valmask = DAG.getConstant(c_valMask, DL, packType);
+      remmask = DAG.getConstant(c_remMask, DL, packType);
+
+    } else {
+      if (Idx.getValueType().getSizeInBits()<XLenVT.getSizeInBits()) {
+        Idx = DAG.getNode(ISD::ZERO_EXTEND, DL, XLenVT, Idx);
+      } else if (Idx.getValueType().getSizeInBits()>XLenVT.getSizeInBits()) {
+        Idx = DAG.getNode(ISD::TRUNCATE, DL, XLenVT, Idx);
+      }
+      // shift=Op(2)*ebw
+      shift = DAG.getNode(ISD::MUL, DL, XLenVT, Idx, DAG.getConstant(inebw, DL, XLenVT)); //XLenVT
+      // valMask = ((1<<ebw)-1)<<shift
+      valmask = DAG.getNode(ISD::SHL, DL, XLenVT, DAG.getConstant( ((1<<inebw)-1) , DL, XLenVT), shift);
+      // remMask = ~valMask
+      remmask = DAG.getNode(ISD::XOR, DL, XLenVT, valmask, DAG.getConstant( -1 , DL, XLenVT));
+    }
+    SDValue Step0;
+    if (Val.getValueType().getSizeInBits()<XLenVT.getSizeInBits()) {
+      Step0 = DAG.getNode(ISD::ZERO_EXTEND, DL, XLenVT, Val);
+    } else if (Val.getValueType().getSizeInBits()>XLenVT.getSizeInBits()) {
+      Step0 = DAG.getNode(ISD::TRUNCATE, DL, XLenVT, Val);
+    } else {
+      // s0=bitcast(newelm) /* useful for vsXp32 */
+      Step0 = DAG.getNode(ISD::BITCAST, DL, XLenVT, Val);
+    }
+
+    // s1=s0 << shift
+    SDValue Step1 = DAG.getNode(ISD::SHL, DL, XLenVT, Step0, shift);
+    // s2 = s1 & valmask
+    SDValue Step2 = DAG.getNode(ISD::AND, DL, XLenVT, Step1, valmask);
+    // s3 = bitcast(vec)
+    SDValue Step3;
+    if (inbw<XLenVT.getSizeInBits()) { // vsXp32 on RV64
+      Step3 = DAG.getNode(ISD::BITCAST, DL, packType, Vec);
+      Step3 = DAG.getNode(ISD::ZERO_EXTEND, DL, XLenVT, Step3);
+    } else {
+      Step3 = DAG.getNode(ISD::BITCAST, DL, XLenVT, Vec);
+    }
+    // s4 = s3 & remmask
+    SDValue Step4 = DAG.getNode(ISD::AND, DL, XLenVT, Step3, remmask);
+    // out = s2 or s4
+    SDValue Step5 = DAG.getNode(ISD::OR, DL, XLenVT, Step2, Step4);
+    // bitcast/extend/truncate to subword type
+    if (outbw<XLenVT.getSizeInBits())
+      Step5 = DAG.getNode(ISD::TRUNCATE, DL, packType, Step5);
+    return DAG.getNode(ISD::BITCAST, DL, VecVT, Step5);
+  }
+
   if (VecVT.getVectorElementType() == MVT::i1) {
     // FIXME: For now we just promote to an i8 vector and insert into that,
     // but this is probably not optimal.
@@ -3358,8 +3837,6 @@ SDValue RISCVTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
     Vec = convertToScalableVector(ContainerVT, Vec, DAG, Subtarget);
   }
 
-  MVT XLenVT = Subtarget.getXLenVT();
-
   SDValue Zero = DAG.getConstant(0, DL, XLenVT);
   bool IsLegalInsert = Subtarget.is64Bit() || Val.getValueType() != MVT::i64;
   // Even i64-element vectors on RV32 can be lowered without scalar
@@ -3439,6 +3916,86 @@ SDValue RISCVTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
   EVT EltVT = Op.getValueType();
   MVT VecVT = Vec.getSimpleValueType();
   MVT XLenVT = Subtarget.getXLenVT();
+/* packed half FP */
+  if (VecVT==MVT::v2f16 && EltVT==MVT::f16) {
+    //assert(inVT == MVT::v2f16);
+    uint64_t idx = Op->getConstantOperandVal(1);
+    if (idx==1) { // extract lower half
+      SDValue IVal = DAG.getNode(RISCVISD::FMV_X_ANYEXTPH_RV64, DL, XLenVT, Vec);
+      SDValue FPConv = DAG.getNode(RISCVISD::FMV_H_X, DL, MVT::f16, IVal);
+      return FPConv;
+    } else {      // extract upper half
+      SDValue SwapOp = DAG.getNode(RISCVISD::MVLUPH, DL, MVT::v2f16, Vec, Vec);
+      SDValue IVal = DAG.getNode(RISCVISD::FMV_X_ANYEXTPH_RV64, DL, XLenVT, SwapOp);
+      SDValue FPConv = DAG.getNode(RISCVISD::FMV_H_X, DL, MVT::f16, IVal);
+      return FPConv;
+    }
+  }
+/* packed single FP */
+  if (VecVT==MVT::v2f32 && EltVT==MVT::f32) {
+    //assert(inVT == MVT::v2f32);
+    uint64_t idx = Op->getConstantOperandVal(1);
+    if (idx==1) { // extract lower half
+      SDValue IVal = DAG.getNode(RISCVISD::FMV_X_PS_RV64, DL, XLenVT, Vec);
+      SDValue FPConv = DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, IVal);
+      return FPConv;
+    } else {      // extract upper half
+      SDValue SwapOp = DAG.getNode(RISCVISD::MVLUPS, DL, MVT::v2f32, Vec, Vec);
+      SDValue IVal = DAG.getNode(RISCVISD::FMV_X_PS_RV64, DL, XLenVT, SwapOp);
+      SDValue FPConv = DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, IVal);
+      return FPConv;
+    }
+  }
+/* subword vectors */
+  if (VecVT.isSubwordVector()) {
+
+//    EVT EVecVT = Vec.getValueType();
+    unsigned NumElts = VecVT.getVectorNumElements();
+    unsigned bw = VecVT.getSizeInBits();
+    unsigned ebw = VecVT.getSubwordElmBitWidth();
+
+
+    assert(EltVT.getSizeInBits() >= ebw); /* the output type has at least the same size as an element of the input type */
+
+    MVT IntVT = (Op.getOperand(0).getSimpleValueType().getSizeInBits() == 32) ? MVT::i32 : MVT::i64;
+
+    ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Op.getOperand(1));
+    if (Const) { /* index is constant */
+      uint64_t idx = Op.getConstantOperandVal(1);
+
+      unsigned shift = ebw*idx;
+      uint64_t valMask = ((1<<ebw)-1);
+
+      // s0=bitcast(vect)
+      SDValue Step0 = DAG.getNode(ISD::BITCAST, DL, IntVT, Op.getOperand(0));
+      // s1=s0 >> shift
+      SDValue Step1 = DAG.getNode(ISD::SRL, DL, IntVT, Step0, DAG.getConstant(shift, DL, IntVT));
+      // s2 = s1 & valmask
+      SDValue Step2 = DAG.getNode(ISD::AND, DL, IntVT, Step1, DAG.getConstant(valMask, DL, IntVT));
+      // return bitcast(s2)
+      return DAG.getNode(ISD::BITCAST, DL, IntVT, Step2); // VT
+    } else {
+
+      // s0=bitcast(subword vect) to basic integer (vswp32 -> i32, vswp64 -> i64)
+      SDValue Step0 = DAG.getNode(ISD::BITCAST, DL, IntVT, Op.getOperand(0));
+      // sX0=trunc_or_zext(s0)
+      if (XLenVT.getSizeInBits()<IntVT.getSizeInBits()) // truncate
+        Step0 = DAG.getNode(ISD::TRUNCATE, DL, XLenVT, Step0);
+      else if (XLenVT.getSizeInBits()>IntVT.getSizeInBits()) // zext
+        Step0 = DAG.getNode(ISD::ZERO_EXTEND, DL, XLenVT, Step0);
+      // shift=Op(1)*ebw
+      SDValue shift = DAG.getNode(ISD::MUL, DL, XLenVT, Op.getOperand(1), DAG.getConstant(ebw, DL, XLenVT));
+      // valMask = ((1<<ebw)-1)
+      SDValue valmask = DAG.getConstant( ((1<<ebw)-1) , DL, XLenVT);
+      // s1=s0 >> shift
+      SDValue Step1 = DAG.getNode(ISD::SRL, DL, XLenVT, Step0, shift);
+      // s2 = s1 & valmask
+      SDValue Step2 = DAG.getNode(ISD::AND, DL, XLenVT, Step1, valmask);
+      // return bitcast(vec)
+      return DAG.getNode(ISD::BITCAST, DL, XLenVT, Step2); // VT
+    }
+
+  }
 
   if (VecVT.getVectorElementType() == MVT::i1) {
     // FIXME: For now we just promote to an i8 vector and extract from that,
@@ -4277,6 +4834,62 @@ SDValue RISCVTargetLowering::lowerVECTOR_REVERSE(SDValue Op,
   return DAG.getNode(GatherOpc, DL, VecVT, Op.getOperand(0), Indices, Mask, VL);
 }
 
+SDValue
+RISCVTargetLowering::lowerXswar32Load(SDValue Op, SelectionDAG &DAG) const {
+  SDLoc dl(Op);
+  LoadSDNode *LdNode = cast<LoadSDNode>(Op.getNode());
+  SDValue LVal = SDValue(
+          DAG.getMachineNode(RISCV::LSWAR32, dl, Op.getValueType(), {LdNode->getOperand(0), LdNode->getOperand(1)}), 0);
+  SDValue LChain = LdNode->getChain();
+  return DAG.getMergeValues({LVal, LChain}, dl);
+}
+
+SDValue
+RISCVTargetLowering::lowerXswar32Store(SDValue Op, SelectionDAG &DAG) const {
+  SDLoc dl(Op);
+  StoreSDNode *St = cast<StoreSDNode>(Op.getNode());
+  SDValue Chain = SDValue(DAG.getMachineNode(RISCV::SSWAR32, dl, MVT::vswp32i1, {St->getOperand(0), St->getOperand(1), St->getOperand(2)}), 0);
+  return Chain;
+}
+
+SDValue
+RISCVTargetLowering::lowerXfphLoad(SDValue Op, SelectionDAG &DAG) const {
+  SDLoc dl(Op);
+  LoadSDNode *LdNode = cast<LoadSDNode>(Op.getNode());
+  SDValue LVal = SDValue(
+          DAG.getMachineNode(RISCV::FLW, dl, MVT::v2f16, {LdNode->getOperand(0), LdNode->getOperand(1)}), 0);
+  SDValue LChain = LdNode->getChain();
+  return DAG.getMergeValues({LVal, LChain}, dl);
+}
+
+SDValue
+RISCVTargetLowering::lowerXfphStore(SDValue Op, SelectionDAG &DAG) const {
+  SDLoc dl(Op);
+  StoreSDNode *St = cast<StoreSDNode>(Op.getNode());
+  SDValue Chain = SDValue(DAG.getMachineNode(RISCV::FSW, dl, MVT::v2f16, {St->getOperand(0), St->getOperand(1), St->getOperand(2)}), 0);
+  return Chain;
+}
+
+SDValue
+RISCVTargetLowering::lowerXfpsLoad(SDValue Op, SelectionDAG &DAG) const {
+  SDLoc dl(Op);
+  LoadSDNode *LdNode = cast<LoadSDNode>(Op.getNode());
+  SDValue LVal = SDValue(
+          DAG.getMachineNode(RISCV::FLD, dl, MVT::v2f32, {LdNode->getOperand(0), LdNode->getOperand(1)}), 0);
+  SDValue LChain = LdNode->getChain();
+  return DAG.getMergeValues({LVal, LChain}, dl);
+}
+
+SDValue
+RISCVTargetLowering::lowerXfpsStore(SDValue Op, SelectionDAG &DAG) const {
+  SDLoc dl(Op);
+  StoreSDNode *St = cast<StoreSDNode>(Op.getNode());
+  SDValue Chain = SDValue(DAG.getMachineNode(RISCV::FSD, dl, MVT::v2f32, {St->getOperand(0), St->getOperand(1), St->getOperand(2)}), 0);
+  return Chain;
+}
+
+/* -------------------------------------------------------------------------- */
+
 SDValue
 RISCVTargetLowering::lowerFixedLengthVectorLoadToRVV(SDValue Op,
                                                      SelectionDAG &DAG) const {
@@ -4406,17 +5019,30 @@ SDValue RISCVTargetLowering::lowerMSTORE(SDValue Op, SelectionDAG &DAG) const {
 SDValue
 RISCVTargetLowering::lowerFixedLengthVectorSetccToRVV(SDValue Op,
                                                       SelectionDAG &DAG) const {
+  SDLoc DL(Op);
   MVT InVT = Op.getOperand(0).getSimpleValueType();
-  MVT ContainerVT = getContainerForFixedLengthVector(InVT);
-
   MVT VT = Op.getSimpleValueType();
 
+  // pass all integer operands to normal SetCC
+  if (InVT.isInteger()) {
+    ISD::CondCode CCCode = cast<CondCodeSDNode>(Op->getOperand(2))->get();
+    unsigned ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
+    SDValue Tmp1 = DAG.getNode(ExtOp, DL, VT, Op->getOperand(0));
+    SDValue Tmp2 = DAG.getNode(ExtOp, DL, VT, Op->getOperand(1));
+    return DAG.getNode(ISD::SETCC, DL, Op->getValueType(0), Tmp1,
+                                  Tmp2, Op->getOperand(2), Op->getFlags());
+  }
+  if (InVT.isFloatingPoint()) {
+    return SDValue();
+  }
+
+  MVT ContainerVT = getContainerForFixedLengthVector(InVT);
+
   SDValue Op1 =
       convertToScalableVector(ContainerVT, Op.getOperand(0), DAG, Subtarget);
   SDValue Op2 =
       convertToScalableVector(ContainerVT, Op.getOperand(1), DAG, Subtarget);
 
-  SDLoc DL(Op);
   SDValue VL =
       DAG.getConstant(VT.getVectorNumElements(), DL, Subtarget.getXLenVT());
 
@@ -8448,6 +9074,33 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
   NODE_NAME_CASE(READ_CSR)
   NODE_NAME_CASE(WRITE_CSR)
   NODE_NAME_CASE(SWAP_CSR)
+
+  NODE_NAME_CASE(SWAR)
+//  NODE_NAME_CASE(SWARCC)
+  NODE_NAME_CASE(SWARCTRL)
+//  NODE_NAME_CASE(SWAPPH)
+  NODE_NAME_CASE(MVUUPH)
+  NODE_NAME_CASE(MVLLPH)
+  NODE_NAME_CASE(MVULPH)
+  NODE_NAME_CASE(MVLUPH)
+  NODE_NAME_CASE(MVZUPH)
+  NODE_NAME_CASE(MVZLPH)
+  NODE_NAME_CASE(FMV_PH_X_RV64)
+  NODE_NAME_CASE(FMV_X_ANYEXTPH_RV64)
+  NODE_NAME_CASE(FMV_X_PS_RV64)
+  NODE_NAME_CASE(FMV_PS_X_RV64)
+
+//  NODE_NAME_CASE(SWAPPS)
+  NODE_NAME_CASE(MVUUPS)
+  NODE_NAME_CASE(MVLLPS)
+  NODE_NAME_CASE(MVULPS)
+  NODE_NAME_CASE(MVLUPS)
+  NODE_NAME_CASE(MVZUPS)
+  NODE_NAME_CASE(MVZLPS)
+
+  NODE_NAME_CASE(MVLL_SINGLE2PACK_PH)
+  NODE_NAME_CASE(MVLL_SINGLE2PACK_PS)
+
   }
   // clang-format on
   return nullptr;
@@ -8495,6 +9148,10 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
         return std::make_pair(0U, &RISCV::FPR32RegClass);
       if (Subtarget.hasStdExtD() && VT == MVT::f64)
         return std::make_pair(0U, &RISCV::FPR64RegClass);
+      if (Subtarget.hasDaiExtXfph() && VT == MVT::v2f16)
+        return std::make_pair(0U, &RISCV::FPR16V2RegClass);
+      if (Subtarget.hasDaiExtXfps() && VT == MVT::v2f32)
+        return std::make_pair(0U, &RISCV::FPR32V2RegClass);
       break;
     case 'v':
       for (const auto *RC :
@@ -8557,7 +9214,8 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
   //
   // The second case is the ABI name of the register, so that frontends can also
   // use the ABI names in register constraint lists.
-  if (Subtarget.hasStdExtF()) {
+  if (Subtarget.hasStdExtF() ||
+      Subtarget.hasDaiExtXfph() || Subtarget.hasDaiExtXfps()) {
     unsigned FReg = StringSwitch<unsigned>(Constraint.lower())
                         .Cases("{f0}", "{ft0}", RISCV::F0_F)
                         .Cases("{f1}", "{ft1}", RISCV::F1_F)
@@ -8594,7 +9252,7 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
                         .Default(RISCV::NoRegister);
     if (FReg != RISCV::NoRegister) {
       assert(RISCV::F0_F <= FReg && FReg <= RISCV::F31_F && "Unknown fp-reg");
-      if (Subtarget.hasStdExtD()) {
+      if (Subtarget.hasStdExtD() || Subtarget.hasDaiExtXfps()) {
         unsigned RegNo = FReg - RISCV::F0_F;
         unsigned DReg = RISCV::F0_D + RegNo;
         return std::make_pair(DReg, &RISCV::FPR64RegClass);
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 0e71220da3b3..7c0d48e13d8d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -275,6 +275,34 @@ enum NodeType : unsigned {
   // the value read before the modification and the new chain pointer.
   SWAP_CSR,
 
+  // daiteq extensions swar, packed half, packed single
+  SWAR,       // swar direct operation
+  SWARCTRL,   // swar control -> currently wrasr
+
+//  SWAPPH,    // SWAP for floating point packed half type (AuAl -> AlAu)
+  MVUUPH,     // copy upper elements from two v2f16 into one v2f16 (AuAl,BuBl -> AuBu)
+  MVLLPH,     // copy lower elements from two v2f16 into one v2f16 (AuAl,BuBl -> AlBl)
+  MVULPH,     // copy upper element from the first register and lower element from the second register into one v2f16 (AuAl,BuBl -> AuBl)
+  MVLUPH,     // copy lower element from the first register and upper element from the second register and swap them into one v2f16 (AuAl,BuBl -> AlBu)
+  MVZUPH,     // copy upper element of v2f16 to lower element and set zero to upper element of v2f16 (AuAl -> 0Au)
+  MVZLPH,     // copy lower element of v2f16 to lower element and set zero to upper element of v2f16 (AuAl -> 0Al)
+
+  FMV_PH_X_RV64,
+  FMV_X_ANYEXTPH_RV64,
+  FMV_PS_X_RV64,
+  FMV_X_PS_RV64,
+
+//  SWAPPS,    // SWAP for floating point packed single type (AuAl -> AlAu)
+  MVUUPS,    // copy upper elements from two v2f32 into one v2f32 (AuAl,BuBl -> AuBu)
+  MVLLPS,    // copy lower elements from two v2f32 into one v2f32 (AuAl,BuBl -> AlBl)
+  MVULPS,    // copy upper element from the first register and lower element from the second register into one v2f32 (AuAl,BuBl -> AuBl)
+  MVLUPS,    // copy lower element from the first register and upper element from the second register and swap them into one v2f32 (AuAl,BuBl -> AlBu)
+  MVZUPS,    // copy upper element of v2f32 to lower element and set zero to upper element of v2f32 (AuAl -> 0Au)
+  MVZLPS,    // copy lower element of v2f32 to lower element and set zero to upper element of v2f32 (AuAl -> 0Al)
+
+  MVLL_SINGLE2PACK_PH,
+  MVLL_SINGLE2PACK_PS,
+
   // Memory opcodes start here.
   VLE_VL = ISD::FIRST_TARGET_MEMORY_OPCODE,
   VSE_VL,
@@ -581,6 +609,14 @@ private:
   SDValue expandUnalignedRVVLoad(SDValue Op, SelectionDAG &DAG) const;
   SDValue expandUnalignedRVVStore(SDValue Op, SelectionDAG &DAG) const;
 
+  SDValue lowerXswar32Load(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerXswar32Store(SDValue Op, SelectionDAG &DAG) const;
+
+  SDValue lowerXfphLoad(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerXfphStore(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerXfpsLoad(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerXfpsStore(SDValue Op, SelectionDAG &DAG) const;
+
   bool isEligibleForTailCallOptimization(
       CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
       const SmallVector<CCValAssign, 16> &ArgLocs) const;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 207101763ac2..5cc840e6cb8c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -135,7 +135,13 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   unsigned NF = 1;
   unsigned LMul = 1;
   unsigned SubRegIdx = RISCV::sub_vrm1_0;
-  if (RISCV::FPR16RegClass.contains(DstReg, SrcReg)) {
+  if (RISCV::FPR32V2RegClass.contains(DstReg, SrcReg)) {
+    Opc = RISCV::FSGNJ_PS;
+    IsScalableVector = false;
+  } else if (RISCV::FPR16V2RegClass.contains(DstReg, SrcReg)) {
+    Opc = RISCV::FSGNJ_PH;
+    IsScalableVector = false;
+  } else if (RISCV::FPR16RegClass.contains(DstReg, SrcReg)) {
     Opc = RISCV::FSGNJ_H;
     IsScalableVector = false;
   } else if (RISCV::FPR32RegClass.contains(DstReg, SrcReg)) {
@@ -259,6 +265,12 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
     Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
              RISCV::SW : RISCV::SD;
     IsScalableVector = false;
+  } else if (RISCV::FPR32V2RegClass.hasSubClassEq(RC)) {
+    Opcode = RISCV::FSD;
+    IsScalableVector = false;
+  } else if (RISCV::FPR16V2RegClass.hasSubClassEq(RC)) {
+    Opcode = RISCV::FSW;
+    IsScalableVector = false;
   } else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) {
     Opcode = RISCV::FSH;
     IsScalableVector = false;
@@ -353,6 +365,12 @@ void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
     Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
              RISCV::LW : RISCV::LD;
     IsScalableVector = false;
+  } else if (RISCV::FPR32V2RegClass.hasSubClassEq(RC)) {
+    Opcode = RISCV::FLD;
+    IsScalableVector = false;
+  } else if (RISCV::FPR16V2RegClass.hasSubClassEq(RC)) {
+    Opcode = RISCV::FLW;
+    IsScalableVector = false;
   } else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) {
     Opcode = RISCV::FLH;
     IsScalableVector = false;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 949fff25e9e0..08005e195539 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1305,6 +1305,43 @@ def : Pat<(sext_inreg (add_oneuse GPR:$rs1, (AddiPair:$rs2)), i32),
                  (AddiPairImmA AddiPair:$rs2))>;
 }
 
+
+//
+//===----------------------------------------------------------------------===//
+// Standard extensions
+//===----------------------------------------------------------------------===//
+
+// from RISCVInstrInfoF, used in RISCVInstrInfoF,RISCVInstrInfoD,RISCVInstrInfoXfph,RISCVInstrInfoXfps,RISCVInstrInfoZfh
+// Floating-point rounding mode
+def FRMArg : AsmOperandClass {
+  let Name = "FRMArg";
+  let RenderMethod = "addFRMArgOperands";
+  let DiagnosticType = "InvalidFRMArg";
+}
+def frmarg : Operand<XLenVT> {
+  let ParserMatchClass = FRMArg;
+  let PrintMethod = "printFRMArg";
+  let DecoderMethod = "decodeFRMArg";
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FPUnaryOp_r<bits<7> funct7, bits<3> funct3, RegisterClass rdty,
+                RegisterClass rs1ty, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_FP, (outs rdty:$rd), (ins rs1ty:$rs1),
+              opcodestr, "$rd, $rs1">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FPUnaryOp_r_frm<bits<7> funct7, RegisterClass rdty, RegisterClass rs1ty,
+                      string opcodestr>
+    : RVInstRFrm<funct7, OPC_OP_FP, (outs rdty:$rd),
+                 (ins rs1ty:$rs1, frmarg:$funct3), opcodestr,
+                  "$rd, $rs1, $funct3">;
+
+class FPUnaryOpDynFrmAlias<FPUnaryOp_r_frm Inst, string OpcodeStr,
+                           RegisterClass rdty, RegisterClass rs1ty>
+    : InstAlias<OpcodeStr#" $rd, $rs1",
+                (Inst rdty:$rd, rs1ty:$rs1, 0b111)>;
+
 //===----------------------------------------------------------------------===//
 // Standard extensions
 //===----------------------------------------------------------------------===//
@@ -1317,3 +1354,7 @@ include "RISCVInstrInfoC.td"
 include "RISCVInstrInfoB.td"
 include "RISCVInstrInfoV.td"
 include "RISCVInstrInfoZfh.td"
+
+include "RISCVInstrInfoXfph.td"
+include "RISCVInstrInfoXfps.td"
+include "RISCVInstrInfoXswar.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
index 41eff2ef7607..57ea046958e9 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
@@ -80,7 +80,9 @@ def FSD : RVInstS<0b011, OPC_STORE_FP, (outs),
                   (ins FPR64:$rs2, GPR:$rs1, simm12:$imm12),
                    "fsd", "$rs2, ${imm12}(${rs1})">,
           Sched<[WriteFST64, ReadStoreData, ReadFMemBase]>;
+} // Predicates = [HasStdExtD]
 
+let Predicates = [HasStdExtD] in {
 def FMADD_D  : FPFMAD_rrr_frm<OPC_MADD, "fmadd.d">,
                Sched<[WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64]>;
 def          : FPFMADDynFrmAlias<FMADD_D, "fmadd.d">;
@@ -93,10 +95,16 @@ def          : FPFMADDynFrmAlias<FNMSUB_D, "fnmsub.d">;
 def FNMADD_D : FPFMAD_rrr_frm<OPC_NMADD, "fnmadd.d">,
                Sched<[WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64]>;
 def          : FPFMADDynFrmAlias<FNMADD_D, "fnmadd.d">;
+} // Predicates = [HasStdExtD]
 
+let Predicates = [HasStdExtD, NotSoftFADDDouble] in {
 def FADD_D : FPALUD_rr_frm<0b0000001, "fadd.d">,
              Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
 def        : FPALUDDynFrmAlias<FADD_D, "fadd.d">;
+} // Predicates = [HasStdExtD, NotSoftFADDDouble]
+
+
+let Predicates = [HasStdExtD] in {
 def FSUB_D : FPALUD_rr_frm<0b0000101, "fsub.d">,
              Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
 def        : FPALUDDynFrmAlias<FSUB_D, "fsub.d">;
@@ -211,6 +219,11 @@ let Predicates = [HasStdExtD] in {
 def : InstAlias<"fld $rd, (${rs1})",  (FLD FPR64:$rd,  GPR:$rs1, 0), 0>;
 def : InstAlias<"fsd $rs2, (${rs1})", (FSD FPR64:$rs2, GPR:$rs1, 0), 0>;
 
+def PseudoFLD  : PseudoFloatLoad<"fld", FPR64>;
+def PseudoFSD  : PseudoStore<"fsd", FPR64>;
+} // Predicates = [HasStdExtD]
+
+let Predicates = [HasStdExtD] in {
 def : InstAlias<"fmv.d $rd, $rs",  (FSGNJ_D  FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
 def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
 def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
@@ -221,9 +234,6 @@ def : InstAlias<"fgt.d $rd, $rs, $rt",
                 (FLT_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>;
 def : InstAlias<"fge.d $rd, $rs, $rt",
                 (FLE_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>;
-
-def PseudoFLD  : PseudoFloatLoad<"fld", FPR64>;
-def PseudoFSD  : PseudoStore<"fsd", FPR64>;
 } // Predicates = [HasStdExtD]
 
 //===----------------------------------------------------------------------===//
@@ -247,9 +257,15 @@ def : Pat<(fpextend FPR32:$rs1), (FCVT_D_S FPR32:$rs1)>;
 // [u]int<->double conversion patterns must be gated on IsRV32 or IsRV64, so
 // are defined later.
 
+} // Predicates = [HasStdExtD]
+
 /// Float arithmetic operations
+let Predicates = [HasStdExtD, NotSoftFADDDouble] in {
 
 def : PatFpr64Fpr64DynFrm<fadd, FADD_D>;
+} // Predicates = [HasStdExtD, NotSoftFADDDouble]
+
+let Predicates = [HasStdExtD] in {
 def : PatFpr64Fpr64DynFrm<fsub, FSUB_D>;
 def : PatFpr64Fpr64DynFrm<fmul, FMUL_D>;
 def : PatFpr64Fpr64DynFrm<fdiv, FDIV_D>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
index 6b5c9617426a..09f3b2169b33 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
@@ -37,17 +37,17 @@ def riscv_fcvt_wu_rv64
 
 // Floating-point rounding mode
 
-def FRMArg : AsmOperandClass {
-  let Name = "FRMArg";
-  let RenderMethod = "addFRMArgOperands";
-  let DiagnosticType = "InvalidFRMArg";
-}
-
-def frmarg : Operand<XLenVT> {
-  let ParserMatchClass = FRMArg;
-  let PrintMethod = "printFRMArg";
-  let DecoderMethod = "decodeFRMArg";
-}
+//def FRMArg : AsmOperandClass {
+//  let Name = "FRMArg";
+//  let RenderMethod = "addFRMArgOperands";
+//  let DiagnosticType = "InvalidFRMArg";
+//}
+
+//def frmarg : Operand<XLenVT> {
+//  let ParserMatchClass = FRMArg;
+//  let PrintMethod = "printFRMArg";
+//  let DecoderMethod = "decodeFRMArg";
+//}
 
 //===----------------------------------------------------------------------===//
 // Instruction class templates
@@ -78,23 +78,23 @@ class FPALUSDynFrmAlias<FPALUS_rr_frm Inst, string OpcodeStr>
     : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
                 (Inst FPR32:$rd, FPR32:$rs1, FPR32:$rs2, 0b111)>;
 
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-class FPUnaryOp_r<bits<7> funct7, bits<3> funct3, RegisterClass rdty,
-                RegisterClass rs1ty, string opcodestr>
-    : RVInstR<funct7, funct3, OPC_OP_FP, (outs rdty:$rd), (ins rs1ty:$rs1),
-              opcodestr, "$rd, $rs1">;
-
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-class FPUnaryOp_r_frm<bits<7> funct7, RegisterClass rdty, RegisterClass rs1ty,
-                      string opcodestr>
-    : RVInstRFrm<funct7, OPC_OP_FP, (outs rdty:$rd),
-                 (ins rs1ty:$rs1, frmarg:$funct3), opcodestr,
-                  "$rd, $rs1, $funct3">;
-
-class FPUnaryOpDynFrmAlias<FPUnaryOp_r_frm Inst, string OpcodeStr,
-                           RegisterClass rdty, RegisterClass rs1ty>
-    : InstAlias<OpcodeStr#" $rd, $rs1",
-                (Inst rdty:$rd, rs1ty:$rs1, 0b111)>;
+//let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+//class FPUnaryOp_r<bits<7> funct7, bits<3> funct3, RegisterClass rdty,
+//                RegisterClass rs1ty, string opcodestr>
+//    : RVInstR<funct7, funct3, OPC_OP_FP, (outs rdty:$rd), (ins rs1ty:$rs1),
+//              opcodestr, "$rd, $rs1">;
+
+//let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+//class FPUnaryOp_r_frm<bits<7> funct7, RegisterClass rdty, RegisterClass rs1ty,
+//                      string opcodestr>
+//    : RVInstRFrm<funct7, OPC_OP_FP, (outs rdty:$rd),
+//                 (ins rs1ty:$rs1, frmarg:$funct3), opcodestr,
+//                  "$rd, $rs1, $funct3">;
+//
+//class FPUnaryOpDynFrmAlias<FPUnaryOp_r_frm Inst, string OpcodeStr,
+//                           RegisterClass rdty, RegisterClass rs1ty>
+//    : InstAlias<OpcodeStr#" $rd, $rs1",
+//                (Inst rdty:$rd, rs1ty:$rs1, 0b111)>;
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class FPCmpS_rr<bits<3> funct3, string opcodestr>
@@ -254,6 +254,17 @@ def : InstAlias<"fgt.s $rd, $rs, $rt",
 def : InstAlias<"fge.s $rd, $rs, $rt",
                 (FLE_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;
 
+// fmv.w.x and fmv.x.w were previously known as fmv.s.x and fmv.x.s. Both
+// spellings should be supported by standard tools.
+def : MnemonicAlias<"fmv.s.x", "fmv.w.x">;
+def : MnemonicAlias<"fmv.x.s", "fmv.x.w">;
+
+def PseudoFLW  : PseudoFloatLoad<"flw", FPR32>;
+def PseudoFSW  : PseudoStore<"fsw", FPR32>;
+} // Predicates = [HasStdExtF]
+
+
+let Predicates = [HasStdExtFOrDOrZfh] in {
 // The following csr instructions actually alias instructions from the base ISA.
 // However, it only makes sense to support them when the F extension is enabled.
 // NOTE: "frcsr", "frrm", and "frflags" are more specialized version of "csrr".
@@ -278,15 +289,8 @@ def : InstAlias<"fsflags $rd, $rs",   (CSRRW  GPR:$rd, SysRegFFLAGS.Encoding, GP
 def : InstAlias<"fsflags $rs",        (CSRRW       X0, SysRegFFLAGS.Encoding, GPR:$rs), 2>;
 def : InstAlias<"fsflagsi $rd, $imm", (CSRRWI GPR:$rd, SysRegFFLAGS.Encoding, uimm5:$imm)>;
 def : InstAlias<"fsflagsi $imm",      (CSRRWI      X0, SysRegFFLAGS.Encoding, uimm5:$imm), 2>;
+} // Predicates = [HasStdExtFOrDOrZfh]
 
-// fmv.w.x and fmv.x.w were previously known as fmv.s.x and fmv.x.s. Both
-// spellings should be supported by standard tools.
-def : MnemonicAlias<"fmv.s.x", "fmv.w.x">;
-def : MnemonicAlias<"fmv.x.s", "fmv.x.w">;
-
-def PseudoFLW  : PseudoFloatLoad<"flw", FPR32>;
-def PseudoFSW  : PseudoStore<"fsw", FPR32>;
-} // Predicates = [HasStdExtF]
 
 //===----------------------------------------------------------------------===//
 // Pseudo-instructions and codegen patterns
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXfph.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXfph.td
new file mode 100644
index 000000000000..38258b8af822
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXfph.td
@@ -0,0 +1,535 @@
+//===-- RISCVInstrInfoXfph.td - daiteq 'x-fph' instructions -----*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes instructions for daiteq s.r.o. extension 'x-fph'
+// packed half-precision floating-point extension, version 0.1.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// RISC-V specific DAG Nodes.
+//===----------------------------------------------------------------------===//
+
+//def SDT_RISCVFMV_PH_X
+//    : SDTypeProfile<1, 1, [SDTCisVT<0, v2f16>, SDTCisVT<1, XLenVT>]>;
+//def SDT_RISCVFMV_X_ANYEXTPH
+//    : SDTypeProfile<1, 1, [SDTCisVT<0, XLenVT>, SDTCisVT<1, v2f16>]>;
+
+//def riscv_fmv_ph_x
+//    : SDNode<"RISCVISD::FMV_PH_X", SDT_RISCVFMV_PH_X>;
+//def riscv_fmv_x_anyextph
+//    : SDNode<"RISCVISD::FMV_X_ANYEXTPH", SDT_RISCVFMV_X_ANYEXTPH>;
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+
+//let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+//class FPFMAH_rrr_frm<RISCVOpcode opcode, string opcodestr>
+//    : RVInstR4Frm<0b10, opcode, (outs FPR16:$rd),
+//                  (ins FPR16V2:$rs1, FPR16V2:$rs2, FPR16:$rs3, frmarg:$funct3),
+//                  opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">;
+
+//class FPFMAHDynFrmAlias<FPFMAH_rrr_frm Inst, string OpcodeStr>
+//    : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3",
+//                (Inst FPR16:$rd, FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FPALUPH_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR16V2:$rd),
+              (ins FPR16V2:$rs1, FPR16V2:$rs2), opcodestr, "$rd, $rs1, $rs2">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, hasCompleteDecoder = 0 in
+class FPALUH2PH_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR16V2:$rd),
+              (ins FPR16:$rs1, FPR16:$rs2), opcodestr, "$rd, $rs1, $rs2">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FPALUPH_rr_frm<bits<7> funct7, string opcodestr>
+    : RVInstRFrm<funct7, OPC_OP_FP, (outs FPR16V2:$rd),
+                 (ins FPR16V2:$rs1, FPR16V2:$rs2, frmarg:$funct3), opcodestr,
+                  "$rd, $rs1, $rs2, $funct3">;
+
+class FPALUPHDynFrmAlias<FPALUPH_rr_frm Inst, string OpcodeStr>
+    : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
+                (Inst FPR16V2:$rd, FPR16V2:$rs1, FPR16V2:$rs2, 0b111)>;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FPCmpPH_rr<bits<3> funct3, string opcodestr>
+    : RVInstR<0b1010000, funct3, OPC_OP_FP, (outs GPR:$rd),
+              (ins FPR16V2:$rs1, FPR16V2:$rs2), opcodestr, "$rd, $rs1, $rs2">,
+      Sched<[WriteFCmp16v2, ReadFCmp16v2, ReadFCmp16v2]>;
+
+
+//let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+//class FP_PH2PH_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
+//    : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR16V2:$rd),
+//              (ins FPR16V2:$rs1, FPR16V2:$rs2), opcodestr, "$rd, $rs1, $rs2">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FP_H2PH_r<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR16V2:$rd),
+              (ins FPR16:$rs1), opcodestr, "$rd, $rs1">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FP_PH2H_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR16:$rd),
+              (ins FPR16V2:$rs1, FPR16V2:$rs2), opcodestr, "$rd, $rs1, $rs2">;
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+// predicate HasDaiExtXfph
+
+let Predicates = [HasDaiExtXfph] in {
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+def FLPH : RVInstI<0b010, OPC_LOAD_FP, (outs FPR16V2:$rd),
+                  (ins GPR:$rs1, simm12:$imm12),
+                   "flw", "$rd, ${imm12}(${rs1})">,
+          Sched<[WriteFLD16v2, ReadFMemBase]>;
+
+// Operands for stores are in the order srcreg, base, offset rather than
+// reflecting the order these fields are specified in the instruction
+// encoding.
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+def FSPH : RVInstS<0b010, OPC_STORE_FP, (outs),
+                  (ins FPR16V2:$rs2, GPR:$rs1, simm12:$imm12),
+                   "fsw", "$rs2, ${imm12}(${rs1})">,
+          Sched<[WriteFST16v2, ReadStoreData, ReadFMemBase]>;
+
+def FADD_PH : FPALUPH_rr_frm<0b1000000, "fadd.ph">,
+              Sched<[WriteFALU16v2, ReadFALU16v2, ReadFALU16v2]>;
+def         : FPALUPHDynFrmAlias<FADD_PH, "fadd.ph">;
+def FSUB_PH : FPALUPH_rr_frm<0b1000100, "fsub.ph">,
+              Sched<[WriteFALU16v2, ReadFALU16v2, ReadFALU16v2]>;
+def         : FPALUPHDynFrmAlias<FSUB_PH, "fsub.ph">;
+def FMUL_PH : FPALUPH_rr_frm<0b1001000, "fmul.ph">,
+              Sched<[WriteFMul16v2, ReadFMul16v2, ReadFMul16v2]>;
+def         : FPALUPHDynFrmAlias<FMUL_PH, "fmul.ph">;
+def FDIV_PH : FPALUPH_rr_frm<0b1001100, "fdiv.ph">,
+              Sched<[WriteFDiv16v2, ReadFDiv16v2, ReadFDiv16v2]>;
+def         : FPALUPHDynFrmAlias<FDIV_PH, "fdiv.ph">;
+
+def FSQRT_PH : FPUnaryOp_r_frm<0b1101100, FPR16V2, FPR16V2, "fsqrt.ph">,
+               Sched<[WriteFSqrt16v2, ReadFSqrt16v2]> {
+  let rs2 = 0b00000;
+}
+def         : FPUnaryOpDynFrmAlias<FSQRT_PH, "fsqrt.ph", FPR16V2, FPR16V2>;
+
+def FSGNJ_PH  : FPALUPH_rr<0b0010000, 0b100, "fsgnj.ph">,
+                Sched<[WriteFSGNJ16v2, ReadFSGNJ16v2, ReadFSGNJ16v2]>;
+def FSGNJN_PH : FPALUPH_rr<0b0010000, 0b101, "fsgnjn.ph">,
+                Sched<[WriteFSGNJ16v2, ReadFSGNJ16v2, ReadFSGNJ16v2]>;
+def FSGNJX_PH : FPALUPH_rr<0b0010000, 0b110, "fsgnjx.ph">,
+                Sched<[WriteFSGNJ16v2, ReadFSGNJ16v2, ReadFSGNJ16v2]>;
+def FMIN_PH   : FPALUPH_rr<0b0010100, 0b100, "fmin.ph">,
+                Sched<[WriteFMinMax16v2, ReadFMinMax16v2, ReadFMinMax16v2]>;
+def FMAX_PH   : FPALUPH_rr<0b0010100, 0b101, "fmax.ph">,
+                Sched<[WriteFMinMax16v2, ReadFMinMax16v2, ReadFMinMax16v2]>;
+
+def FADDX_PH : FPALUPH_rr_frm<0b0110000, "faddx.ph">,
+               Sched<[WriteFALU16v2, ReadFALU16v2, ReadFALU16v2]>;
+def          : FPALUPHDynFrmAlias<FADDX_PH, "faddx.ph">;
+def FSUBX_PH : FPALUPH_rr_frm<0b0110100, "fsubx.ph">,
+               Sched<[WriteFALU16v2, ReadFALU16v2, ReadFALU16v2]>;
+def          : FPALUPHDynFrmAlias<FSUBX_PH, "fsubx.ph">;
+def FMULX_PH : FPALUPH_rr_frm<0b0111000, "fmulx.ph">,
+               Sched<[WriteFMul16v2, ReadFMul16v2, ReadFMul16v2]>;
+def          : FPALUPHDynFrmAlias<FMULX_PH, "fmulx.ph">;
+def FDIVX_PH : FPALUPH_rr_frm<0b0111100, "fdivx.ph">,
+               Sched<[WriteFDiv16v2, ReadFDiv16v2, ReadFDiv16v2]>;
+def          : FPALUPHDynFrmAlias<FDIVX_PH, "fdivx.ph">;
+
+def FADDR_PH : FPALUPH_rr_frm<0b1010100, "faddr.ph">,
+               Sched<[WriteFALU16v2, ReadFALU16v2, ReadFALU16v2]>;
+def          : FPALUPHDynFrmAlias<FADDR_PH, "faddr.ph">;
+def FSUBR_PH : FPALUPH_rr_frm<0b1011000, "fsubr.ph">,
+               Sched<[WriteFALU16v2, ReadFALU16v2, ReadFALU16v2]>;
+def          : FPALUPHDynFrmAlias<FSUBR_PH, "fsubr.ph">;
+def FMULR_PH : FPALUPH_rr_frm<0b1011100, "fmulr.ph">,
+               Sched<[WriteFMul16v2, ReadFMul16v2, ReadFMul16v2]>;
+def          : FPALUPHDynFrmAlias<FMULR_PH, "fmulr.ph">;
+def FDIVR_PH : FPALUPH_rr_frm<0b1100100, "fdivr.ph">,
+               Sched<[WriteFDiv16v2, ReadFDiv16v2, ReadFDiv16v2]>;
+def          : FPALUPHDynFrmAlias<FDIVR_PH, "fdivr.ph">;
+
+def FADDSUBR_PH : FPALUPH_rr_frm<0b0011000, "faddsubr.ph">,
+                  Sched<[WriteFALU16v2, ReadFALU16v2, ReadFALU16v2]>;
+def             : FPALUPHDynFrmAlias<FADDSUBR_PH, "faddsubr.ph">;
+def FSUBADDR_PH : FPALUPH_rr_frm<0b0011100, "fsubaddr.ph">,
+                  Sched<[WriteFALU16v2, ReadFALU16v2, ReadFALU16v2]>;
+def             : FPALUPHDynFrmAlias<FSUBADDR_PH, "fsubaddr.ph">;
+
+// def FCVT_W_H : FPUnaryOp_r_frm<0b1100010, GPR, FPR16, "fcvt.w.h">,
+//                Sched<[WriteFCvtF16ToI32, ReadFCvtF16ToI32]> {
+//   let rs2 = 0b00000;
+// }
+// def          : FPUnaryOpDynFrmAlias<FCVT_W_H, "fcvt.w.h", GPR, FPR16>;
+//
+// def FCVT_WU_H : FPUnaryOp_r_frm<0b1100010, GPR, FPR16, "fcvt.wu.h">,
+//                 Sched<[WriteFCvtF16ToI32, ReadFCvtF16ToI32]> {
+//   let rs2 = 0b00001;
+// }
+// def           : FPUnaryOpDynFrmAlias<FCVT_WU_H, "fcvt.wu.h", GPR, FPR16>;
+//
+// def FCVT_H_W : FPUnaryOp_r_frm<0b1101010, FPR16, GPR, "fcvt.h.w">,
+//                Sched<[WriteFCvtI32ToF16, ReadFCvtI32ToF16]> {
+//   let rs2 = 0b00000;
+// }
+// def          : FPUnaryOpDynFrmAlias<FCVT_H_W, "fcvt.h.w", FPR16, GPR>;
+//
+// def FCVT_H_WU : FPUnaryOp_r_frm<0b1101010, FPR16, GPR, "fcvt.h.wu">,
+//                 Sched<[WriteFCvtI32ToF16, ReadFCvtI32ToF16]> {
+//   let rs2 = 0b00001;
+// }
+// def           : FPUnaryOpDynFrmAlias<FCVT_H_WU, "fcvt.h.wu", FPR16, GPR>;
+//
+// def FCVT_H_S : FPUnaryOp_r_frm<0b0100010, FPR16, FPR32, "fcvt.h.s">,
+//                Sched<[WriteFCvtF32ToF16, ReadFCvtF32ToF16]> {
+//   let rs2 = 0b00000;
+// }
+// def          : FPUnaryOpDynFrmAlias<FCVT_H_S, "fcvt.h.s", FPR16, FPR32>;
+//
+// def FCVT_S_H : FPUnaryOp_r<0b0100000, 0b000, FPR32, FPR16, "fcvt.s.h">,
+//                Sched<[WriteFCvtF16ToF32, ReadFCvtF16ToF32]> {
+//   let rs2 = 0b00010;
+// }
+//
+// def FMV_X_H : FPUnaryOp_r<0b1110010, 0b000, GPR, FPR16, "fmv.x.h">,
+//               Sched<[WriteFMovF16ToI16, ReadFMovF16ToI16]> {
+//   let rs2 = 0b00000;
+// }
+//
+// def FMV_H_X : FPUnaryOp_r<0b1111010, 0b000, FPR16, GPR, "fmv.h.x">,
+//               Sched<[WriteFMovI16ToF16, ReadFMovI16ToF16]> {
+//   let rs2 = 0b00000;
+// }
+
+// def FMV_X_W : FPUnaryOp_r<0b1110000, 0b000, GPR, FPR32, "fmv.x.w">,
+//               Sched<[WriteFMovF32ToI32, ReadFMovF32ToI32]> {
+//   let rs2 = 0b00000;
+// }
+
+def FMV_X_PH : FPUnaryOp_r<0b1110000, 0b000, GPR, FPR16V2, "fmv.x.ph">,
+              Sched<[WriteFClass16v2, ReadFClass16v2]> {
+  let rs2 = 0b00000;
+}
+
+def FMV_PH_X : FPUnaryOp_r<0b1111000, 0b000, FPR16V2, GPR, "fmv.ph.x">,
+                Sched<[WriteFClass16v2, ReadFClass16v2]> {
+  let rs2 = 0b00000;
+}
+
+
+def FEQ_PH : FPCmpPH_rr<0b110, "feq.ph">;
+def FLT_PH : FPCmpPH_rr<0b101, "flt.ph">;
+def FLE_PH : FPCmpPH_rr<0b100, "fle.ph">;
+
+def FCLASS_PH : FPUnaryOp_r<0b1110000, 0b101, GPR, FPR16V2, "fclass.ph">,
+                Sched<[WriteFClass16v2, ReadFClass16v2]> {
+  let rs2 = 0b00000;
+}
+
+// daiteq - Floating-point packing/unpacking Instructions
+def FMOVUU_PH : FPALUPH_rr<0b1110100, 0b000, "fmvuu.ph">,
+                Sched<[WriteFMov16v2, ReadFMov16v2, ReadFMov16v2]>;
+
+def FMOVLL_PH : FPALUPH_rr<0b1110100, 0b001, "fmvll.ph">,
+                Sched<[WriteFMov16v2, ReadFMov16v2, ReadFMov16v2]>;
+def FMOVLL_H2PH : FPALUH2PH_rr<0b1110100, 0b001, "fmvll.ph">,
+                Sched<[WriteFMov16v2, ReadFMov16v2, ReadFMov16v2]>;
+
+def FMOVUL_PH : FPALUPH_rr<0b1110100, 0b010, "fmvul.ph">,
+                Sched<[WriteFMov16v2, ReadFMov16v2, ReadFMov16v2]>;
+
+def FMOVLU_PH : FPALUPH_rr<0b1110100, 0b011, "fmvlu.ph">,
+                Sched<[WriteFMov16v2, ReadFMov16v2, ReadFMov16v2]>;
+
+def FMOVZU_PH : FPUnaryOp_r<0b1110100, 0b100, FPR16V2, FPR16V2, "fmvzu.ph">,
+                Sched<[WriteFMov16v2, ReadFMov16v2, ReadFMov16v2]> {
+  let rs2 = 0b00000;
+}
+
+def FMOVZL_PH : FPUnaryOp_r<0b1110100, 0b101, FPR16V2, FPR16V2, "fmvzl.ph">,
+                Sched<[WriteFMov16v2, ReadFMov16v2, ReadFMov16v2]> {
+  let rs2 = 0b00000;
+}
+
+def : InstAlias<"fswap.ph $rd, $rs",   (FMOVLU_PH FPR16V2:$rd, FPR16V2:$rs, FPR16V2:$rs)>;
+
+} // Predicates = [HasDaiExtXfph]
+
+def SDT_RISCVFMV_PH_X_RV64
+    : SDTypeProfile<1, 1, [SDTCisVT<0, v2f16>, SDTCisVT<1, i64>]>;
+def riscv_fmv_ph_x_rv64
+    : SDNode<"RISCVISD::FMV_PH_X_RV64", SDT_RISCVFMV_PH_X_RV64>;
+
+def SDT_RISCVFMV_X_ANYEXTPH_RV64
+    : SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, v2f16>]>;
+def riscv_fmv_x_anyextph_rv64
+    : SDNode<"RISCVISD::FMV_X_ANYEXTPH_RV64", SDT_RISCVFMV_X_ANYEXTPH_RV64>;
+
+let Predicates = [HasDaiExtXfph, IsRV32] in {
+// Moves (no conversion)
+def : Pat<(bitconvert (i32 GPR:$rs1)), (FMV_PH_X GPR:$rs1)>;
+def : Pat<(i32 (bitconvert FPR16V2:$rs1)), (FMV_X_PH FPR16V2:$rs1)>;
+}
+let Predicates = [HasDaiExtXfph, IsRV64] in {
+// Moves (no conversion)
+def : Pat<(riscv_fmv_ph_x_rv64 GPR:$src), (FMV_PH_X GPR:$src)>;
+def : Pat<(riscv_fmv_x_anyextph_rv64 FPR16V2:$src), (FMV_X_PH FPR16V2:$src)>;
+def : Pat<(sext_inreg (riscv_fmv_x_anyextph_rv64 FPR16V2:$src), i32),
+          (FMV_X_PH FPR16V2:$src)>;
+}
+
+//
+// let Predicates = [HasStdExtZfh, IsRV64] in {
+// def FCVT_L_H  : FPUnaryOp_r_frm<0b1100010, GPR, FPR16, "fcvt.l.h">,
+//                 Sched<[WriteFCvtF16ToI64, ReadFCvtF16ToI64]> {
+//   let rs2 = 0b00010;
+// }
+// def           : FPUnaryOpDynFrmAlias<FCVT_L_H, "fcvt.l.h", GPR, FPR16>;
+//
+// def FCVT_LU_H  : FPUnaryOp_r_frm<0b1100010, GPR, FPR16, "fcvt.lu.h">,
+//                  Sched<[WriteFCvtF16ToI64, ReadFCvtF16ToI64]> {
+//   let rs2 = 0b00011;
+// }
+// def            : FPUnaryOpDynFrmAlias<FCVT_LU_H, "fcvt.lu.h", GPR, FPR16>;
+//
+// def FCVT_H_L : FPUnaryOp_r_frm<0b1101010, FPR16, GPR, "fcvt.h.l">,
+//                Sched<[WriteFCvtI64ToF16, ReadFCvtI64ToF16]> {
+//   let rs2 = 0b00010;
+// }
+// def          : FPUnaryOpDynFrmAlias<FCVT_H_L, "fcvt.h.l", FPR16, GPR>;
+//
+// def FCVT_H_LU : FPUnaryOp_r_frm<0b1101010, FPR16, GPR, "fcvt.h.lu">,
+//                 Sched<[WriteFCvtI64ToF16, ReadFCvtI64ToF16]> {
+//   let rs2 = 0b00011;
+// }
+// def           : FPUnaryOpDynFrmAlias<FCVT_H_LU, "fcvt.h.lu", FPR16, GPR>;
+// } // Predicates = [HasStdExtZfh, IsRV64]
+//
+// let Predicates = [HasStdExtZfh, HasStdExtD] in {
+// def FCVT_H_D : FPUnaryOp_r_frm<0b0100010, FPR16, FPR64, "fcvt.h.d">,
+//                Sched<[WriteFCvtF64ToF16, ReadFCvtF64ToF16]> {
+//   let rs2 = 0b00001;
+// }
+// def          : FPUnaryOpDynFrmAlias<FCVT_H_D, "fcvt.h.d", FPR16, FPR64>;
+//
+// def FCVT_D_H : FPUnaryOp_r<0b0100001, 0b000, FPR64, FPR16, "fcvt.d.h">,
+//                Sched<[WriteFCvtF16ToF64, ReadFCvtF16ToF64]> {
+//   let rs2 = 0b00010;
+// }
+// } // Predicates = [HasStdExtZfh, HasStdExtD]
+
+//===----------------------------------------------------------------------===//
+// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasDaiExtXfph] in {
+def : InstAlias<"flw $rd, (${rs1})",  (FLPH FPR16V2:$rd,  GPR:$rs1, 0), 0>;
+def : InstAlias<"fsw $rs2, (${rs1})", (FSPH FPR16V2:$rs2, GPR:$rs1, 0), 0>;
+
+def : InstAlias<"fmv.ph $rd, $rs",  (FSGNJ_PH  FPR16V2:$rd, FPR16V2:$rs, FPR16V2:$rs)>;
+def : InstAlias<"fabs.ph $rd, $rs", (FSGNJX_PH FPR16V2:$rd, FPR16V2:$rs, FPR16V2:$rs)>;
+def : InstAlias<"fneg.ph $rd, $rs", (FSGNJN_PH FPR16V2:$rd, FPR16V2:$rs, FPR16V2:$rs)>;
+
+// fgt.h/fge.h are recognised by the GNU assembler but the canonical
+// flt.h/fle.h forms will always be printed. Therefore, set a zero weight.
+def : InstAlias<"fgt.ph $rd, $rs, $rt",
+                (FLT_PH GPR:$rd, FPR16V2:$rt, FPR16V2:$rs), 0>;
+def : InstAlias<"fge.ph $rd, $rs, $rt",
+                (FLE_PH GPR:$rd, FPR16V2:$rt, FPR16V2:$rs), 0>;
+
+def PseudoFLPH  : PseudoFloatLoad<"flw", FPR16V2>;
+def PseudoFSPH  : PseudoStore<"fsw", FPR16V2>;
+
+} // Predicates = [HasDaiExtXfph]
+
+//===----------------------------------------------------------------------===//
+// Pseudo-instructions and codegen patterns
+//===----------------------------------------------------------------------===//
+
+/// Generic pattern classes
+class PatFpr16v2Fpr16v2<SDPatternOperator OpNode, RVInstR Inst>
+    : Pat<(OpNode FPR16V2:$rs1, FPR16V2:$rs2), (Inst $rs1, $rs2)>;
+
+class PatFpr16v2Fpr16v2DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst>
+    : Pat<(OpNode FPR16V2:$rs1, FPR16V2:$rs2), (Inst $rs1, $rs2, 0b111)>;
+
+class PatFpr16v2<SDPatternOperator OpNode, RVInstR Inst>
+    : Pat<(OpNode FPR16V2:$rs1), (Inst $rs1, $rs1)>;
+
+//def SPswapph
+//    : SDTypeProfile<1, 1, [SDTCisVT<0, v2f16>, SDTCisVT<1, v2f16>]>;
+//def riscv_swap_ph
+//    : SDNode<"RISCVISD::SWAPPH", SPswapph>;
+
+def SPmv_ph
+    : SDTypeProfile<1, 2, [SDTCisVT<0, v2f16>, SDTCisVT<1, v2f16>, SDTCisVT<2, v2f16>]>;
+def SPmv_h2ph
+    : SDTypeProfile<1, 2, [SDTCisVT<0, v2f16>, SDTCisVT<1, f16>, SDTCisVT<2, f16>]>;
+def riscv_mvul_ph
+    : SDNode<"RISCVISD::MVULPH", SPmv_ph>;
+def riscv_mvlu_ph
+    : SDNode<"RISCVISD::MVLUPH", SPmv_ph>;
+def riscv_mvll_ph
+    : SDNode<"RISCVISD::MVLLPH", SPmv_ph>;
+def riscv_mvuu_ph
+    : SDNode<"RISCVISD::MVUUPH", SPmv_ph>;
+
+def riscv_mvll_h2ph
+    : SDNode<"RISCVISD::MVLL_SINGLE2PACK_PH", SPmv_h2ph>;
+
+let Predicates = [HasDaiExtXfph] in {
+
+// /// Float constants
+// def : Pat<(f16 (fpimm0)), (FMV_H_X X0)>;
+//
+// /// Float conversion operations
+//
+// // [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
+// // are defined later.
+//
+/// Float arithmetic operations
+
+def : PatFpr16v2Fpr16v2DynFrm<fadd, FADD_PH>;
+def : PatFpr16v2Fpr16v2DynFrm<fsub, FSUB_PH>;
+def : PatFpr16v2Fpr16v2DynFrm<fmul, FMUL_PH>;
+def : PatFpr16v2Fpr16v2DynFrm<fdiv, FDIV_PH>;
+
+def : Pat<(fsqrt FPR16V2:$rs1), (FSQRT_PH FPR16V2:$rs1, 0b111)>;
+
+def : Pat<(fneg FPR16V2:$rs1), (FSGNJN_PH $rs1, $rs1)>;
+def : Pat<(fabs FPR16V2:$rs1), (FSGNJX_PH $rs1, $rs1)>;
+
+def : PatFpr16v2Fpr16v2<fcopysign, FSGNJ_PH>;
+def : Pat<(fcopysign FPR16V2:$rs1, (fneg FPR16V2:$rs2)), (FSGNJN_PH $rs1, $rs2)>;
+// def : Pat<(fcopysign FPR16:$rs1, FPR32:$rs2),
+//           (FSGNJ_H $rs1, (FCVT_H_S $rs2, 0b111))>;
+// def : Pat<(fcopysign FPR32:$rs1, FPR16:$rs2), (FSGNJ_S $rs1, (FCVT_S_H $rs2))>;
+//
+// // fmadd: rs1 * rs2 + rs3
+// def : Pat<(fma FPR16:$rs1, FPR16:$rs2, FPR16:$rs3),
+//           (FMADD_H $rs1, $rs2, $rs3, 0b111)>;
+//
+// // fmsub: rs1 * rs2 - rs3
+// def : Pat<(fma FPR16:$rs1, FPR16:$rs2, (fneg FPR16:$rs3)),
+//           (FMSUB_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>;
+//
+// // fnmsub: -rs1 * rs2 + rs3
+// def : Pat<(fma (fneg FPR16:$rs1), FPR16:$rs2, FPR16:$rs3),
+//           (FNMSUB_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>;
+//
+// // fnmadd: -rs1 * rs2 - rs3
+// def : Pat<(fma (fneg FPR16:$rs1), FPR16:$rs2, (fneg FPR16:$rs3)),
+//           (FNMADD_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>;
+//
+// The ratified 20191213 ISA spec defines fmin and fmax in a way that matches
+// LLVM's fminnum and fmaxnum
+// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>.
+def : PatFpr16v2Fpr16v2<fminnum, FMIN_PH>;
+def : PatFpr16v2Fpr16v2<fmaxnum, FMAX_PH>;
+
+/// Setcc
+
+def : PatFpr16v2Fpr16v2<seteq, FEQ_PH>;
+def : PatFpr16v2Fpr16v2<setoeq, FEQ_PH>;
+def : PatFpr16v2Fpr16v2<setlt, FLT_PH>;
+def : PatFpr16v2Fpr16v2<setolt, FLT_PH>;
+def : PatFpr16v2Fpr16v2<setle, FLE_PH>;
+def : PatFpr16v2Fpr16v2<setole, FLE_PH>;
+
+def Select_FPR16V2_Using_CC_GPR : SelectCC_rrirr<FPR16V2, GPR>;
+
+/// Loads
+
+defm : LdPat<load, FLPH, v2f16>;
+
+/// Stores
+
+defm : StPat<store, FSPH, FPR16V2, v2f16>;
+
+// MOVs
+//def : PatFpr16v2Fpr16v2<SPmovhuu, FMOVUU_PH>;
+//def : PatFpr16v2Fpr16v2<SPmovhll, FMOVLL_PH>;
+
+//def : Pat<(riscv_swap_ph FPR16V2:$rs1), (FSWAP_PH FPR16V2:$rs1)>;
+
+def : Pat<(riscv_mvul_ph FPR16V2:$rs1,FPR16V2:$rs2), (FMOVUL_PH FPR16V2:$rs1,FPR16V2:$rs2)>;
+def : Pat<(riscv_mvlu_ph FPR16V2:$rs1,FPR16V2:$rs2), (FMOVLU_PH FPR16V2:$rs1,FPR16V2:$rs2)>;
+def : Pat<(riscv_mvll_ph FPR16V2:$rs1,FPR16V2:$rs2), (FMOVLL_PH FPR16V2:$rs1,FPR16V2:$rs2)>;
+def : Pat<(riscv_mvuu_ph FPR16V2:$rs1,FPR16V2:$rs2), (FMOVUU_PH FPR16V2:$rs1,FPR16V2:$rs2)>;
+
+def : Pat<(riscv_mvll_h2ph FPR16:$rs1,FPR16:$rs2), (FMOVLL_H2PH FPR16:$rs1,FPR16:$rs2)>;
+
+// /// Float conversion operations
+//
+// // f32 -> f16, f16 -> f32
+// def : Pat<(fpround FPR32:$rs1), (FCVT_H_S FPR32:$rs1, 0b111)>;
+// def : Pat<(fpextend FPR16:$rs1), (FCVT_S_H FPR16:$rs1)>;
+//
+// // Moves (no conversion)
+// def : Pat<(riscv_fmv_h_x GPR:$src), (FMV_H_X GPR:$src)>;
+// def : Pat<(riscv_fmv_x_anyexth FPR16:$src), (FMV_X_H FPR16:$src)>;
+} // Predicates = [HasDaiExtXfph]
+
+// let Predicates = [HasStdExtZfh, IsRV32] in {
+// // half->[u]int. Round-to-zero must be used.
+// def : Pat<(i32 (fp_to_sint FPR16:$rs1)), (FCVT_W_H $rs1, 0b001)>;
+// def : Pat<(i32 (fp_to_uint FPR16:$rs1)), (FCVT_WU_H $rs1, 0b001)>;
+//
+// // half->int32 with current rounding mode.
+// def : Pat<(i32 (lrint FPR16:$rs1)), (FCVT_W_H $rs1, 0b111)>;
+//
+// // half->int32 rounded to nearest with ties rounded away from zero.
+// def : Pat<(i32 (lround FPR16:$rs1)), (FCVT_W_H $rs1, 0b100)>;
+//
+// // [u]int->half. Match GCC and default to using dynamic rounding mode.
+// def : Pat<(sint_to_fp (i32 GPR:$rs1)), (FCVT_H_W $rs1, 0b111)>;
+// def : Pat<(uint_to_fp (i32 GPR:$rs1)), (FCVT_H_WU $rs1, 0b111)>;
+// } // Predicates = [HasStdExtZfh, IsRV32]
+//
+// let Predicates = [HasStdExtZfh, IsRV64] in {
+// // Use target specific isd nodes to help us remember the result is sign
+// // extended. Matching sext_inreg+fptoui/fptosi may cause the conversion to be
+// // duplicated if it has another user that didn't need the sign_extend.
+// def : Pat<(riscv_fcvt_w_rv64 FPR16:$rs1),  (FCVT_W_H $rs1, 0b001)>;
+// def : Pat<(riscv_fcvt_wu_rv64 FPR16:$rs1), (FCVT_WU_H $rs1, 0b001)>;
+//
+// // half->[u]int64. Round-to-zero must be used.
+// def : Pat<(i64 (fp_to_sint FPR16:$rs1)), (FCVT_L_H $rs1, 0b001)>;
+// def : Pat<(i64 (fp_to_uint FPR16:$rs1)), (FCVT_LU_H $rs1, 0b001)>;
+//
+// // half->int64 with current rounding mode.
+// def : Pat<(i64 (lrint FPR16:$rs1)), (FCVT_L_H $rs1, 0b111)>;
+// def : Pat<(i64 (llrint FPR16:$rs1)), (FCVT_L_H $rs1, 0b111)>;
+//
+// // half->int64 rounded to nearest with ties rounded away from zero.
+// def : Pat<(i64 (lround FPR16:$rs1)), (FCVT_L_H $rs1, 0b100)>;
+// def : Pat<(i64 (llround FPR16:$rs1)), (FCVT_L_H $rs1, 0b100)>;
+//
+// // [u]int->fp. Match GCC and default to using dynamic rounding mode.
+// def : Pat<(sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_H_W $rs1, 0b111)>;
+// def : Pat<(uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_H_WU $rs1, 0b111)>;
+// def : Pat<(sint_to_fp (i64 GPR:$rs1)), (FCVT_H_L $rs1, 0b111)>;
+// def : Pat<(uint_to_fp (i64 GPR:$rs1)), (FCVT_H_LU $rs1, 0b111)>;
+// } // Predicates = [HasStdExtZfh, IsRV64]
+//
+// let Predicates = [HasStdExtZfh, HasStdExtD] in {
+// /// Float conversion operations
+// // f64 -> f16, f16 -> f64
+// def : Pat<(fpround FPR64:$rs1), (FCVT_H_D FPR64:$rs1, 0b111)>;
+// def : Pat<(fpextend FPR16:$rs1), (FCVT_D_H FPR16:$rs1)>;
+//
+// /// Float arithmetic operations
+// def : Pat<(fcopysign FPR16:$rs1, FPR64:$rs2),
+//           (FSGNJ_H $rs1, (FCVT_H_D $rs2, 0b111))>;
+// def : Pat<(fcopysign FPR64:$rs1, FPR16:$rs2), (FSGNJ_D $rs1, (FCVT_D_H $rs2))>;
+// }
+//
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXfps.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXfps.td
new file mode 100644
index 000000000000..3bf9cd32f0a2
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXfps.td
@@ -0,0 +1,448 @@
+//===-- RISCVInstrInfoXfps.td - daiteq 'x-fps' instructions -----*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes instructions for daiteq s.r.o. extension 'x-fps'
+// packed single-precision floating-point extension, version 0.1.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// RISC-V specific DAG Nodes.
+//===----------------------------------------------------------------------===//
+
+def SDT_RISCVFMV_PS_X_RV64
+    : SDTypeProfile<1, 1, [SDTCisVT<0, v2f32>, SDTCisVT<1, i64>]>;
+def riscv_fmv_ps_x_rv64
+    : SDNode<"RISCVISD::FMV_PS_X_RV64", SDT_RISCVFMV_PS_X_RV64>;
+
+def SDT_RISCVFMV_X_PS_RV64
+    : SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, v2f32>]>;
+def riscv_fmv_x_ps_rv64
+    : SDNode<"RISCVISD::FMV_X_PS_RV64", SDT_RISCVFMV_X_PS_RV64>;
+
+//def SPswapps
+//    : SDTypeProfile<1, 1, [SDTCisVT<0, v2f32>, SDTCisVT<1, v2f32>]>;
+//def riscv_swap_ps
+//    : SDNode<"RISCVISD::SWAPPS", SPswapps>;
+
+def SPmv_ps
+    : SDTypeProfile<1, 2, [SDTCisVT<0, v2f32>, SDTCisVT<1, v2f32>, SDTCisVT<2, v2f32>]>;
+def SPmv_s2ps
+    : SDTypeProfile<1, 2, [SDTCisVT<0, v2f32>, SDTCisVT<1, f32>, SDTCisVT<2, f32>]>;
+def riscv_mvul_ps
+    : SDNode<"RISCVISD::MVULPS", SPmv_ps>;
+def riscv_mvlu_ps
+    : SDNode<"RISCVISD::MVLUPS", SPmv_ps>;
+def riscv_mvll_ps
+    : SDNode<"RISCVISD::MVLLPS", SPmv_ps>;
+def riscv_mvuu_ps
+    : SDNode<"RISCVISD::MVUUPS", SPmv_ps>;
+
+def riscv_mvll_s2ps
+    : SDNode<"RISCVISD::MVLL_SINGLE2PACK_PS", SPmv_s2ps>;
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FPALUPS_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR32V2:$rd),
+              (ins FPR32V2:$rs1, FPR32V2:$rs2), opcodestr, "$rd, $rs1, $rs2">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, hasCompleteDecoder = 0 in
+class FPALUS2PS_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR32V2:$rd),
+              (ins FPR32:$rs1, FPR32:$rs2), opcodestr, "$rd, $rs1, $rs2">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FPALUPS_rr_frm<bits<7> funct7, string opcodestr>
+    : RVInstRFrm<funct7, OPC_OP_FP, (outs FPR32V2:$rd),
+                 (ins FPR32V2:$rs1, FPR32V2:$rs2, frmarg:$funct3), opcodestr,
+                  "$rd, $rs1, $rs2, $funct3">;
+
+class FPALUPSDynFrmAlias<FPALUPS_rr_frm Inst, string OpcodeStr>
+    : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
+                (Inst FPR32V2:$rd, FPR32V2:$rs1, FPR32V2:$rs2, 0b111)>;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FPCmpPS_rr<bits<3> funct3, string opcodestr>
+    : RVInstR<0b1010001, funct3, OPC_OP_FP, (outs GPR:$rd),
+              (ins FPR32V2:$rs1, FPR32V2:$rs2), opcodestr, "$rd, $rs1, $rs2">,
+      Sched<[WriteFCmp16v2, ReadFCmp16v2, ReadFCmp16v2]>;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FP_S2PS_r<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR32V2:$rd),
+              (ins FPR32:$rs1), opcodestr, "$rd, $rs1">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FP_PS2S_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR32:$rd),
+              (ins FPR32V2:$rs1, FPR32V2:$rs2), opcodestr, "$rd, $rs1, $rs2">;
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+// predicate HasDaiExtXfps
+
+let Predicates = [HasDaiExtXfps] in {
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+def FLPS : RVInstI<0b011, OPC_LOAD_FP, (outs FPR32V2:$rd),
+                  (ins GPR:$rs1, simm12:$imm12),
+                   "flps", "$rd, ${imm12}(${rs1})">,
+          Sched<[WriteFLD16v2, ReadFMemBase]>;
+
+// Operands for stores are in the order srcreg, base, offset rather than
+// reflecting the order these fields are specified in the instruction
+// encoding.
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+def FSPS : RVInstS<0b011, OPC_STORE_FP, (outs),
+                  (ins FPR32V2:$rs2, GPR:$rs1, simm12:$imm12),
+                   "fsps", "$rs2, ${imm12}(${rs1})">,
+          Sched<[WriteFST16v2, ReadStoreData, ReadFMemBase]>;
+
+def FADD_PS : FPALUPS_rr_frm<0b1000001, "fadd.ps">,
+              Sched<[WriteFALU16v2, ReadFALU16v2, ReadFALU16v2]>;
+def         : FPALUPSDynFrmAlias<FADD_PS, "fadd.ps">;
+def FSUB_PS : FPALUPS_rr_frm<0b1000101, "fsub.ps">,
+              Sched<[WriteFALU16v2, ReadFALU16v2, ReadFALU16v2]>;
+def         : FPALUPSDynFrmAlias<FSUB_PS, "fsub.ps">;
+def FMUL_PS : FPALUPS_rr_frm<0b1001001, "fmul.ps">,
+              Sched<[WriteFMul16v2, ReadFMul16v2, ReadFMul16v2]>;
+def         : FPALUPSDynFrmAlias<FMUL_PS, "fmul.ps">;
+def FDIV_PS : FPALUPS_rr_frm<0b1001101, "fdiv.ps">,
+              Sched<[WriteFDiv16v2, ReadFDiv16v2, ReadFDiv16v2]>;
+def         : FPALUPSDynFrmAlias<FDIV_PS, "fdiv.ps">;
+
+def FSQRT_PS : FPUnaryOp_r_frm<0b1101101, FPR32V2, FPR32V2, "fsqrt.ps">,
+               Sched<[WriteFSqrt16v2, ReadFSqrt16v2]> {
+  let rs2 = 0b00000;
+}
+def         : FPUnaryOpDynFrmAlias<FSQRT_PS, "fsqrt.ps", FPR32V2, FPR32V2>;
+
+def FSGNJ_PS  : FPALUPS_rr<0b0010001, 0b100, "fsgnj.ps">,
+                Sched<[WriteFSGNJ16v2, ReadFSGNJ16v2, ReadFSGNJ16v2]>;
+def FSGNJN_PS : FPALUPS_rr<0b0010001, 0b101, "fsgnjn.ps">,
+                Sched<[WriteFSGNJ16v2, ReadFSGNJ16v2, ReadFSGNJ16v2]>;
+def FSGNJX_PS : FPALUPS_rr<0b0010001, 0b110, "fsgnjx.ps">,
+                Sched<[WriteFSGNJ16v2, ReadFSGNJ16v2, ReadFSGNJ16v2]>;
+def FMIN_PS   : FPALUPS_rr<0b0010101, 0b100, "fmin.ps">,
+                Sched<[WriteFMinMax16v2, ReadFMinMax16v2, ReadFMinMax16v2]>;
+def FMAX_PS   : FPALUPS_rr<0b0010101, 0b101, "fmax.ps">,
+                Sched<[WriteFMinMax16v2, ReadFMinMax16v2, ReadFMinMax16v2]>;
+
+def FADDX_PS : FPALUPS_rr_frm<0b0110001, "faddx.ps">,
+               Sched<[WriteFALU16v2, ReadFALU16v2, ReadFALU16v2]>;
+def          : FPALUPSDynFrmAlias<FADDX_PS, "faddx.ps">;
+def FSUBX_PS : FPALUPS_rr_frm<0b0110101, "fsubx.ps">,
+               Sched<[WriteFALU16v2, ReadFALU16v2, ReadFALU16v2]>;
+def          : FPALUPSDynFrmAlias<FSUBX_PS, "fsubx.ps">;
+def FMULX_PS : FPALUPS_rr_frm<0b0111001, "fmulx.ps">,
+               Sched<[WriteFMul16v2, ReadFMul16v2, ReadFMul16v2]>;
+def          : FPALUPSDynFrmAlias<FMULX_PS, "fmulx.ps">;
+def FDIVX_PS : FPALUPS_rr_frm<0b0111101, "fdivx.ps">,
+               Sched<[WriteFDiv16v2, ReadFDiv16v2, ReadFDiv16v2]>;
+def          : FPALUPSDynFrmAlias<FDIVX_PS, "fdivx.ps">;
+
+def FADDR_PS : FPALUPS_rr_frm<0b1010101, "faddr.ps">,
+               Sched<[WriteFALU16v2, ReadFALU16v2, ReadFALU16v2]>;
+def          : FPALUPSDynFrmAlias<FADDR_PS, "faddr.ps">;
+def FSUBR_PS : FPALUPS_rr_frm<0b1011001, "fsubr.ps">,
+               Sched<[WriteFALU16v2, ReadFALU16v2, ReadFALU16v2]>;
+def          : FPALUPSDynFrmAlias<FSUBR_PS, "fsubr.ps">;
+def FMULR_PS : FPALUPS_rr_frm<0b1011101, "fmulr.ps">,
+               Sched<[WriteFMul16v2, ReadFMul16v2, ReadFMul16v2]>;
+def          : FPALUPSDynFrmAlias<FMULR_PS, "fmulr.ps">;
+def FDIVR_PS : FPALUPS_rr_frm<0b1100101, "fdivr.ps">,
+               Sched<[WriteFDiv16v2, ReadFDiv16v2, ReadFDiv16v2]>;
+def          : FPALUPSDynFrmAlias<FDIVR_PS, "fdivr.ps">;
+
+def FADDSUBR_PS : FPALUPS_rr_frm<0b0011001, "faddsubr.ps">,
+                  Sched<[WriteFALU16v2, ReadFALU16v2, ReadFALU16v2]>;
+def             : FPALUPSDynFrmAlias<FADDSUBR_PS, "faddsubr.ps">;
+def FSUBADDR_PS : FPALUPS_rr_frm<0b0011101, "fsubaddr.ps">,
+                  Sched<[WriteFALU16v2, ReadFALU16v2, ReadFALU16v2]>;
+def             : FPALUPSDynFrmAlias<FSUBADDR_PS, "fsubaddr.ps">;
+
+
+def FMV_X_PS : FPUnaryOp_r<0b1110001, 0b000, GPR, FPR32V2, "fmv.x.ps">,
+              Sched<[WriteFClass16v2, ReadFClass16v2]> {
+  let rs2 = 0b00000;
+}
+
+def FMV_PS_X : FPUnaryOp_r<0b1111001, 0b000, FPR32V2, GPR, "fmv.ps.x">,
+                Sched<[WriteFClass16v2, ReadFClass16v2]> {
+  let rs2 = 0b00000;
+}
+
+
+def FEQ_PS : FPCmpPS_rr<0b110, "feq.ps">;
+def FLT_PS : FPCmpPS_rr<0b101, "flt.ps">;
+def FLE_PS : FPCmpPS_rr<0b100, "fle.ps">;
+
+def FCLASS_PS : FPUnaryOp_r<0b1110001, 0b101, GPR, FPR32V2, "fclass.ps">,
+                Sched<[WriteFClass16v2, ReadFClass16v2]> {
+  let rs2 = 0b00000;
+}
+
+// daiteq - Floating-point packing/unpacking Instructions
+def FMOVUU_PS : FPALUPS_rr<0b1110101, 0b000, "fmvuu.ps">,
+                Sched<[WriteFMov16v2, ReadFMov16v2, ReadFMov16v2]>;
+
+def FMOVLL_PS : FPALUPS_rr<0b1110101, 0b001, "fmvll.ps">,
+                Sched<[WriteFMov16v2, ReadFMov16v2, ReadFMov16v2]>;
+def FMOVLL_S2PS : FPALUS2PS_rr<0b1110101, 0b001, "fmvll.ps">,
+                Sched<[WriteFMov16v2, ReadFMov16v2, ReadFMov16v2]>;
+
+def FMOVUL_PS : FPALUPS_rr<0b1110101, 0b010, "fmvul.ps">,
+                Sched<[WriteFMov16v2, ReadFMov16v2, ReadFMov16v2]>;
+
+def FMOVLU_PS : FPALUPS_rr<0b1110101, 0b011, "fmvlu.ps">,
+                Sched<[WriteFMov16v2, ReadFMov16v2, ReadFMov16v2]>;
+
+def FMOVZU_PS : FPUnaryOp_r<0b1110101, 0b100, FPR32V2, FPR32V2, "fmvzu.ps">,
+                Sched<[WriteFMov16v2, ReadFMov16v2, ReadFMov16v2]> {
+  let rs2 = 0b00000;
+}
+
+def FMOVZL_PS : FPUnaryOp_r<0b1110101, 0b101, FPR32V2, FPR32V2, "fmvzl.ps">,
+                Sched<[WriteFMov16v2, ReadFMov16v2, ReadFMov16v2]> {
+  let rs2 = 0b00000;
+}
+
+def : InstAlias<"fswap.ps $rd, $rs",   (FMOVLU_PS FPR32V2:$rd, FPR32V2:$rs, FPR32V2:$rs)>;
+
+} // Predicates = [HasDaiExtXfps]
+
+
+let Predicates = [HasDaiExtXfps, IsRV64] in {
+// Moves (no conversion)
+def : Pat<(bitconvert (i64 GPR:$rs1)), (FMV_PS_X GPR:$rs1)>;
+def : Pat<(i64 (bitconvert FPR32V2:$rs1)), (FMV_X_PS FPR32V2:$rs1)>;
+}
+
+let Predicates = [HasDaiExtXfps, IsRV64] in {
+// Moves (no conversion)
+def : Pat<(riscv_fmv_ps_x_rv64 GPR:$src), (FMV_PS_X GPR:$src)>;
+def : Pat<(riscv_fmv_x_ps_rv64 FPR32V2:$src), (FMV_X_PS FPR32V2:$src)>;
+}
+
+//
+// let Predicates = [HasStdExtZfh, IsRV64] in {
+// def FCVT_L_H  : FPUnaryOp_r_frm<0b1100010, GPR, FPR16, "fcvt.l.h">,
+//                 Sched<[WriteFCvtF16ToI64, ReadFCvtF16ToI64]> {
+//   let rs2 = 0b00010;
+// }
+// def           : FPUnaryOpDynFrmAlias<FCVT_L_H, "fcvt.l.h", GPR, FPR16>;
+//
+// def FCVT_LU_H  : FPUnaryOp_r_frm<0b1100010, GPR, FPR16, "fcvt.lu.h">,
+//                  Sched<[WriteFCvtF16ToI64, ReadFCvtF16ToI64]> {
+//   let rs2 = 0b00011;
+// }
+// def            : FPUnaryOpDynFrmAlias<FCVT_LU_H, "fcvt.lu.h", GPR, FPR16>;
+//
+// def FCVT_H_L : FPUnaryOp_r_frm<0b1101010, FPR16, GPR, "fcvt.h.l">,
+//                Sched<[WriteFCvtI64ToF16, ReadFCvtI64ToF16]> {
+//   let rs2 = 0b00010;
+// }
+// def          : FPUnaryOpDynFrmAlias<FCVT_H_L, "fcvt.h.l", FPR16, GPR>;
+//
+// def FCVT_H_LU : FPUnaryOp_r_frm<0b1101010, FPR16, GPR, "fcvt.h.lu">,
+//                 Sched<[WriteFCvtI64ToF16, ReadFCvtI64ToF16]> {
+//   let rs2 = 0b00011;
+// }
+// def           : FPUnaryOpDynFrmAlias<FCVT_H_LU, "fcvt.h.lu", FPR16, GPR>;
+// } // Predicates = [HasStdExtZfh, IsRV64]
+//
+// let Predicates = [HasStdExtZfh, HasStdExtD] in {
+// def FCVT_H_D : FPUnaryOp_r_frm<0b0100010, FPR16, FPR64, "fcvt.h.d">,
+//                Sched<[WriteFCvtF64ToF16, ReadFCvtF64ToF16]> {
+//   let rs2 = 0b00001;
+// }
+// def          : FPUnaryOpDynFrmAlias<FCVT_H_D, "fcvt.h.d", FPR16, FPR64>;
+//
+// def FCVT_D_H : FPUnaryOp_r<0b0100001, 0b000, FPR64, FPR16, "fcvt.d.h">,
+//                Sched<[WriteFCvtF16ToF64, ReadFCvtF16ToF64]> {
+//   let rs2 = 0b00010;
+// }
+// } // Predicates = [HasStdExtZfh, HasStdExtD]
+
+//===----------------------------------------------------------------------===//
+// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasDaiExtXfps] in {
+def : InstAlias<"flps $rd, (${rs1})",  (FLPS FPR32V2:$rd,  GPR:$rs1, 0), 0>;
+def : InstAlias<"fsps $rs2, (${rs1})", (FSPS FPR32V2:$rs2, GPR:$rs1, 0), 0>;
+
+def : InstAlias<"fmv.ps $rd, $rs",  (FSGNJ_PS  FPR32V2:$rd, FPR32V2:$rs, FPR32V2:$rs)>;
+def : InstAlias<"fabs.ps $rd, $rs", (FSGNJX_PS FPR32V2:$rd, FPR32V2:$rs, FPR32V2:$rs)>;
+def : InstAlias<"fneg.ps $rd, $rs", (FSGNJN_PS FPR32V2:$rd, FPR32V2:$rs, FPR32V2:$rs)>;
+
+// fgt.h/fge.h are recognised by the GNU assembler but the canonical
+// flt.h/fle.h forms will always be printed. Therefore, set a zero weight.
+def : InstAlias<"fgt.ps $rd, $rs, $rt",
+                (FLT_PS GPR:$rd, FPR32V2:$rt, FPR32V2:$rs), 0>;
+def : InstAlias<"fge.ps $rd, $rs, $rt",
+                (FLE_PS GPR:$rd, FPR32V2:$rt, FPR32V2:$rs), 0>;
+
+def PseudoFLPS  : PseudoFloatLoad<"flps", FPR32V2>;
+def PseudoFSPS  : PseudoStore<"fsps", FPR32V2>;
+
+} // Predicates = [HasDaiExtXfps]
+
+//===----------------------------------------------------------------------===//
+// Pseudo-instructions and codegen patterns
+//===----------------------------------------------------------------------===//
+
+/// Generic pattern classes
+class PatFpr32v2Fpr32v2<SDPatternOperator OpNode, RVInstR Inst>
+    : Pat<(OpNode FPR32V2:$rs1, FPR32V2:$rs2), (Inst $rs1, $rs2)>;
+
+class PatFpr32v2Fpr32v2DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst>
+    : Pat<(OpNode FPR32V2:$rs1, FPR32V2:$rs2), (Inst $rs1, $rs2, 0b111)>;
+
+class PatFpr32v2<SDPatternOperator OpNode, RVInstR Inst>
+    : Pat<(OpNode FPR32V2:$rs1), (Inst $rs1, $rs1)>;
+
+let Predicates = [HasDaiExtXfps] in {
+
+def : PatFpr32v2Fpr32v2DynFrm<fadd, FADD_PS>;
+def : PatFpr32v2Fpr32v2DynFrm<fsub, FSUB_PS>;
+def : PatFpr32v2Fpr32v2DynFrm<fmul, FMUL_PS>;
+def : PatFpr32v2Fpr32v2DynFrm<fdiv, FDIV_PS>;
+
+def : Pat<(fsqrt FPR32V2:$rs1), (FSQRT_PS FPR32V2:$rs1, 0b111)>;
+
+def : Pat<(fneg FPR32V2:$rs1), (FSGNJN_PS $rs1, $rs1)>;
+def : Pat<(fabs FPR32V2:$rs1), (FSGNJX_PS $rs1, $rs1)>;
+
+def : PatFpr32v2Fpr32v2<fcopysign, FSGNJ_PS>;
+def : Pat<(fcopysign FPR32V2:$rs1, (fneg FPR32V2:$rs2)), (FSGNJN_PS $rs1, $rs2)>;
+// def : Pat<(fcopysign FPR16:$rs1, FPR32:$rs2),
+//           (FSGNJ_H $rs1, (FCVT_H_S $rs2, 0b111))>;
+// def : Pat<(fcopysign FPR32:$rs1, FPR16:$rs2), (FSGNJ_S $rs1, (FCVT_S_H $rs2))>;
+//
+// // fmadd: rs1 * rs2 + rs3
+// def : Pat<(fma FPR16:$rs1, FPR16:$rs2, FPR16:$rs3),
+//           (FMADD_H $rs1, $rs2, $rs3, 0b111)>;
+//
+// // fmsub: rs1 * rs2 - rs3
+// def : Pat<(fma FPR16:$rs1, FPR16:$rs2, (fneg FPR16:$rs3)),
+//           (FMSUB_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>;
+//
+// // fnmsub: -rs1 * rs2 + rs3
+// def : Pat<(fma (fneg FPR16:$rs1), FPR16:$rs2, FPR16:$rs3),
+//           (FNMSUB_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>;
+//
+// // fnmadd: -rs1 * rs2 - rs3
+// def : Pat<(fma (fneg FPR16:$rs1), FPR16:$rs2, (fneg FPR16:$rs3)),
+//           (FNMADD_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>;
+//
+// The ratified 20191213 ISA spec defines fmin and fmax in a way that matches
+// LLVM's fminnum and fmaxnum
+// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>.
+
+def : PatFpr32v2Fpr32v2<fminnum, FMIN_PS>;
+def : PatFpr32v2Fpr32v2<fmaxnum, FMAX_PS>;
+
+/// Setcc
+
+def : PatFpr32v2Fpr32v2<seteq, FEQ_PS>;
+def : PatFpr32v2Fpr32v2<setoeq, FEQ_PS>;
+def : PatFpr32v2Fpr32v2<setlt, FLT_PS>;
+def : PatFpr32v2Fpr32v2<setolt, FLT_PS>;
+def : PatFpr32v2Fpr32v2<setle, FLE_PS>;
+def : PatFpr32v2Fpr32v2<setole, FLE_PS>;
+
+def Select_FPR32V2_Using_CC_GPR : SelectCC_rrirr<FPR32V2, GPR>;
+
+/// Loads
+
+defm : LdPat<load, FLPS, v2f32>;
+
+/// Stores
+
+defm : StPat<store, FSPS, FPR32V2, v2f32>;
+
+// MOVs
+//def : Pat<(riscv_swap_ps FPR32V2:$rs1), (FSWAP_PS FPR32V2:$rs1)>;
+
+def : Pat<(riscv_mvul_ps FPR32V2:$rs1,FPR32V2:$rs2), (FMOVUL_PS FPR32V2:$rs1,FPR32V2:$rs2)>;
+def : Pat<(riscv_mvlu_ps FPR32V2:$rs1,FPR32V2:$rs2), (FMOVLU_PS FPR32V2:$rs1,FPR32V2:$rs2)>;
+def : Pat<(riscv_mvll_ps FPR32V2:$rs1,FPR32V2:$rs2), (FMOVLL_PS FPR32V2:$rs1,FPR32V2:$rs2)>;
+def : Pat<(riscv_mvuu_ps FPR32V2:$rs1,FPR32V2:$rs2), (FMOVUU_PS FPR32V2:$rs1,FPR32V2:$rs2)>;
+
+def : Pat<(riscv_mvll_s2ps FPR32:$rs1,FPR32:$rs2), (FMOVLL_S2PS FPR32:$rs1,FPR32:$rs2)>;
+
+// /// Float conversion operations
+//
+// // f32 -> f16, f16 -> f32
+// def : Pat<(fpround FPR32:$rs1), (FCVT_H_S FPR32:$rs1, 0b111)>;
+// def : Pat<(fpextend FPR16:$rs1), (FCVT_S_H FPR16:$rs1)>;
+//
+// // Moves (no conversion)
+// def : Pat<(riscv_fmv_h_x GPR:$src), (FMV_H_X GPR:$src)>;
+// def : Pat<(riscv_fmv_x_anyexth FPR16:$src), (FMV_X_H FPR16:$src)>;
+} // Predicates = [HasDaiExtXfps]
+
+// let Predicates = [HasStdExtZfh, IsRV32] in {
+// // half->[u]int. Round-to-zero must be used.
+// def : Pat<(i32 (fp_to_sint FPR16:$rs1)), (FCVT_W_H $rs1, 0b001)>;
+// def : Pat<(i32 (fp_to_uint FPR16:$rs1)), (FCVT_WU_H $rs1, 0b001)>;
+//
+// // half->int32 with current rounding mode.
+// def : Pat<(i32 (lrint FPR16:$rs1)), (FCVT_W_H $rs1, 0b111)>;
+//
+// // half->int32 rounded to nearest with ties rounded away from zero.
+// def : Pat<(i32 (lround FPR16:$rs1)), (FCVT_W_H $rs1, 0b100)>;
+//
+// // [u]int->half. Match GCC and default to using dynamic rounding mode.
+// def : Pat<(sint_to_fp (i32 GPR:$rs1)), (FCVT_H_W $rs1, 0b111)>;
+// def : Pat<(uint_to_fp (i32 GPR:$rs1)), (FCVT_H_WU $rs1, 0b111)>;
+// } // Predicates = [HasStdExtZfh, IsRV32]
+//
+// let Predicates = [HasStdExtZfh, IsRV64] in {
+// // Use target specific isd nodes to help us remember the result is sign
+// // extended. Matching sext_inreg+fptoui/fptosi may cause the conversion to be
+// // duplicated if it has another user that didn't need the sign_extend.
+// def : Pat<(riscv_fcvt_w_rv64 FPR16:$rs1),  (FCVT_W_H $rs1, 0b001)>;
+// def : Pat<(riscv_fcvt_wu_rv64 FPR16:$rs1), (FCVT_WU_H $rs1, 0b001)>;
+//
+// // half->[u]int64. Round-to-zero must be used.
+// def : Pat<(i64 (fp_to_sint FPR16:$rs1)), (FCVT_L_H $rs1, 0b001)>;
+// def : Pat<(i64 (fp_to_uint FPR16:$rs1)), (FCVT_LU_H $rs1, 0b001)>;
+//
+// // half->int64 with current rounding mode.
+// def : Pat<(i64 (lrint FPR16:$rs1)), (FCVT_L_H $rs1, 0b111)>;
+// def : Pat<(i64 (llrint FPR16:$rs1)), (FCVT_L_H $rs1, 0b111)>;
+//
+// // half->int64 rounded to nearest with ties rounded away from zero.
+// def : Pat<(i64 (lround FPR16:$rs1)), (FCVT_L_H $rs1, 0b100)>;
+// def : Pat<(i64 (llround FPR16:$rs1)), (FCVT_L_H $rs1, 0b100)>;
+//
+// // [u]int->fp. Match GCC and default to using dynamic rounding mode.
+// def : Pat<(sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_H_W $rs1, 0b111)>;
+// def : Pat<(uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_H_WU $rs1, 0b111)>;
+// def : Pat<(sint_to_fp (i64 GPR:$rs1)), (FCVT_H_L $rs1, 0b111)>;
+// def : Pat<(uint_to_fp (i64 GPR:$rs1)), (FCVT_H_LU $rs1, 0b111)>;
+// } // Predicates = [HasStdExtZfh, IsRV64]
+//
+// let Predicates = [HasStdExtZfh, HasStdExtD] in {
+// /// Float conversion operations
+// // f64 -> f16, f16 -> f64
+// def : Pat<(fpround FPR64:$rs1), (FCVT_H_D FPR64:$rs1, 0b111)>;
+// def : Pat<(fpextend FPR16:$rs1), (FCVT_D_H FPR16:$rs1)>;
+//
+// /// Float arithmetic operations
+// def : Pat<(fcopysign FPR16:$rs1, FPR64:$rs2),
+//           (FSGNJ_H $rs1, (FCVT_H_D $rs2, 0b111))>;
+// def : Pat<(fcopysign FPR64:$rs1, FPR16:$rs2), (FSGNJ_D $rs1, (FCVT_D_H $rs2))>;
+// }
+//
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXswar.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXswar.td
new file mode 100644
index 000000000000..75650de07c85
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXswar.td
@@ -0,0 +1,355 @@
+//===-- RISCVInstrInfoXswar.td - daiteq 'x-swar' instructions -----*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes instructions for daiteq s.r.o. extension 'x-swar'
+// SWAR extension, version 0.1.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// RISC-V specific DAG Nodes.
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+// predicate HasDaiExtXswar
+
+def OPC_SWAR      : RISCVOpcode<0b0101011>;
+//def OPC_SWARI     : RISCVOpcode<0b0001011>;
+
+
+def SDT_RISCVSWAR_i32
+    : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>]>;
+def riscv_swar_i32
+    : SDNode<"RISCVISD::SWAR", SDT_RISCVSWAR_i32>;
+
+def SDT_RISCVSWAR_i1in32
+    : SDTypeProfile<1, 2, [SDTCisVT<0, vswp32i1>, SDTCisVT<1, vswp32i1>, SDTCisVT<2, vswp32i1>]>;
+def riscv_swar_i1in32
+    : SDNode<"RISCVISD::SWAR", SDT_RISCVSWAR_i1in32>;
+
+def SDT_RISCVSWAR_i2in16
+    : SDTypeProfile<1, 2, [SDTCisVT<0, vswp32i2>, SDTCisVT<1, vswp32i2>, SDTCisVT<2, vswp32i2>]>;
+def riscv_swar_i2in16
+    : SDNode<"RISCVISD::SWAR", SDT_RISCVSWAR_i2in16>;
+
+def SDT_RISCVSWAR_i3in10
+    : SDTypeProfile<1, 2, [SDTCisVT<0, vswp32i3>, SDTCisVT<1, vswp32i3>, SDTCisVT<2, vswp32i3>]>;
+def riscv_swar_i3in10
+    : SDNode<"RISCVISD::SWAR", SDT_RISCVSWAR_i3in10>;
+
+def SDT_RISCVSWAR_i4in8
+    : SDTypeProfile<1, 2, [SDTCisVT<0, vswp32i4>, SDTCisVT<1, vswp32i4>, SDTCisVT<2, vswp32i4>]>;
+def riscv_swar_i4in8
+    : SDNode<"RISCVISD::SWAR", SDT_RISCVSWAR_i4in8>;
+
+def SDT_RISCVSWAR_i8in4
+    : SDTypeProfile<1, 2, [SDTCisVT<0, vswp32i8>, SDTCisVT<1, vswp32i8>, SDTCisVT<2, vswp32i8>]>;
+def riscv_swar_i8in4
+    : SDNode<"RISCVISD::SWAR", SDT_RISCVSWAR_i8in4>;
+
+def SDT_RISCVSWAR_i16in2
+    : SDTypeProfile<1, 2, [SDTCisVT<0, vswp32i16>, SDTCisVT<1, vswp32i16>, SDTCisVT<2, vswp32i16>]>;
+def riscv_swar_i16in2
+    : SDNode<"RISCVISD::SWAR", SDT_RISCVSWAR_i16in2>;
+
+
+def SDT_RISCVSWAR_i64
+    : SDTypeProfile<1, 2, [SDTCisVT<0, i64>, SDTCisVT<1, i64>, SDTCisVT<2, i64>]>;
+def riscv_swar_i64
+    : SDNode<"RISCVISD::SWAR", SDT_RISCVSWAR_i64>;
+
+def SDT_RISCVSWAR_i1in64
+    : SDTypeProfile<1, 2, [SDTCisVT<0, vswp64i1>, SDTCisVT<1, vswp64i1>, SDTCisVT<2, vswp64i1>]>;
+def riscv_swar_i1in64
+    : SDNode<"RISCVISD::SWAR", SDT_RISCVSWAR_i1in64>;
+
+def SDT_RISCVSWAR_i2in32
+    : SDTypeProfile<1, 2, [SDTCisVT<0, vswp64i2>, SDTCisVT<1, vswp64i2>, SDTCisVT<2, vswp64i2>]>;
+def riscv_swar_i2in32
+    : SDNode<"RISCVISD::SWAR", SDT_RISCVSWAR_i2in32>;
+
+def SDT_RISCVSWAR_i3in21
+    : SDTypeProfile<1, 2, [SDTCisVT<0, vswp64i3>, SDTCisVT<1, vswp64i3>, SDTCisVT<2, vswp64i3>]>;
+def riscv_swar_i3in21
+    : SDNode<"RISCVISD::SWAR", SDT_RISCVSWAR_i3in21>;
+
+def SDT_RISCVSWAR_i4in16
+    : SDTypeProfile<1, 2, [SDTCisVT<0, vswp64i4>, SDTCisVT<1, vswp64i4>, SDTCisVT<2, vswp64i4>]>;
+def riscv_swar_i4in16
+    : SDNode<"RISCVISD::SWAR", SDT_RISCVSWAR_i4in16>;
+
+def SDT_RISCVSWAR_i8in8
+    : SDTypeProfile<1, 2, [SDTCisVT<0, vswp64i8>, SDTCisVT<1, vswp64i8>, SDTCisVT<2, vswp64i8>]>;
+def riscv_swar_i8in8
+    : SDNode<"RISCVISD::SWAR", SDT_RISCVSWAR_i8in8>;
+
+def SDT_RISCVSWAR_i16in4
+    : SDTypeProfile<1, 2, [SDTCisVT<0, vswp64i16>, SDTCisVT<1, vswp64i16>, SDTCisVT<2, vswp64i16>]>;
+def riscv_swar_i16in4
+    : SDNode<"RISCVISD::SWAR", SDT_RISCVSWAR_i16in4>;
+
+def SDT_RISCVSWAR_i32in2
+    : SDTypeProfile<1, 2, [SDTCisVT<0, vswp64i32>, SDTCisVT<1, vswp64i32>, SDTCisVT<2, vswp64i32>]>;
+def riscv_swar_i32in2
+    : SDNode<"RISCVISD::SWAR", SDT_RISCVSWAR_i32in2>;
+
+
+
+
+let Predicates = [HasDaiExtXswar] in {
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+def SWAR   : RVInstR<0b0000000, 0b000, OPC_SWAR, (outs SWARR:$rd),
+             (ins SWARR:$rs1, SWARR:$rs2), "swar", "$rd, $rs1, $rs2">,
+             Sched<[WriteIALU, ReadIALU]>;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+def SWARINT32 : RVInstR<0b0000000, 0b000, OPC_SWAR, (outs GPR:$rd),
+                (ins GPR:$rs1, GPR:$rs2), "swar", "$rd, $rs1, $rs2">,
+                Sched<[WriteIALU, ReadIALU]>;
+
+def : Pat<(riscv_swar_i32 GPR:$rs1, GPR:$rs2), (SWARINT32 GPR:$rs1, GPR:$rs2)>;
+def : Pat<(riscv_swar_i1in32 SWARR:$rs1, SWARR:$rs2), (SWAR SWARR:$rs1, SWARR:$rs2)>;
+def : Pat<(riscv_swar_i2in16 SWARR:$rs1, SWARR:$rs2), (SWAR SWARR:$rs1, SWARR:$rs2)>;
+def : Pat<(riscv_swar_i3in10 SWARR:$rs1, SWARR:$rs2), (SWAR SWARR:$rs1, SWARR:$rs2)>;
+def : Pat<(riscv_swar_i4in8 SWARR:$rs1, SWARR:$rs2), (SWAR SWARR:$rs1, SWARR:$rs2)>;
+def : Pat<(riscv_swar_i8in4 SWARR:$rs1, SWARR:$rs2), (SWAR SWARR:$rs1, SWARR:$rs2)>;
+def : Pat<(riscv_swar_i16in2 SWARR:$rs1, SWARR:$rs2), (SWAR SWARR:$rs1, SWARR:$rs2)>;
+
+
+//let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+//def SWARI  : RVInstI<0b000, OPC_SWARI, (outs SWARR:$rd),
+//             (ins SWARR:$rs1, simm12:$imm12), "swari", "$rd, $rs1, ${imm12}">,
+//             Sched<[WriteIALU, ReadIALU]>;
+}
+
+
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+def SSWAR32 : RVInstS<0b010, OPC_STORE, (outs),
+              (ins SWARR:$rs2, GPR:$rs1, simm12:$imm12),
+              "sw", "$rs2, ${imm12}(${rs1})">,
+              Sched<[WriteSTW, ReadStoreData, ReadMemBase]>;
+
+def : Pat<(store (vswp32i1 SWARR:$rs2), BaseAddr:$rs1),
+            (SSWAR32 SWARR:$rs2, BaseAddr:$rs1, 0)>;
+def : Pat<(store (vswp32i2 SWARR:$rs2), BaseAddr:$rs1),
+            (SSWAR32 SWARR:$rs2, BaseAddr:$rs1, 0)>;
+def : Pat<(store (vswp32i3 SWARR:$rs2), BaseAddr:$rs1),
+            (SSWAR32 SWARR:$rs2, BaseAddr:$rs1, 0)>;
+def : Pat<(store (vswp32i4 SWARR:$rs2), BaseAddr:$rs1),
+            (SSWAR32 SWARR:$rs2, BaseAddr:$rs1, 0)>;
+def : Pat<(store (vswp32i8 SWARR:$rs2), BaseAddr:$rs1),
+            (SSWAR32 SWARR:$rs2, BaseAddr:$rs1, 0)>;
+def : Pat<(store (vswp32i16 SWARR:$rs2), BaseAddr:$rs1),
+            (SSWAR32 SWARR:$rs2, BaseAddr:$rs1, 0)>;
+
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+def LSWAR32 : RVInstI<0b010, OPC_LOAD, (outs SWARR:$rd),
+              (ins GPR:$rs1, simm12:$imm12),
+              "lwu", "$rd, ${imm12}(${rs1})">,
+              Sched<[WriteLDW, ReadMemBase]>;
+
+def : Pat<(vswp32i1 (load BaseAddr:$rs1)), (LSWAR32 BaseAddr:$rs1, 0)>;
+def : Pat<(vswp32i2 (load BaseAddr:$rs1)), (LSWAR32 BaseAddr:$rs1, 0)>;
+def : Pat<(vswp32i3 (load BaseAddr:$rs1)), (LSWAR32 BaseAddr:$rs1, 0)>;
+def : Pat<(vswp32i4 (load BaseAddr:$rs1)), (LSWAR32 BaseAddr:$rs1, 0)>;
+def : Pat<(vswp32i8 (load BaseAddr:$rs1)), (LSWAR32 BaseAddr:$rs1, 0)>;
+def : Pat<(vswp32i16 (load BaseAddr:$rs1)), (LSWAR32 BaseAddr:$rs1, 0)>;
+
+
+def : Pat<(add (vswp32i1 SWARR:$rs1), (vswp32i1 SWARR:$rs2)),
+            (SWAR SWARR:$rs1, SWARR:$rs2)>;
+def : Pat<(sub (vswp32i1 SWARR:$rs1), (vswp32i1 SWARR:$rs2)),
+            (SWAR SWARR:$rs1, SWARR:$rs2)>;
+def : Pat<(mul (vswp32i1 SWARR:$rs1), (vswp32i1 SWARR:$rs2)),
+            (SWAR SWARR:$rs1, SWARR:$rs2)>;
+
+def : Pat<(add (vswp32i2 SWARR:$rs1), (vswp32i2 SWARR:$rs2)),
+            (SWAR SWARR:$rs1, SWARR:$rs2)>;
+def : Pat<(sub (vswp32i2 SWARR:$rs1), (vswp32i2 SWARR:$rs2)),
+            (SWAR SWARR:$rs1, SWARR:$rs2)>;
+def : Pat<(mul (vswp32i2 SWARR:$rs1), (vswp32i2 SWARR:$rs2)),
+            (SWAR SWARR:$rs1, SWARR:$rs2)>;
+
+def : Pat<(add (vswp32i3 SWARR:$rs1), (vswp32i3 SWARR:$rs2)),
+            (SWAR SWARR:$rs1, SWARR:$rs2)>;
+def : Pat<(sub (vswp32i3 SWARR:$rs1), (vswp32i3 SWARR:$rs2)),
+            (SWAR SWARR:$rs1, SWARR:$rs2)>;
+def : Pat<(mul (vswp32i3 SWARR:$rs1), (vswp32i3 SWARR:$rs2)),
+            (SWAR SWARR:$rs1, SWARR:$rs2)>;
+
+def : Pat<(add (vswp32i4 SWARR:$rs1), (vswp32i4 SWARR:$rs2)),
+            (SWAR SWARR:$rs1, SWARR:$rs2)>;
+def : Pat<(sub (vswp32i4 SWARR:$rs1), (vswp32i4 SWARR:$rs2)),
+            (SWAR SWARR:$rs1, SWARR:$rs2)>;
+def : Pat<(mul (vswp32i4 SWARR:$rs1), (vswp32i4 SWARR:$rs2)),
+            (SWAR SWARR:$rs1, SWARR:$rs2)>;
+
+def : Pat<(add (vswp32i8 SWARR:$rs1), (vswp32i8 SWARR:$rs2)),
+            (SWAR SWARR:$rs1, SWARR:$rs2)>;
+def : Pat<(sub (vswp32i8 SWARR:$rs1), (vswp32i8 SWARR:$rs2)),
+            (SWAR SWARR:$rs1, SWARR:$rs2)>;
+def : Pat<(mul (vswp32i8 SWARR:$rs1), (vswp32i8 SWARR:$rs2)),
+            (SWAR SWARR:$rs1, SWARR:$rs2)>;
+
+def : Pat<(add (vswp32i16 SWARR:$rs1), (vswp32i16 SWARR:$rs2)),
+            (SWAR SWARR:$rs1, SWARR:$rs2)>;
+def : Pat<(sub (vswp32i16 SWARR:$rs1), (vswp32i16 SWARR:$rs2)),
+            (SWAR SWARR:$rs1, SWARR:$rs2)>;
+def : Pat<(mul (vswp32i16 SWARR:$rs1), (vswp32i16 SWARR:$rs2)),
+            (SWAR SWARR:$rs1, SWARR:$rs2)>;
+
+
+
+//===----------------------------------------------------------------------===//
+// Bitcasts between same-size vector types are no-ops, except for the
+// actual type change.
+multiclass swar32_cast_pat<ValueType Ty1, ValueType Ty2> {
+  def: Pat<(Ty1 (bitconvert (Ty2 SWARR:$Val))), (Ty1 GPR:$Val)>;
+  def: Pat<(Ty2 (bitconvert (Ty1 GPR:$Val))), (Ty2 SWARR:$Val)>;
+}
+
+multiclass swar64_cast_pat<ValueType Ty1, ValueType Ty2> {
+  def: Pat<(Ty1 (bitconvert (Ty2 SWARR64:$Val))), (Ty1 GPR:$Val)>;
+  def: Pat<(Ty2 (bitconvert (Ty1 GPR:$Val))), (Ty2 SWARR64:$Val)>;
+}
+
+// All of these are bitcastable to one another: i32, vswp32iX. (only for RV32)
+defm: swar32_cast_pat<i32,   vswp32i1>;
+defm: swar32_cast_pat<i32,   vswp32i2>;
+defm: swar32_cast_pat<i32,   vswp32i3>;
+defm: swar32_cast_pat<i32,   vswp32i4>;
+defm: swar32_cast_pat<i32,   vswp32i8>;
+defm: swar32_cast_pat<i32,   vswp32i16>;
+
+// All of these are bitcastable to one another: i64, vswp64iX.
+let Predicates = [IsRV64] in {
+
+defm: swar64_cast_pat<i64,   vswp64i1>;
+defm: swar64_cast_pat<i64,   vswp64i2>;
+defm: swar64_cast_pat<i64,   vswp64i3>;
+defm: swar64_cast_pat<i64,   vswp64i4>;
+defm: swar64_cast_pat<i64,   vswp64i8>;
+defm: swar64_cast_pat<i64,   vswp64i16>;
+defm: swar64_cast_pat<i64,   vswp64i32>;
+
+}
+
+//===----------------------------------------------------------------------===//
+let Predicates = [IsRV64] in {
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+def SWAR64 : RVInstR<0b0000000, 0b000, OPC_SWAR, (outs SWARR64:$rd),
+             (ins SWARR64:$rs1, SWARR64:$rs2), "swar", "$rd, $rs1, $rs2">,
+             Sched<[WriteIALU, ReadIALU]>;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+def SWARINT64 : RVInstR<0b0000000, 0b000, OPC_SWAR, (outs GPR:$rd),
+                (ins GPR:$rs1, GPR:$rs2), "swar", "$rd, $rs1, $rs2">,
+                Sched<[WriteIALU, ReadIALU]>;
+
+def : Pat<(riscv_swar_i64 GPR:$rs1, GPR:$rs2), (SWARINT64 GPR:$rs1, GPR:$rs2)>;
+def : Pat<(riscv_swar_i1in64 SWARR64:$rs1, SWARR64:$rs2), (SWAR64 SWARR64:$rs1, SWARR64:$rs2)>;
+def : Pat<(riscv_swar_i2in32 SWARR64:$rs1, SWARR64:$rs2), (SWAR64 SWARR64:$rs1, SWARR64:$rs2)>;
+def : Pat<(riscv_swar_i3in21 SWARR64:$rs1, SWARR64:$rs2), (SWAR64 SWARR64:$rs1, SWARR64:$rs2)>;
+def : Pat<(riscv_swar_i4in16 SWARR64:$rs1, SWARR64:$rs2), (SWAR64 SWARR64:$rs1, SWARR64:$rs2)>;
+def : Pat<(riscv_swar_i8in8 SWARR64:$rs1, SWARR64:$rs2), (SWAR64 SWARR64:$rs1, SWARR64:$rs2)>;
+def : Pat<(riscv_swar_i16in4 SWARR64:$rs1, SWARR64:$rs2), (SWAR64 SWARR64:$rs1, SWARR64:$rs2)>;
+def : Pat<(riscv_swar_i32in2 SWARR64:$rs1, SWARR64:$rs2), (SWAR64 SWARR64:$rs1, SWARR64:$rs2)>;
+
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+  def SSWAR64 : RVInstS<0b011, OPC_STORE, (outs),
+                (ins SWARR64:$rs2, GPR:$rs1, simm12:$imm12),
+                "sd", "$rs2, ${imm12}(${rs1})">,
+                Sched<[WriteSTD, ReadStoreData, ReadMemBase]>;
+
+  def : Pat<(store (vswp64i1 SWARR64:$rs2), BaseAddr:$rs1),
+              (SSWAR64 SWARR64:$rs2, BaseAddr:$rs1, 0)>;
+  def : Pat<(store (vswp64i2 SWARR64:$rs2), BaseAddr:$rs1),
+              (SSWAR64 SWARR64:$rs2, BaseAddr:$rs1, 0)>;
+  def : Pat<(store (vswp64i3 SWARR64:$rs2), BaseAddr:$rs1),
+              (SSWAR64 SWARR64:$rs2, BaseAddr:$rs1, 0)>;
+  def : Pat<(store (vswp64i4 SWARR64:$rs2), BaseAddr:$rs1),
+              (SSWAR64 SWARR64:$rs2, BaseAddr:$rs1, 0)>;
+  def : Pat<(store (vswp64i8 SWARR64:$rs2), BaseAddr:$rs1),
+              (SSWAR64 SWARR64:$rs2, BaseAddr:$rs1, 0)>;
+  def : Pat<(store (vswp64i16 SWARR64:$rs2), BaseAddr:$rs1),
+              (SSWAR64 SWARR64:$rs2, BaseAddr:$rs1, 0)>;
+  def : Pat<(store (vswp64i32 SWARR64:$rs2), BaseAddr:$rs1),
+              (SSWAR64 SWARR64:$rs2, BaseAddr:$rs1, 0)>;
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+def LSWAR64 : RVInstI<0b011, OPC_LOAD, (outs SWARR64:$rd),
+              (ins GPR:$rs1, simm12:$imm12),
+              "ld", "$rd, ${imm12}(${rs1})">,
+              Sched<[WriteLDD, ReadMemBase]>;
+
+def : Pat<(vswp64i1 (load BaseAddr:$rs1)), (LSWAR64 BaseAddr:$rs1, 0)>;
+def : Pat<(vswp64i2 (load BaseAddr:$rs1)), (LSWAR64 BaseAddr:$rs1, 0)>;
+def : Pat<(vswp64i3 (load BaseAddr:$rs1)), (LSWAR64 BaseAddr:$rs1, 0)>;
+def : Pat<(vswp64i4 (load BaseAddr:$rs1)), (LSWAR64 BaseAddr:$rs1, 0)>;
+def : Pat<(vswp64i8 (load BaseAddr:$rs1)), (LSWAR64 BaseAddr:$rs1, 0)>;
+def : Pat<(vswp64i16 (load BaseAddr:$rs1)), (LSWAR64 BaseAddr:$rs1, 0)>;
+def : Pat<(vswp64i32 (load BaseAddr:$rs1)), (LSWAR64 BaseAddr:$rs1, 0)>;
+
+
+def : Pat<(add (vswp64i1 SWARR64:$rs1), (vswp64i1 SWARR64:$rs2)),
+            (SWAR64 SWARR64:$rs1, SWARR64:$rs2)>;
+def : Pat<(sub (vswp64i1 SWARR64:$rs1), (vswp64i1 SWARR64:$rs2)),
+            (SWAR64 SWARR64:$rs1, SWARR64:$rs2)>;
+def : Pat<(mul (vswp64i1 SWARR64:$rs1), (vswp64i1 SWARR64:$rs2)),
+            (SWAR64 SWARR64:$rs1, SWARR64:$rs2)>;
+
+def : Pat<(add (vswp64i2 SWARR64:$rs1), (vswp64i2 SWARR64:$rs2)),
+            (SWAR64 SWARR64:$rs1, SWARR64:$rs2)>;
+def : Pat<(sub (vswp64i2 SWARR64:$rs1), (vswp64i2 SWARR64:$rs2)),
+            (SWAR64 SWARR64:$rs1, SWARR64:$rs2)>;
+def : Pat<(mul (vswp64i2 SWARR64:$rs1), (vswp64i2 SWARR64:$rs2)),
+            (SWAR64 SWARR64:$rs1, SWARR64:$rs2)>;
+
+def : Pat<(add (vswp64i3 SWARR64:$rs1), (vswp64i3 SWARR64:$rs2)),
+            (SWAR64 SWARR64:$rs1, SWARR64:$rs2)>;
+def : Pat<(sub (vswp64i3 SWARR64:$rs1), (vswp64i3 SWARR64:$rs2)),
+            (SWAR64 SWARR64:$rs1, SWARR64:$rs2)>;
+def : Pat<(mul (vswp64i3 SWARR64:$rs1), (vswp64i3 SWARR64:$rs2)),
+            (SWAR64 SWARR64:$rs1, SWARR64:$rs2)>;
+
+def : Pat<(add (vswp64i4 SWARR64:$rs1), (vswp64i4 SWARR64:$rs2)),
+            (SWAR64 SWARR64:$rs1, SWARR64:$rs2)>;
+def : Pat<(sub (vswp64i4 SWARR64:$rs1), (vswp64i4 SWARR64:$rs2)),
+            (SWAR64 SWARR64:$rs1, SWARR64:$rs2)>;
+def : Pat<(mul (vswp64i4 SWARR64:$rs1), (vswp64i4 SWARR64:$rs2)),
+            (SWAR64 SWARR64:$rs1, SWARR64:$rs2)>;
+
+def : Pat<(add (vswp64i8 SWARR64:$rs1), (vswp64i8 SWARR64:$rs2)),
+            (SWAR64 SWARR64:$rs1, SWARR64:$rs2)>;
+def : Pat<(sub (vswp64i8 SWARR64:$rs1), (vswp64i8 SWARR64:$rs2)),
+            (SWAR64 SWARR64:$rs1, SWARR64:$rs2)>;
+def : Pat<(mul (vswp64i8 SWARR64:$rs1), (vswp64i8 SWARR64:$rs2)),
+            (SWAR64 SWARR64:$rs1, SWARR64:$rs2)>;
+
+def : Pat<(add (vswp64i16 SWARR64:$rs1), (vswp64i16 SWARR64:$rs2)),
+            (SWAR64 SWARR64:$rs1, SWARR64:$rs2)>;
+def : Pat<(sub (vswp64i16 SWARR64:$rs1), (vswp64i16 SWARR64:$rs2)),
+            (SWAR64 SWARR64:$rs1, SWARR64:$rs2)>;
+def : Pat<(mul (vswp64i16 SWARR64:$rs1), (vswp64i16 SWARR64:$rs2)),
+            (SWAR64 SWARR64:$rs1, SWARR64:$rs2)>;
+
+def : Pat<(add (vswp64i32 SWARR64:$rs1), (vswp64i32 SWARR64:$rs2)),
+            (SWAR64 SWARR64:$rs1, SWARR64:$rs2)>;
+def : Pat<(sub (vswp64i32 SWARR64:$rs1), (vswp64i32 SWARR64:$rs2)),
+            (SWAR64 SWARR64:$rs1, SWARR64:$rs2)>;
+def : Pat<(mul (vswp64i32 SWARR64:$rs1), (vswp64i32 SWARR64:$rs2)),
+            (SWAR64 SWARR64:$rs1, SWARR64:$rs2)>;
+
+}
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index fde75206889c..2ffe16628aaf 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -42,6 +42,26 @@ class RISCVReg64<RISCVReg32 subreg> : Register<""> {
   let AltNames = subreg.AltNames;
 }
 
+def sub_322 : SubRegIndex<32>;
+class RISCVReg16V2<RISCVReg64 subreg> : Register<""> {
+  let HWEncoding{4-0} = subreg.HWEncoding{4-0};
+  let SubRegs = [subreg];
+  let SubRegIndices = [sub_322];
+  let AsmName = subreg.AsmName;
+  let AltNames = subreg.AltNames;
+}
+
+def sub_323 : SubRegIndex<32>;
+class RISCVReg32V2<RISCVReg16V2 subreg> : Register<""> {
+  let HWEncoding{4-0} = subreg.HWEncoding{4-0};
+  let SubRegs = [subreg];
+  let SubRegIndices = [sub_323];
+  let AsmName = subreg.AsmName;
+  let AltNames = subreg.AltNames;
+}
+
+
+
 class RISCVRegWithSubRegs<bits<5> Enc, string n, list<Register> subregs,
                           list<string> alt = []>
       : RegisterWithSubRegs<n, subregs> {
@@ -199,6 +219,27 @@ def SP : RegisterClass<"RISCV", [XLenVT], 32, (add X2)> {
   let RegInfos = XLenRI;
 }
 
+// daiteq SWAR registers
+def SWARR : RegisterClass<"RISCV", [vswp32i1,vswp32i2,vswp32i3,vswp32i4,vswp32i8,vswp32i16], 32, (add
+    (sequence "X%u", 10, 17),
+    (sequence "X%u", 5, 7),
+    (sequence "X%u", 28, 31),
+    (sequence "X%u", 8, 9),
+    (sequence "X%u", 18, 27)
+  )> {
+  let RegInfos = XLenRI;
+}
+
+def SWARR64 : RegisterClass<"RISCV", [vswp64i1,vswp64i2,vswp64i3,vswp64i4,vswp64i8,vswp64i16,vswp64i32], 32, (add
+    (sequence "X%u", 10, 17),
+    (sequence "X%u", 5, 7),
+    (sequence "X%u", 28, 31),
+    (sequence "X%u", 8, 9),
+    (sequence "X%u", 18, 27)
+  )> {
+  let RegInfos = XLenRI;
+}
+
 // Floating point registers
 let RegAltNameIndices = [ABIRegAltName] in {
   def F0_H  : RISCVReg16<0, "f0", ["ft0"]>, DwarfRegNum<[32]>;
@@ -243,10 +284,22 @@ let RegAltNameIndices = [ABIRegAltName] in {
     def F#Index#_D : RISCVReg64<!cast<RISCVReg32>("F"#Index#"_F")>,
       DwarfRegNum<[!add(Index, 32)]>;
   }
+
+  foreach Index = 0-31 in {
+    def F#Index#_PH : RISCVReg16V2<!cast<RISCVReg64>("F"#Index#"_D")>,
+      DwarfRegNum<[!add(Index, 32)]>;
+  }
+
+  foreach Index = 0-31 in {
+    def F#Index#_PS : RISCVReg32V2<!cast<RISCVReg16V2>("F"#Index#"_PH")>,
+      DwarfRegNum<[!add(Index, 32)]>;
+  }
+
 }
 
 // The order of registers represents the preferred allocation sequence,
 // meaning caller-save regs are listed before callee-save.
+let KindGroup = 1 in {
 def FPR16 : RegisterClass<"RISCV", [f16], 16, (add
     (sequence "F%u_H", 0, 7),
     (sequence "F%u_H", 10, 17),
@@ -283,6 +336,25 @@ def FPR64C : RegisterClass<"RISCV", [f64], 64, (add
   (sequence "F%u_D", 8, 9)
 )>;
 
+// Packed vectors for the daiteq extensions
+def FPR16V2 : RegisterClass<"RISCV", [v2f16], 32, (add
+    (sequence "F%u_PH", 0, 7),
+    (sequence "F%u_PH", 10, 17),
+    (sequence "F%u_PH", 28, 31),
+    (sequence "F%u_PH", 8, 9),
+    (sequence "F%u_PH", 18, 27)
+)>;
+
+def FPR32V2 : RegisterClass<"RISCV", [v2f32], 64, (add
+    (sequence "F%u_PS", 0, 7),
+    (sequence "F%u_PS", 10, 17),
+    (sequence "F%u_PS", 28, 31),
+    (sequence "F%u_PS", 8, 9),
+    (sequence "F%u_PS", 18, 27)
+)>;
+}
+
+
 // Vector type mapping to LLVM types.
 //
 // The V vector extension requires that VLEN >= 128 and <= 65536.
diff --git a/llvm/lib/Target/RISCV/RISCVSchedDaiteq.td b/llvm/lib/Target/RISCV/RISCVSchedDaiteq.td
new file mode 100644
index 000000000000..d8590f01ed61
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVSchedDaiteq.td
@@ -0,0 +1,304 @@
+//==- RISCVSchedDaiteq.td - Daiteq (NOEL64) Scheduling Definitions --*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+//* base on SiFive7 scheduling model *//
+
+// Daiteq machine model for scheduling and other instruction cost heuristics.
+def DaiteqModel : SchedMachineModel {
+  let MicroOpBufferSize = 0; // Explicitly set to zero since CPU is in-order.
+  let IssueWidth = 2;        // 2 micro-ops are dispatched per cycle.
+  let LoadLatency = 3;
+  let MispredictPenalty = 3;
+  let CompleteModel = 0;
+  let UnsupportedFeatures = [HasStdExtV, HasStdExtZvamo, HasStdExtZvlsseg];
+}
+
+// The SiFive7 microarchitecure has two pipelines: A and B.
+// Pipe A can handle memory, integer alu and vector operations.
+// Pipe B can handle integer alu, control flow, integer multiply and divide,
+// and floating point computation.
+let SchedModel = DaiteqModel in {
+let BufferSize = 0 in {
+def DaiteqPipeA       : ProcResource<1>;
+def DaiteqPipeB       : ProcResource<1>;
+}
+
+let BufferSize = 1 in {
+def DaiteqIDiv        : ProcResource<1> { let Super = DaiteqPipeB; } // Int Division
+def DaiteqFDiv        : ProcResource<1> { let Super = DaiteqPipeB; } // FP Division/Sqrt
+}
+
+def DaiteqPipeAB : ProcResGroup<[DaiteqPipeA, DaiteqPipeB]>;
+
+// Branching
+def : WriteRes<WriteJmp, [DaiteqPipeB]>;
+def : WriteRes<WriteJal, [DaiteqPipeB]>;
+def : WriteRes<WriteJalr, [DaiteqPipeB]>;
+def : WriteRes<WriteJmpReg, [DaiteqPipeB]>;
+
+// Integer arithmetic and logic
+let Latency = 3 in {
+def : WriteRes<WriteIALU, [DaiteqPipeAB]>;
+def : WriteRes<WriteIALU32, [DaiteqPipeAB]>;
+def : WriteRes<WriteShiftImm, [DaiteqPipeAB]>;
+def : WriteRes<WriteShiftImm32, [DaiteqPipeAB]>;
+def : WriteRes<WriteShiftReg, [DaiteqPipeAB]>;
+def : WriteRes<WriteShiftReg32, [DaiteqPipeAB]>;
+}
+
+// Integer multiplication
+let Latency = 3 in {
+def : WriteRes<WriteIMul, [DaiteqPipeB]>;
+def : WriteRes<WriteIMul32, [DaiteqPipeB]>;
+}
+
+// Integer division
+def : WriteRes<WriteIDiv, [DaiteqPipeB, DaiteqIDiv]> {
+  let Latency = 16;
+  let ResourceCycles = [1, 15];
+}
+def : WriteRes<WriteIDiv32,  [DaiteqPipeB, DaiteqIDiv]> {
+  let Latency = 16;
+  let ResourceCycles = [1, 15];
+}
+
+// Memory
+def : WriteRes<WriteSTB, [DaiteqPipeA]>;
+def : WriteRes<WriteSTH, [DaiteqPipeA]>;
+def : WriteRes<WriteSTW, [DaiteqPipeA]>;
+def : WriteRes<WriteSTD, [DaiteqPipeA]>;
+def : WriteRes<WriteFST32, [DaiteqPipeA]>;
+def : WriteRes<WriteFST64, [DaiteqPipeA]>;
+
+let Latency = 3 in {
+def : WriteRes<WriteLDB, [DaiteqPipeA]>;
+def : WriteRes<WriteLDH, [DaiteqPipeA]>;
+def : WriteRes<WriteLDW, [DaiteqPipeA]>;
+def : WriteRes<WriteLDWU, [DaiteqPipeA]>;
+def : WriteRes<WriteLDD, [DaiteqPipeA]>;
+}
+
+let Latency = 2 in {
+def : WriteRes<WriteFLD32, [DaiteqPipeA]>;
+def : WriteRes<WriteFLD64, [DaiteqPipeA]>;
+}
+
+let Latency = 10 in {
+def : WriteRes<WriteFLD16, [DaiteqPipeA]>;
+def : WriteRes<WriteFST16, [DaiteqPipeA]>;
+}
+
+// Atomic memory
+def : WriteRes<WriteAtomicSTW, [DaiteqPipeA]>;
+def : WriteRes<WriteAtomicSTD, [DaiteqPipeA]>;
+
+let Latency = 3 in {
+def : WriteRes<WriteAtomicW, [DaiteqPipeA]>;
+def : WriteRes<WriteAtomicD, [DaiteqPipeA]>;
+def : WriteRes<WriteAtomicLDW, [DaiteqPipeA]>;
+def : WriteRes<WriteAtomicLDD, [DaiteqPipeA]>;
+}
+
+// Single precision.
+let Latency = 5 in {
+def : WriteRes<WriteFALU32, [DaiteqPipeB]>;
+def : WriteRes<WriteFMul32, [DaiteqPipeB]>;
+def : WriteRes<WriteFMA32, [DaiteqPipeB]>;
+}
+let Latency = 3 in {
+def : WriteRes<WriteFSGNJ32, [DaiteqPipeB]>;
+def : WriteRes<WriteFMinMax32, [DaiteqPipeB]>;
+}
+
+def : WriteRes<WriteFDiv32, [DaiteqPipeB, DaiteqFDiv]> { let Latency = 27;
+                                                         let ResourceCycles = [1, 26]; }
+def : WriteRes<WriteFSqrt32, [DaiteqPipeB, DaiteqFDiv]> { let Latency = 27;
+                                                          let ResourceCycles = [1, 26]; }
+
+// Double precision
+let Latency = 7 in {
+def : WriteRes<WriteFALU64, [DaiteqPipeB]>;
+def : WriteRes<WriteFMul64, [DaiteqPipeB]>;
+def : WriteRes<WriteFMA64, [DaiteqPipeB]>;
+}
+let Latency = 3 in {
+def : WriteRes<WriteFSGNJ64, [DaiteqPipeB]>;
+def : WriteRes<WriteFMinMax64, [DaiteqPipeB]>;
+}
+
+def : WriteRes<WriteFDiv64, [DaiteqPipeB, DaiteqFDiv]> { let Latency = 56;
+                                                         let ResourceCycles = [1, 55]; }
+def : WriteRes<WriteFSqrt64, [DaiteqPipeB, DaiteqFDiv]> { let Latency = 56;
+                                                          let ResourceCycles = [1, 55]; }
+
+// Conversions
+let Latency = 3 in {
+def : WriteRes<WriteFCvtI32ToF32, [DaiteqPipeB]>;
+def : WriteRes<WriteFCvtI32ToF64, [DaiteqPipeB]>;
+def : WriteRes<WriteFCvtI64ToF32, [DaiteqPipeB]>;
+def : WriteRes<WriteFCvtI64ToF64, [DaiteqPipeB]>;
+def : WriteRes<WriteFCvtF32ToI32, [DaiteqPipeB]>;
+def : WriteRes<WriteFCvtF32ToI64, [DaiteqPipeB]>;
+def : WriteRes<WriteFCvtF32ToF64, [DaiteqPipeB]>;
+def : WriteRes<WriteFCvtF64ToI32, [DaiteqPipeB]>;
+def : WriteRes<WriteFCvtF64ToI64, [DaiteqPipeB]>;
+def : WriteRes<WriteFCvtF64ToF32, [DaiteqPipeB]>;
+
+def : WriteRes<WriteFClass32, [DaiteqPipeB]>;
+def : WriteRes<WriteFClass64, [DaiteqPipeB]>;
+def : WriteRes<WriteFCmp32, [DaiteqPipeB]>;
+def : WriteRes<WriteFCmp64, [DaiteqPipeB]>;
+def : WriteRes<WriteFMovI32ToF32, [DaiteqPipeB]>;
+def : WriteRes<WriteFMovF32ToI32, [DaiteqPipeB]>;
+def : WriteRes<WriteFMovI64ToF64, [DaiteqPipeB]>;
+def : WriteRes<WriteFMovF64ToI64, [DaiteqPipeB]>;
+}
+
+// Others
+def : WriteRes<WriteCSR, [DaiteqPipeB]>;
+def : WriteRes<WriteNop, []>;
+
+def : InstRW<[WriteIALU], (instrs COPY)>;
+
+//===----------------------------------------------------------------------===//
+// Bypass and advance
+def : ReadAdvance<ReadJmp, 0>;
+def : ReadAdvance<ReadJalr, 0>;
+def : ReadAdvance<ReadCSR, 0>;
+def : ReadAdvance<ReadStoreData, 0>;
+def : ReadAdvance<ReadMemBase, 0>;
+def : ReadAdvance<ReadIALU, 0>;
+def : ReadAdvance<ReadIALU32, 0>;
+def : ReadAdvance<ReadShiftImm, 0>;
+def : ReadAdvance<ReadShiftImm32, 0>;
+def : ReadAdvance<ReadShiftReg, 0>;
+def : ReadAdvance<ReadShiftReg32, 0>;
+def : ReadAdvance<ReadIDiv, 0>;
+def : ReadAdvance<ReadIDiv32, 0>;
+def : ReadAdvance<ReadIMul, 0>;
+def : ReadAdvance<ReadIMul32, 0>;
+def : ReadAdvance<ReadAtomicWA, 0>;
+def : ReadAdvance<ReadAtomicWD, 0>;
+def : ReadAdvance<ReadAtomicDA, 0>;
+def : ReadAdvance<ReadAtomicDD, 0>;
+def : ReadAdvance<ReadAtomicLDW, 0>;
+def : ReadAdvance<ReadAtomicLDD, 0>;
+def : ReadAdvance<ReadAtomicSTW, 0>;
+def : ReadAdvance<ReadAtomicSTD, 0>;
+def : ReadAdvance<ReadFMemBase, 0>;
+def : ReadAdvance<ReadFALU32, 0>;
+def : ReadAdvance<ReadFALU64, 0>;
+def : ReadAdvance<ReadFMul32, 0>;
+def : ReadAdvance<ReadFMA32, 0>;
+def : ReadAdvance<ReadFMul64, 0>;
+def : ReadAdvance<ReadFMA64, 0>;
+def : ReadAdvance<ReadFDiv32, 0>;
+def : ReadAdvance<ReadFDiv64, 0>;
+def : ReadAdvance<ReadFSqrt32, 0>;
+def : ReadAdvance<ReadFSqrt64, 0>;
+def : ReadAdvance<ReadFCmp32, 0>;
+def : ReadAdvance<ReadFCmp64, 0>;
+def : ReadAdvance<ReadFSGNJ32, 0>;
+def : ReadAdvance<ReadFSGNJ64, 0>;
+def : ReadAdvance<ReadFMinMax32, 0>;
+def : ReadAdvance<ReadFMinMax64, 0>;
+def : ReadAdvance<ReadFCvtF32ToI32, 0>;
+def : ReadAdvance<ReadFCvtF32ToI64, 0>;
+def : ReadAdvance<ReadFCvtF64ToI32, 0>;
+def : ReadAdvance<ReadFCvtF64ToI64, 0>;
+def : ReadAdvance<ReadFCvtI32ToF32, 0>;
+def : ReadAdvance<ReadFCvtI32ToF64, 0>;
+def : ReadAdvance<ReadFCvtI64ToF32, 0>;
+def : ReadAdvance<ReadFCvtI64ToF64, 0>;
+def : ReadAdvance<ReadFCvtF32ToF64, 0>;
+def : ReadAdvance<ReadFCvtF64ToF32, 0>;
+def : ReadAdvance<ReadFMovF32ToI32, 0>;
+def : ReadAdvance<ReadFMovI32ToF32, 0>;
+def : ReadAdvance<ReadFMovF64ToI64, 0>;
+def : ReadAdvance<ReadFMovI64ToF64, 0>;
+def : ReadAdvance<ReadFClass32, 0>;
+def : ReadAdvance<ReadFClass64, 0>;
+
+//===----------------------------------------------------------------------===//
+// PackedHalf //
+let Latency = 1 in {
+def : WriteRes<WriteFALU16v2, [DaiteqPipeB]>;
+def : WriteRes<WriteFCmp16v2, [DaiteqPipeB]>;
+def : WriteRes<WriteFDiv16v2, [DaiteqPipeB]>;
+def : WriteRes<WriteFLD16v2, [DaiteqPipeB]>;
+def : WriteRes<WriteFMul16v2, [DaiteqPipeB]>;
+def : WriteRes<WriteFST16v2, [DaiteqPipeB]>;
+def : WriteRes<WriteFSqrt16v2, [DaiteqPipeB]>;
+def : WriteRes<WriteFSGNJ16v2, [DaiteqPipeB]>;
+def : WriteRes<WriteFMinMax16v2, [DaiteqPipeB]>;
+def : WriteRes<WriteFClass16v2, [DaiteqPipeB]>;
+def : WriteRes<WriteFMov16v2, [DaiteqPipeB]>;
+def : WriteRes<WriteFSwap16v2, [DaiteqPipeB]>;
+
+def : WriteRes<WriteFALU16, [DaiteqPipeB]>;
+def : WriteRes<WriteFClass16, [DaiteqPipeB]>;
+def : WriteRes<WriteFCvtF16ToF64, [DaiteqPipeB]>;
+def : WriteRes<WriteFCvtF64ToF16, [DaiteqPipeB]>;
+def : WriteRes<WriteFCvtI64ToF16, [DaiteqPipeB]>;
+def : WriteRes<WriteFCvtF32ToF16, [DaiteqPipeB]>;
+def : WriteRes<WriteFCvtI32ToF16, [DaiteqPipeB]>;
+def : WriteRes<WriteFCvtF16ToI64, [DaiteqPipeB]>;
+def : WriteRes<WriteFCvtF16ToF32, [DaiteqPipeB]>;
+def : WriteRes<WriteFCvtF16ToI32, [DaiteqPipeB]>;
+def : WriteRes<WriteFDiv16, [DaiteqPipeB]>;
+def : WriteRes<WriteFCmp16, [DaiteqPipeB]>;
+//def : WriteRes<WriteFLD16, [DaiteqPipeB]>;
+def : WriteRes<WriteFMA16, [DaiteqPipeB]>;
+def : WriteRes<WriteFMinMax16, [DaiteqPipeB]>;
+def : WriteRes<WriteFMul16, [DaiteqPipeB]>;
+def : WriteRes<WriteFMovI16ToF16, [DaiteqPipeB]>;
+def : WriteRes<WriteFMovF16ToI16, [DaiteqPipeB]>;
+def : WriteRes<WriteFSGNJ16, [DaiteqPipeB]>;
+//def : WriteRes<WriteFST16, [DaiteqPipeB]>;
+def : WriteRes<WriteFSqrt16, [DaiteqPipeB]>;
+}
+def : ReadAdvance<ReadFALU16v2, 0>;
+def : ReadAdvance<ReadFCmp16v2, 0>;
+def : ReadAdvance<ReadFDiv16v2, 0>;
+def : ReadAdvance<ReadFMul16v2, 0>;
+def : ReadAdvance<ReadFSqrt16v2, 0>;
+def : ReadAdvance<ReadFSGNJ16v2, 0>;
+def : ReadAdvance<ReadFMinMax16v2, 0>;
+def : ReadAdvance<ReadFClass16v2, 0>;
+def : ReadAdvance<ReadFMov16v2, 0>;
+def : ReadAdvance<ReadFSwap16v2, 0>;
+
+def : ReadAdvance<ReadFALU16, 0>;
+def : ReadAdvance<ReadFClass16, 0>;
+def : ReadAdvance<ReadFCvtF16ToF64, 0>;
+def : ReadAdvance<ReadFCvtF64ToF16, 0>;
+def : ReadAdvance<ReadFCvtI64ToF16, 0>;
+def : ReadAdvance<ReadFCvtF32ToF16, 0>;
+def : ReadAdvance<ReadFCvtI32ToF16, 0>;
+def : ReadAdvance<ReadFCvtF16ToI64, 0>;
+def : ReadAdvance<ReadFCvtF16ToF32, 0>;
+def : ReadAdvance<ReadFCvtF16ToI32, 0>;
+def : ReadAdvance<ReadFDiv16, 0>;
+def : ReadAdvance<ReadFCmp16, 0>;
+def : ReadAdvance<ReadFMA16, 0>;
+def : ReadAdvance<ReadFMinMax16, 0>;
+def : ReadAdvance<ReadFMul16, 0>;
+def : ReadAdvance<ReadFMovI16ToF16, 0>;
+def : ReadAdvance<ReadFMovF16ToI16, 0>;
+def : ReadAdvance<ReadFSGNJ16, 0>;
+def : ReadAdvance<ReadFSqrt16, 0>;
+
+//===----------------------------------------------------------------------===//
+// Unsupported extensions
+defm : UnsupportedSchedV;
+defm : UnsupportedSchedZba;
+defm : UnsupportedSchedZbb;
+//defm : UnsupportedSchedZfh;
+//defm : UnsupportedSchedXfph;
+}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedRocket.td b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
index 14f59152ed42..332c06a79cfc 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedRocket.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
@@ -237,4 +237,5 @@ defm : UnsupportedSchedV;
 defm : UnsupportedSchedZba;
 defm : UnsupportedSchedZbb;
 defm : UnsupportedSchedZfh;
+defm : UnsupportedSchedXfph;
 }
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 75ca6ca861be..343db13095fc 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -225,4 +225,5 @@ defm : UnsupportedSchedV;
 defm : UnsupportedSchedZba;
 defm : UnsupportedSchedZbb;
 defm : UnsupportedSchedZfh;
+defm : UnsupportedSchedXfph;
 }
diff --git a/llvm/lib/Target/RISCV/RISCVSchedule.td b/llvm/lib/Target/RISCV/RISCVSchedule.td
index 4971ca1d4e3e..efc1c1f8ce1d 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedule.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedule.td
@@ -98,10 +98,10 @@ def WriteFMovI32ToF32     : SchedWrite;
 def WriteFMovF64ToI64     : SchedWrite;    // RV64I only
 def WriteFMovI64ToF64     : SchedWrite;    // RV64I only
 
-def WriteFLD16        : SchedWrite;    // Floating point sp load
+def WriteFLD16        : SchedWrite;    // Floating point hp load
 def WriteFLD32        : SchedWrite;    // Floating point sp load
 def WriteFLD64        : SchedWrite;    // Floating point dp load
-def WriteFST16        : SchedWrite;    // Floating point sp store
+def WriteFST16        : SchedWrite;    // Floating point hp store
 def WriteFST32        : SchedWrite;    // Floating point sp store
 def WriteFST64        : SchedWrite;    // Floating point dp store
 
@@ -228,6 +228,59 @@ def : ReadAdvance<ReadFSqrt16, 0>;
 } // Unsupported = true
 }
 
+
+def WriteFLD16v2    : SchedWrite;    // Floating point php load
+def WriteFST16v2    : SchedWrite;    // Floating point php store
+def WriteFALU16v2   : SchedWrite;    // packed 2x 16-bit FP computation
+def WriteFCmp16v2   : SchedWrite;    // packed 2x 16-bit FP compare
+def WriteFMul16v2   : SchedWrite;    // 16-bit floating point multiply
+def WriteFDiv16v2   : SchedWrite;    // 16-bit floating point divide
+def WriteFSqrt16v2  : SchedWrite;    // 16-bit floating point sqrt
+def WriteFSGNJ16v2  : SchedWrite;    // 16-bit floating point sign-injection
+def WriteFMinMax16v2: SchedWrite;    // 16-bit floating point min or max
+def WriteFClass16v2 : SchedWrite;    // 16-bit floating point classify
+def WriteFMov16v2   : SchedWrite;
+def WriteFSwap16v2  : SchedWrite;
+
+def ReadFALU16v2    : SchedRead;    // packed FP 2x16-bit computation
+def ReadFCmp16v2    : SchedRead;
+def ReadFMul16v2    : SchedRead;    // 16-bit floating point multiply
+def ReadFDiv16v2    : SchedRead;    // 16-bit floating point divide
+def ReadFSqrt16v2   : SchedRead;    // 16-bit floating point sqrt
+def ReadFSGNJ16v2   : SchedRead;
+def ReadFMinMax16v2 : SchedRead;
+def ReadFClass16v2  : SchedRead;
+def ReadFMov16v2    : SchedRead;
+def ReadFSwap16v2   : SchedRead;
+
+multiclass UnsupportedSchedXfph {
+let Unsupported = true in {
+def : WriteRes<WriteFALU16v2, []>;
+def : WriteRes<WriteFCmp16v2, []>;
+def : WriteRes<WriteFDiv16v2, []>;
+def : WriteRes<WriteFLD16v2, []>;
+def : WriteRes<WriteFMul16v2, []>;
+def : WriteRes<WriteFST16v2, []>;
+def : WriteRes<WriteFSqrt16v2, []>;
+def : WriteRes<WriteFSGNJ16v2, []>;
+def : WriteRes<WriteFMinMax16v2, []>;
+def : WriteRes<WriteFClass16v2, []>;
+def : WriteRes<WriteFMov16v2, []>;
+def : WriteRes<WriteFSwap16v2, []>;
+
+def : ReadAdvance<ReadFALU16v2, 0>;
+def : ReadAdvance<ReadFCmp16v2, 0>;
+def : ReadAdvance<ReadFDiv16v2, 0>;
+def : ReadAdvance<ReadFMul16v2, 0>;
+def : ReadAdvance<ReadFSqrt16v2, 0>;
+def : ReadAdvance<ReadFSGNJ16v2, 0>;
+def : ReadAdvance<ReadFMinMax16v2, 0>;
+def : ReadAdvance<ReadFClass16v2, 0>;
+def : ReadAdvance<ReadFMov16v2, 0>;
+def : ReadAdvance<ReadFSwap16v2, 0>;
+}
+}
+
 // Include the scheduler resources for other instruction extensions.
 include "RISCVScheduleB.td"
 include "RISCVScheduleV.td"
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index b19fdcb0082b..10a0b06077a6 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -51,6 +51,13 @@ RISCVSubtarget &
 RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU,
                                                 StringRef TuneCPU, StringRef FS,
                                                 StringRef ABIName) {
+  // Reset MultiFeatures
+  for(unsigned i=0;i<32;++i) {
+    UseSoftFPopsHalf[i] = false;
+    UseSoftFPopsSingle[i] = false;
+    UseSoftFPopsDouble[i] = false;
+  }
+
   // Determine default and user-specified characteristics
   bool Is64Bit = TT.isArch64Bit();
   if (CPU.empty())
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index ce36331e044d..b2d266cc110f 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -55,11 +55,22 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
   bool HasStdExtZvlsseg = false;
   bool HasStdExtZvamo = false;
   bool HasStdExtZfh = false;
+  bool HasDaiExtXfph = false;
+  bool HasDaiExtXfps = false;
+  bool HasDaiExtXswar = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
   bool EnableLinkerRelax = false;
   bool EnableRVCHintInstrs = true;
   bool EnableSaveRestore = false;
+
+  // daiteq features - soft float FP operations
+  bool UseSoftFPopsHalf[32];
+  bool UseSoftFPopsSingle[32];
+  bool UseSoftFPopsDouble[32];
+  bool UseFPPackedHalf = false; /* duplicate Xfph */
+  bool UseFPPackedSingle = false; /* duplicate Xfps */
+
   unsigned XLen = 32;
   MVT XLenVT = MVT::i32;
   uint8_t MaxInterleaveFactor = 2;
@@ -123,6 +134,12 @@ public:
   bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; }
   bool hasStdExtZvamo() const { return HasStdExtZvamo; }
   bool hasStdExtZfh() const { return HasStdExtZfh; }
+  bool hasDaiExtXfph() const { return HasDaiExtXfph; }
+  bool hasDaiExtXfps() const { return HasDaiExtXfps; }
+  bool hasDaiExtXswar() const { return HasDaiExtXswar; }
+  bool isSoftFPHalf(unsigned fopidx) const { return UseSoftFPopsHalf[fopidx]; }
+  bool isSoftFPSingle(unsigned fopidx) const { return UseSoftFPopsSingle[fopidx]; }
+  bool isSoftFPDouble(unsigned fopidx) const { return UseSoftFPopsDouble[fopidx]; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index a561772b650b..ee750248dc7d 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -251,6 +251,15 @@ def : SysReg<"pmpaddr13", 0x3BD>;
 def : SysReg<"pmpaddr14", 0x3BE>;
 def : SysReg<"pmpaddr15", 0x3BF>;
 
+//===----------------------------------
+// Daiteq SWAR
+//===----------------------------------
+def : SysReg<"swarctrlstat", 0x400>;
+def : SysReg<"swaracc", 0x410>;
+let isRV32Only = 1 in {
+def : SysReg<"swaracchi", 0x411>;
+}
+
 
 //===--------------------------
 // Machine Counter and Timers
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index b18ee6009217..485f69286b21 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -84,6 +84,94 @@ RISCVTargetMachine::getSubtargetImpl(const Function &F) const {
       TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
   std::string FS =
       FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
+
+  if (F.hasFnAttribute("soft-fops-half")) {
+    unsigned val = std::stoul(F.getFnAttribute("soft-fops-half").getValueAsString().str(), NULL, 0);
+    if (val>0) {
+      if (val & llvm::SoftFops::FPOP_ADD)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fadd"; }
+      if (val & llvm::SoftFops::FPOP_SUB)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fsub"; }
+      if (val & llvm::SoftFops::FPOP_MUL)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fmul"; }
+      if (val & llvm::SoftFops::FPOP_DIV)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fdiv"; }
+      if (val & llvm::SoftFops::FPOP_MULEX) { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fmulex"; }
+      if (val & llvm::SoftFops::FPOP_SQRT) { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fsqrt"; }
+      if (val & llvm::SoftFops::FPOP_CMP)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fcmp"; }
+      if (val & llvm::SoftFops::FPOP_CI2F) { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fci2f"; }
+      if (val & llvm::SoftFops::FPOP_CF2I) { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fcf2i"; }
+      if (val & llvm::SoftFops::FPOP_CFUP) { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fcfup"; }
+      if (val & llvm::SoftFops::FPOP_CFDN) { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fcfdn"; }
+      if (val & llvm::SoftFops::FPOP_ABS) { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fabs"; }
+      //if (val & llvm::SoftFops::FPOP_PACK) { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-pack"; }
+      if (val & llvm::SoftFops::FPOP_MOV) { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fmov"; }
+      if (val & llvm::SoftFops::FPOP_NEG) { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fneg"; }
+    }
+  }
+  if (F.hasFnAttribute("soft-fops-single")) {
+    unsigned val = std::stoul(F.getFnAttribute("soft-fops-single").getValueAsString().str(), NULL, 0);
+    if (val>0) {
+      if (val & llvm::SoftFops::FPOP_ADD)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fadd"; }
+      if (val & llvm::SoftFops::FPOP_SUB)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fsub"; }
+      if (val & llvm::SoftFops::FPOP_MUL)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fmul"; }
+      if (val & llvm::SoftFops::FPOP_DIV)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fdiv"; }
+      if (val & llvm::SoftFops::FPOP_MULEX) { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fmulex"; }
+      if (val & llvm::SoftFops::FPOP_SQRT) { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fsqrt"; }
+      if (val & llvm::SoftFops::FPOP_CMP)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fcmp"; }
+      if (val & llvm::SoftFops::FPOP_CI2F) { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fci2f"; }
+      if (val & llvm::SoftFops::FPOP_CF2I) { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fcf2i"; }
+      if (val & llvm::SoftFops::FPOP_CFUP) { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fcfup"; }
+      if (val & llvm::SoftFops::FPOP_CFDN) { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fcfdn"; }
+      if (val & llvm::SoftFops::FPOP_ABS) { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fabs"; }
+      //if (val & llvm::SoftFops::FPOP_PACK) { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-pack"; }
+      if (val & llvm::SoftFops::FPOP_MOV) { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fmov"; }
+      if (val & llvm::SoftFops::FPOP_NEG) { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fneg"; }
+    }
+  }
+  if (F.hasFnAttribute("soft-fops-double")) {
+    unsigned val = std::stoul(F.getFnAttribute("soft-fops-double").getValueAsString().str(), NULL, 0);
+    if (val>0) {
+      if (val & llvm::SoftFops::FPOP_ADD)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fadd"; }
+      if (val & llvm::SoftFops::FPOP_SUB)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fsub"; }
+      if (val & llvm::SoftFops::FPOP_MUL)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fmul"; }
+      if (val & llvm::SoftFops::FPOP_DIV)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fdiv"; }
+      if (val & llvm::SoftFops::FPOP_MULEX) { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fmulex"; }
+      if (val & llvm::SoftFops::FPOP_SQRT) { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fsqrt"; }
+      if (val & llvm::SoftFops::FPOP_CMP)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fcmp"; }
+      if (val & llvm::SoftFops::FPOP_CI2F) { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fci2f"; }
+      if (val & llvm::SoftFops::FPOP_CF2I) { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fcf2i"; }
+      if (val & llvm::SoftFops::FPOP_CFUP) { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fcfup"; }
+      if (val & llvm::SoftFops::FPOP_CFDN) { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fcfdn"; }
+      if (val & llvm::SoftFops::FPOP_ABS) { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fabs"; }
+      //if (val & llvm::SoftFops::FPOP_PACK) { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-pack"; }
+      if (val & llvm::SoftFops::FPOP_MOV) { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fmov"; }
+      if (val & llvm::SoftFops::FPOP_NEG) { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fneg"; }
+    }
+  }
+  if (F.hasFnAttribute("soft-fops-packhalf")) {
+    unsigned val = std::stoul(F.getFnAttribute("soft-fops-packhalf").getValueAsString().str(), NULL, 0);
+    if (val>0) {
+      if (val & llvm::SoftFops::FPOP_ADD)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packhalf-fadd"; }
+      if (val & llvm::SoftFops::FPOP_SUB)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packhalf-fsub"; }
+      if (val & llvm::SoftFops::FPOP_MUL)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packhalf-fmul"; }
+      if (val & llvm::SoftFops::FPOP_DIV)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packhalf-fdiv"; }
+      if (val & llvm::SoftFops::FPOP_SQRT) { if (!FS.empty()) FS += ","; FS += "+soft-fops-packhalf-fsqrt"; }
+      if (val & llvm::SoftFops::FPOP_PACK) { if (!FS.empty()) FS += ","; FS += "+soft-fops-packhalf-pack"; }
+      if (val & llvm::SoftFops::FPOP_CMP)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packhalf-fcmp"; }
+      if (val & llvm::SoftFops::FPOP_MOV)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packhalf-fmov"; }  /* FMOVHU, FMOVHL, FSWAPH */
+    }
+  }
+  if (F.hasFnAttribute("soft-fops-packsingle")) {
+    unsigned val = std::stoul(F.getFnAttribute("soft-fops-packsingle").getValueAsString().str(), NULL, 0);
+    if (val>0) {
+      if (val & llvm::SoftFops::FPOP_ADD)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packsingle-fadd"; }
+      if (val & llvm::SoftFops::FPOP_SUB)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packsingle-fsub"; }
+      if (val & llvm::SoftFops::FPOP_MUL)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packsingle-fmul"; }
+      if (val & llvm::SoftFops::FPOP_DIV)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packsingle-fdiv"; }
+      if (val & llvm::SoftFops::FPOP_SQRT) { if (!FS.empty()) FS += ","; FS += "+soft-fops-packsingle-fsqrt"; }
+      if (val & llvm::SoftFops::FPOP_PACK) { if (!FS.empty()) FS += ","; FS += "+soft-fops-packsingle-pack"; }
+      if (val & llvm::SoftFops::FPOP_CMP)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packsingle-fcmp"; }
+    }
+  }
+
+
   std::string Key = CPU + TuneCPU + FS;
   auto &I = SubtargetMap[Key];
   if (!I) {
diff --git a/llvm/lib/Target/Sparc/DelaySlotFiller.cpp b/llvm/lib/Target/Sparc/DelaySlotFiller.cpp
index 7319924a24ba..036361b7b615 100644
--- a/llvm/lib/Target/Sparc/DelaySlotFiller.cpp
+++ b/llvm/lib/Target/Sparc/DelaySlotFiller.cpp
@@ -123,7 +123,9 @@ bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
     // TODO: If we ever want to support v7, this needs to be extended
     // to cover all floating point operations.
     if (!Subtarget->isV9() &&
-        (MI->getOpcode() == SP::FCMPS || MI->getOpcode() == SP::FCMPD
+        (MI->getOpcode() == SP::FCMPH
+         || MI->getOpcode() == SP::FCMPS
+         || MI->getOpcode() == SP::FCMPD
          || MI->getOpcode() == SP::FCMPQ)) {
       BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP));
       Changed = true;
diff --git a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
index 5c4419c108c0..28281a34e8be 100644
--- a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
+++ b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
@@ -164,6 +164,30 @@ static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst,
   return MCDisassembler::Success;
 }
 
+/* the same as for IntRegs */
+static DecodeStatus DecodeSwarRegsRegisterClass(MCInst &Inst,
+                                               unsigned RegNo,
+                                               uint64_t Address,
+                                               const void *Decoder) {
+  if (RegNo > 31)
+    return MCDisassembler::Fail;
+  unsigned Reg = IntRegDecoderTable[RegNo];
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
+
+static DecodeStatus DecodeHFPRegsRegisterClass(MCInst &Inst,
+                                               unsigned RegNo,
+                                               uint64_t Address,
+                                               const void *Decoder) {
+  if (RegNo > 31)
+    return MCDisassembler::Fail;
+  unsigned Reg = FPRegDecoderTable[RegNo];
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
 
 static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst,
                                               unsigned RegNo,
@@ -203,6 +227,31 @@ static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst,
   return MCDisassembler::Success;
 }
 
+
+static DecodeStatus DecodePFPHRegsRegisterClass(MCInst &Inst,
+                                               unsigned RegNo,
+                                               uint64_t Address,
+                                               const void *Decoder) {
+  if (RegNo > 31)
+    return MCDisassembler::Fail;
+  unsigned Reg = FPRegDecoderTable[RegNo];
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
+
+static DecodeStatus DecodePFPSRegsRegisterClass(MCInst &Inst,
+                                               unsigned RegNo,
+                                               uint64_t Address,
+                                               const void *Decoder) {
+  if (RegNo > 31)
+    return MCDisassembler::Fail;
+  unsigned Reg = DFPRegDecoderTable[RegNo];
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
+
 static DecodeStatus DecodeCPRegsRegisterClass(MCInst &Inst,
                                                unsigned RegNo,
                                                uint64_t Address,
@@ -270,12 +319,20 @@ static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
                                   const void *Decoder);
 static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Address,
                                   const void *Decoder);
+static DecodeStatus DecodeLoadSwar(MCInst &Inst, unsigned insn, uint64_t Address,
+                                  const void *Decoder);
+static DecodeStatus DecodeLoadHFP(MCInst &Inst, unsigned insn, uint64_t Address,
+                                 const void *Decoder);
 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
                                  const void *Decoder);
 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
                                   const void *Decoder);
 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
                                   const void *Decoder);
+static DecodeStatus DecodeLoadPFPH(MCInst &Inst, unsigned insn, uint64_t Address,
+                                 const void *Decoder);
+static DecodeStatus DecodeLoadPFPS(MCInst &Inst, unsigned insn, uint64_t Address,
+                                 const void *Decoder);
 static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address,
                                   const void *Decoder);
 static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address,
@@ -284,12 +341,20 @@ static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
                                    uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn,
                                    uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeStoreSwar(MCInst &Inst, unsigned insn,
+                                   uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeStoreHFP(MCInst &Inst, unsigned insn,
+                                  uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn,
                                   uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
                                    uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
                                    uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeStorePFPH(MCInst &Inst, unsigned insn,
+                                  uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeStorePFPS(MCInst &Inst, unsigned insn,
+                                  uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn,
                                    uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn,
@@ -426,6 +491,18 @@ static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Addr
                    DecodeIntPairRegisterClass);
 }
 
+static DecodeStatus DecodeLoadSwar(MCInst &Inst, unsigned insn, uint64_t Address,
+                                  const void *Decoder) {
+  return DecodeMem(Inst, insn, Address, Decoder, true,
+                   DecodeSwarRegsRegisterClass);
+}
+
+static DecodeStatus DecodeLoadHFP(MCInst &Inst, unsigned insn, uint64_t Address,
+                                 const void *Decoder) {
+  return DecodeMem(Inst, insn, Address, Decoder, true,
+                   DecodeHFPRegsRegisterClass);
+}
+
 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
                                  const void *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, true,
@@ -444,6 +521,18 @@ static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
                    DecodeQFPRegsRegisterClass);
 }
 
+static DecodeStatus DecodeLoadPFPH(MCInst &Inst, unsigned insn, uint64_t Address,
+                                 const void *Decoder) {
+  return DecodeMem(Inst, insn, Address, Decoder, true,
+                   DecodePFPHRegsRegisterClass);
+}
+
+static DecodeStatus DecodeLoadPFPS(MCInst &Inst, unsigned insn, uint64_t Address,
+                                 const void *Decoder) {
+  return DecodeMem(Inst, insn, Address, Decoder, true,
+                   DecodePFPSRegsRegisterClass);
+}
+
 static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address,
                                   const void *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, true,
@@ -468,6 +557,18 @@ static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn,
                    DecodeIntPairRegisterClass);
 }
 
+static DecodeStatus DecodeStoreSwar(MCInst &Inst, unsigned insn,
+                                   uint64_t Address, const void *Decoder) {
+  return DecodeMem(Inst, insn, Address, Decoder, false,
+                   DecodeSwarRegsRegisterClass);
+}
+
+static DecodeStatus DecodeStoreHFP(MCInst &Inst, unsigned insn, uint64_t Address,
+                                  const void *Decoder) {
+  return DecodeMem(Inst, insn, Address, Decoder, false,
+                   DecodeHFPRegsRegisterClass);
+}
+
 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address,
                                   const void *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, false,
@@ -486,6 +587,18 @@ static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
                    DecodeQFPRegsRegisterClass);
 }
 
+static DecodeStatus DecodeStorePFPH(MCInst &Inst, unsigned insn, uint64_t Address,
+                                  const void *Decoder) {
+  return DecodeMem(Inst, insn, Address, Decoder, false,
+                   DecodePFPHRegsRegisterClass);
+}
+
+static DecodeStatus DecodeStorePFPS(MCInst &Inst, unsigned insn, uint64_t Address,
+                                  const void *Decoder) {
+  return DecodeMem(Inst, insn, Address, Decoder, false,
+                   DecodePFPSRegsRegisterClass);
+}
+
 static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn,
                                    uint64_t Address, const void *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, false,
diff --git a/llvm/lib/Target/Sparc/LeonFeatures.td b/llvm/lib/Target/Sparc/LeonFeatures.td
index 75273eff1868..f87aee1aef65 100644
--- a/llvm/lib/Target/Sparc/LeonFeatures.td
+++ b/llvm/lib/Target/Sparc/LeonFeatures.td
@@ -61,3 +61,10 @@ def FixAllFDIVSQRT : SubtargetFeature<
 def LeonCycleCounter
   : SubtargetFeature<"leoncyclecounter", "HasLeonCycleCounter", "true",
                      "Use the Leon cycle counter register">;
+
+def InsertNOPYDIV: SubtargetFeature<
+  "insertnopydiv",
+  "InsertNOPYDIV",
+  "true",
+  "LEON2 fix: Insert three NOP instructions between every WRY and SDIV/UDIV instructions"
+>;
diff --git a/llvm/lib/Target/Sparc/LeonPasses.cpp b/llvm/lib/Target/Sparc/LeonPasses.cpp
index fa05a41f3127..7f727f7ac4e0 100644
--- a/llvm/lib/Target/Sparc/LeonPasses.cpp
+++ b/llvm/lib/Target/Sparc/LeonPasses.cpp
@@ -154,3 +154,52 @@ bool FixAllFDIVSQRT::runOnMachineFunction(MachineFunction &MF) {
 
   return Modified;
 }
+
+
+//*****************************************************************************
+//**** InsertNOPYDIV pass
+//*****************************************************************************
+// This pass fixes the using of old value from Y register in SDIV/UDIV
+// instruction if the Y register is set immediately before the SDIV/UDIV
+// instruction. Three NOP are inserted before these two instructions.
+// The bug is in the LEON processors at least.
+//
+// This pass inserts three NOP instructions between WRY and SDIV/UDIV
+// instructions.
+//
+char InsertNOPYDIV::ID = 0;
+
+InsertNOPYDIV::InsertNOPYDIV() : LEONMachineFunctionPass(ID) {}
+
+bool InsertNOPYDIV::runOnMachineFunction(MachineFunction &MF) {
+  Subtarget = &MF.getSubtarget<SparcSubtarget>();
+  const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
+  DebugLoc DL = DebugLoc();
+
+  bool Modified = false;
+  for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
+    MachineBasicBlock &MBB = *MFI;
+    for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
+      MachineInstr &MI = *MBBI;
+      unsigned Opcode = MI.getOpcode();
+      unsigned PrevOpcode = 0;
+      if (MBBI!=MBB.begin()) {
+        auto PMBBI = std::prev(MBBI);
+        MachineInstr &PMI = *PMBBI;
+        PrevOpcode = PMI.getOpcode();
+      }
+      /* TO DO: There should be a test for WRY instruction (WRASR with rd=0) and not only for any WRASR. */
+      if ((PrevOpcode == SP::WRASRrr || PrevOpcode == SP::WRASRri) &&
+          (Opcode == SP::SDIVrr || Opcode == SP::SDIVri ||
+           Opcode == SP::UDIVrr || Opcode == SP::UDIVri)) {
+        for (int InsertedCount = 0; InsertedCount < 3; InsertedCount++)
+          BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
+
+        Modified = true;
+      }
+
+    }
+  }
+
+  return Modified;
+}
diff --git a/llvm/lib/Target/Sparc/LeonPasses.h b/llvm/lib/Target/Sparc/LeonPasses.h
index 9bc4569a1298..8752e0af18e3 100644
--- a/llvm/lib/Target/Sparc/LeonPasses.h
+++ b/llvm/lib/Target/Sparc/LeonPasses.h
@@ -77,6 +77,19 @@ public:
            "instructions with NOPs and floating-point store";
   }
 };
+
+class LLVM_LIBRARY_VISIBILITY InsertNOPYDIV : public LEONMachineFunctionPass {
+public:
+  static char ID;
+
+  InsertNOPYDIV();
+  bool runOnMachineFunction(MachineFunction &MF) override;
+
+  StringRef getPassName() const override {
+    return "InsertNOPYDIV: insert three NOP instructions between "
+           "every WRY and SDIV/UDIV instructions";
+  }
+};
 } // namespace llvm
 
 #endif // LLVM_LIB_TARGET_SPARC_LEON_PASSES_H
diff --git a/llvm/lib/Target/Sparc/Sparc.td b/llvm/lib/Target/Sparc/Sparc.td
index da95602309a1..996ff09b04d8 100644
--- a/llvm/lib/Target/Sparc/Sparc.td
+++ b/llvm/lib/Target/Sparc/Sparc.td
@@ -62,6 +62,101 @@ def UsePopc : SubtargetFeature<"popc", "UsePopc", "true",
 def FeatureSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
                               "Use software emulation for floating point">;
 
+def FeatureSoftFADDHalf : SubtargetFeature<"soft-fops-half-fadd", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_ADD]", "true",
+           "Use software emulation for FADDh">;
+def FeatureSoftFSUBHalf : SubtargetFeature<"soft-fops-half-fsub", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_SUB]", "true",
+           "Use software emulation for FSUBh">;
+def FeatureSoftFMULHalf : SubtargetFeature<"soft-fops-half-fmul", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_MUL]", "true",
+           "Use software emulation for FMULh">;
+def FeatureSoftFDIVHalf : SubtargetFeature<"soft-fops-half-fdiv", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_DIV]", "true",
+           "Use software emulation for FDIVh">;
+def FeatureSoftFMULEXHalf : SubtargetFeature<"soft-fops-half-fmulex", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_MULEX]", "true",
+           "Use software emulation for FHMULS">;
+def FeatureSoftFSQRTHalf : SubtargetFeature<"soft-fops-half-fsqrt", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_SQRT]", "true",
+           "Use software emulation for FSQRTh">;
+def FeatureSoftFCMPHalf : SubtargetFeature<"soft-fops-half-fcmp", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_CMP]", "true",
+           "Use software emulation for FCMPh, FCMPEh">;
+def FeatureSoftFCI2FHalf : SubtargetFeature<"soft-fops-half-fci2f", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_CI2F]", "true",
+           "Use software emulation for FITOH">;
+def FeatureSoftFCF2IHalf : SubtargetFeature<"soft-fops-half-fcf2i", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_CF2I]", "true",
+           "Use software emulation for FHTOI">;
+def FeatureSoftFCFUPHalf : SubtargetFeature<"soft-fops-half-fcfup", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_CFUP]", "true",
+           "Use software emulation for FHTOS">;
+def FeatureSoftFCFDNHalf : SubtargetFeature<"soft-fops-half-fcfdn", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_CFDN]", "true",
+           "Use software emulation for FHTOS">;
+def FeatureSoftFABSHalf : SubtargetFeature<"soft-fops-half-fabs", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_ABS]", "true",
+           "Use software emulation for FABSh">;
+def FeatureSoftFMOVHalf : SubtargetFeature<"soft-fops-half-fmov", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_MOV]", "true",
+           "Use software emulation for FMOVh">;
+def FeatureSoftFNEGHalf : SubtargetFeature<"soft-fops-half-fneg", "UseSoftFPopsHalf[llvm::SoftFops::SOFTFP_NEG]", "true",
+           "Use software emulation for FNEGh">;
+
+def FeatureSoftFADDSingle : SubtargetFeature<"soft-fops-single-fadd", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_ADD]", "true",
+           "Use software emulation for FADDs">;
+def FeatureSoftFSUBSingle : SubtargetFeature<"soft-fops-single-fsub", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_SUB]", "true",
+           "Use software emulation for FSUBs">;
+def FeatureSoftFMULSingle : SubtargetFeature<"soft-fops-single-fmul", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_MUL]", "true",
+           "Use software emulation for FMULs">;
+def FeatureSoftFDIVSingle : SubtargetFeature<"soft-fops-single-fdiv", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_DIV]", "true",
+           "Use software emulation for FDIVs">;
+def FeatureSoftFMULEXSingle : SubtargetFeature<"soft-fops-single-fmulex", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_MULEX]", "true",
+           "Use software emulation for FSMULD">;
+def FeatureSoftFSQRTSingle : SubtargetFeature<"soft-fops-single-fsqrt", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_SQRT]", "true",
+           "Use software emulation for FSQRTs">;
+def FeatureSoftFCMPSingle : SubtargetFeature<"soft-fops-single-fcmp", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_CMP]", "true",
+           "Use software emulation for FCMPs, FCMPEs">;
+def FeatureSoftFCI2FSingle : SubtargetFeature<"soft-fops-single-fci2f", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_CI2F]", "true",
+           "Use software emulation for FITOS">;
+def FeatureSoftFCF2ISingle : SubtargetFeature<"soft-fops-single-fcf2i", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_CF2I]", "true",
+           "Use software emulation for FSTOI">;
+def FeatureSoftFCFUPSingle : SubtargetFeature<"soft-fops-single-fcfup", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_CFUP]", "true",
+           "Use software emulation for FSTOD">;
+def FeatureSoftFCFDNSingle : SubtargetFeature<"soft-fops-single-fcfdn", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_CFDN]", "true",
+           "Use software emulation for FSTOH">;
+def FeatureSoftFABSSingle : SubtargetFeature<"soft-fops-single-fabs", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_ABS]", "true",
+           "Use software emulation for FABSs">;
+def FeatureSoftFMOVSingle : SubtargetFeature<"soft-fops-single-fmov", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_MOV]", "true",
+           "Use software emulation for FMOVs">;
+def FeatureSoftFNEGSingle : SubtargetFeature<"soft-fops-single-fneg", "UseSoftFPopsSingle[llvm::SoftFops::SOFTFP_NEG]", "true",
+           "Use software emulation for FNEGs">;
+
+def FeatureSoftFADDDouble : SubtargetFeature<"soft-fops-double-fadd", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_ADD]", "true",
+           "Use software emulation for FADDd">;
+def FeatureSoftFSUBDouble : SubtargetFeature<"soft-fops-double-fsub", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_SUB]", "true",
+           "Use software emulation for FSUBd">;
+def FeatureSoftFMULDouble : SubtargetFeature<"soft-fops-double-fmul", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_MUL]", "true",
+           "Use software emulation for FMULd">;
+def FeatureSoftFDIVDouble : SubtargetFeature<"soft-fops-double-fdiv", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_DIV]", "true",
+           "Use software emulation for FDIVd">;
+def FeatureSoftFMULEXDouble : SubtargetFeature<"soft-fops-double-fmulex", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_MULEX]", "true",
+           "Use software emulation for FDMULQ">;
+def FeatureSoftFSQRTDouble : SubtargetFeature<"soft-fops-double-fsqrt", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_SQRT]", "true",
+           "Use software emulation for FSQRTd">;
+def FeatureSoftFCMPDouble : SubtargetFeature<"soft-fops-double-fcmp", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_CMP]", "true",
+           "Use software emulation for FCMPd, FCMPEd">;
+def FeatureSoftFCI2FDouble : SubtargetFeature<"soft-fops-double-fci2f", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_CI2F]", "true",
+           "Use software emulation for FITOD">;
+def FeatureSoftFCF2IDouble : SubtargetFeature<"soft-fops-double-fcf2i", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_CF2I]", "true",
+           "Use software emulation for FDTOI">;
+def FeatureSoftFCFUPDouble : SubtargetFeature<"soft-fops-double-fcfup", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_CFUP]", "true",
+           "Use software emulation for FDTOQ">;
+def FeatureSoftFCFDNDouble : SubtargetFeature<"soft-fops-double-fcfdn", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_CFDN]", "true",
+           "Use software emulation for FDTOS">;
+def FeatureSoftFABSDouble : SubtargetFeature<"soft-fops-double-fabs", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_ABS]", "true",
+           "Use software emulation for FABSd">;
+def FeatureSoftFMOVDouble : SubtargetFeature<"soft-fops-double-fmov", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_MOV]", "true",
+           "Use software emulation for FMOVd">;
+def FeatureSoftFNEGDouble : SubtargetFeature<"soft-fops-double-fneg", "UseSoftFPopsDouble[llvm::SoftFops::SOFTFP_NEG]", "true",
+           "Use software emulation for FNEGd">;
+
+
+def FeaturePackedHalf : SubtargetFeature<"enable-packedhalf", "UseFPPackedHalf", "true",
+           "Use packed half FP type">;
+def FeaturePackedSingle : SubtargetFeature<"enable-packedsingle", "UseFPPackedSingle", "true",
+           "Use packed single FP type">;
+def FeatureUnalignedPackedFP : SubtargetFeature<"unaligned-packed-fp", "AllowUnalignedPackedFP", "true",
+           "Allow unaligned packed FP variables">;
+
 //==== Features added predmoninantly for LEON subtarget support
 include "LeonFeatures.td"
 
@@ -127,17 +222,17 @@ def : Proc<"niagara4",        [FeatureV9, FeatureV8Deprecated, UsePopc,
 
 // LEON 2 FT generic
 def : Processor<"leon2", LEON2Itineraries,
-                [FeatureLeon]>;
+                [FeatureLeon, InsertNOPYDIV]>;
 
 // LEON 2 FT (AT697E)
 // TO DO: Place-holder: Processor specific features will be added *very* soon here.
 def : Processor<"at697e", LEON2Itineraries,
-                [FeatureLeon, InsertNOPLoad]>;
+                [FeatureLeon, InsertNOPLoad, InsertNOPYDIV]>;
 
 // LEON 2 FT (AT697F)
 // TO DO: Place-holder: Processor specific features will be added *very* soon here.
 def : Processor<"at697f", LEON2Itineraries,
-                [FeatureLeon, InsertNOPLoad]>;
+                [FeatureLeon, InsertNOPLoad, InsertNOPYDIV]>;
 
 
 // LEON 3 FT generic
diff --git a/llvm/lib/Target/Sparc/SparcCallingConv.td b/llvm/lib/Target/Sparc/SparcCallingConv.td
index db540d6f0c42..34809f85617a 100644
--- a/llvm/lib/Target/Sparc/SparcCallingConv.td
+++ b/llvm/lib/Target/Sparc/SparcCallingConv.td
@@ -17,10 +17,10 @@
 def CC_Sparc32 : CallingConv<[
   // Custom assign SRet to [sp+64].
   CCIfSRet<CCCustom<"CC_Sparc_Assign_SRet">>,
-  // i32 f32 arguments get passed in integer registers if there is space.
-  CCIfType<[i32, f32], CCAssignToReg<[I0, I1, I2, I3, I4, I5]>>,
+  // i32 f16 f32 arguments get passed in integer registers if there is space.
+  CCIfType<[i32, f16, f32, v2f16], CCAssignToReg<[I0, I1, I2, I3, I4, I5]>>,
   // f64 arguments are split and passed through registers or through stack.
-  CCIfType<[f64], CCCustom<"CC_Sparc_Assign_Split_64">>,
+  CCIfType<[f64, v2f32], CCCustom<"CC_Sparc_Assign_Split_64">>,
   // As are v2i32 arguments (this would be the default behavior for
   // v2i32 if it wasn't allocated to the IntPair register-class)
   CCIfType<[v2i32], CCCustom<"CC_Sparc_Assign_Split_64">>,
@@ -32,8 +32,8 @@ def CC_Sparc32 : CallingConv<[
 
 def RetCC_Sparc32 : CallingConv<[
   CCIfType<[i32], CCAssignToReg<[I0, I1, I2, I3, I4, I5]>>,
-  CCIfType<[f32], CCAssignToReg<[F0, F1, F2, F3]>>,
-  CCIfType<[f64], CCAssignToReg<[D0, D1]>>,
+  CCIfType<[f32, f16, v2f16], CCAssignToReg<[F0, F1, F2, F3]>>,
+  CCIfType<[f64, v2f32], CCAssignToReg<[D0, D1]>>,
   CCIfType<[v2i32], CCCustom<"CC_Sparc_Assign_Ret_Split_64">>
 ]>;
 
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index 2007303d9903..a9e439dfe8a1 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -413,7 +413,9 @@ SDValue SparcTargetLowering::LowerFormalArguments_32(
 
     if (VA.isRegLoc()) {
       if (VA.needsCustom()) {
-        assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
+        assert(VA.getLocVT() == MVT::f64 ||
+               VA.getLocVT() == MVT::v2i32 ||
+               VA.getLocVT() == MVT::v2f32);
 
         Register VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
         MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
@@ -446,9 +448,14 @@ SDValue SparcTargetLowering::LowerFormalArguments_32(
       Register VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
       MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
       SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
-      if (VA.getLocVT() == MVT::f32)
+      if (VA.getLocVT() == MVT::f16) {
+        Arg = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Arg);
+        Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f16, Arg);
+      } else if (VA.getLocVT() == MVT::f32) {
         Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
-      else if (VA.getLocVT() != MVT::i32) {
+      } else if (VA.getLocVT() == MVT::v2f16) {
+        Arg = DAG.getNode(ISD::BITCAST, dl, MVT::v2f16, Arg);
+      } else if (VA.getLocVT() != MVT::i32) {
         Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg,
                           DAG.getValueType(VA.getLocVT()));
         Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg);
@@ -463,7 +470,9 @@ SDValue SparcTargetLowering::LowerFormalArguments_32(
     auto PtrVT = getPointerTy(DAG.getDataLayout());
 
     if (VA.needsCustom()) {
-      assert(VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::v2i32);
+      assert(VA.getValVT() == MVT::f64 ||
+             VA.getValVT() == MVT::v2i32 ||
+             VA.getValVT() == MVT::v2f32);
       // If it is double-word aligned, just load.
       if (Offset % 8 == 0) {
         int FI = MF.getFrameInfo().CreateFixedObject(8,
@@ -505,11 +514,16 @@ SDValue SparcTargetLowering::LowerFormalArguments_32(
                                                  true);
     SDValue FIPtr = DAG.getFrameIndex(FI, PtrVT);
     SDValue Load ;
-    if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) {
+    if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32 ||
+        VA.getValVT() == MVT::f16) {
       Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, MachinePointerInfo());
     } else if (VA.getValVT() == MVT::f128) {
       report_fatal_error("SPARCv8 does not handle f128 in calls; "
                          "pass indirectly");
+    } else if (VA.getValVT() == MVT::v2f16) {
+      Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, MachinePointerInfo());
+    } else if (VA.getValVT() == MVT::v2f32) {
+      Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, MachinePointerInfo());
     } else {
       // We shouldn't see any other value types here.
       llvm_unreachable("Unexpected ValVT encountered in frame lowering.");
@@ -832,7 +846,9 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
     }
 
     if (VA.needsCustom()) {
-      assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
+      assert(VA.getLocVT() == MVT::f64 ||
+             VA.getLocVT() == MVT::v2i32 ||
+             VA.getLocVT()==MVT::v2f32);
 
       if (VA.isMemLoc()) {
         unsigned Offset = VA.getLocMemOffset() + StackOffset;
@@ -851,9 +867,11 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
         // Move from the float value from float registers into the
         // integer registers.
         if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Arg))
-          Arg = bitcastConstantFPToInt(C, dl, DAG);
+          Arg = bitcastConstantFPToInt64(C, dl, DAG);
         else
           Arg = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, Arg);
+      } else if (VA.getLocVT() == MVT::v2f32) {
+        Arg = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, Arg);
       }
 
       SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
@@ -898,11 +916,23 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
     // Arguments that can be passed on register must be kept at
     // RegsToPass vector
     if (VA.isRegLoc()) {
-      if (VA.getLocVT() != MVT::f32) {
+      if (VA.getLocVT() == MVT::f16) {
+        // store f16 and load it as i32 (and shift to LSB
+        MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
+        int FI = MFI.CreateStackObject(4, Align(4), false);
+        SDValue FIPtr = DAG.getFrameIndex(FI, MVT::i32); // getPointerTy(DAG.getDataLayout()));
+        MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIPtr, MachinePointerInfo()));
+        SDValue NArg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, MachinePointerInfo());
+        NArg = DAG.getNode(ISD::SRL, dl, MVT::i32, NArg, DAG.getConstant(16, dl, MVT::i32));
+        RegsToPass.push_back(std::make_pair(VA.getLocReg(), NArg));
+        continue;
+      } else
+      if (VA.getLocVT() == MVT::f32 || VA.getLocVT() == MVT::v2f16) {
+        Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
         RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
         continue;
       }
-      Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
+      // all types others than custom (i64/f64,v2i32), f16, f32, v2f16
       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
       continue;
     }
@@ -1420,11 +1450,36 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
 
   // Set up the register classes.
   addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
-  if (!Subtarget->useSoftFloat()) {
+
+  if (!Subtarget->useSoftFloat() &&
+     (Subtarget->useHardHalf() || Subtarget->useHardSingle() ||
+      Subtarget->useHardDouble())) {
+    if (Subtarget->useHardHalf())
+      addRegisterClass(MVT::f16, &SP::HFPRegsRegClass);
     addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
     addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
     addRegisterClass(MVT::f128, &SP::QFPRegsRegClass);
+    if (Subtarget->usePackedHalf())
+      addRegisterClass(MVT::v2f16, &SP::PFPHRegsRegClass);
+    if (Subtarget->usePackedSingle())
+      addRegisterClass(MVT::v2f32, &SP::PFPSRegsRegClass);
+  }
+
+/* TODO: option for enabling swar */
+  for (MVT VT : MVT::subword_vector_valuetypes()) {
+    addRegisterClass(VT, &SP::SwarRegsRegClass);
+    setOperationAction(ISD::LOAD, VT, Legal);
+    setOperationAction(ISD::STORE, VT, Legal);
+
+    setOperationAction(ISD::ADD, VT, Custom);
+    setOperationAction(ISD::SUB, VT, Custom);
+    setOperationAction(ISD::MUL, VT, Custom);
+    setOperationAction(ISD::BITCAST, VT, Expand);
+    setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);  /* vs1p32-vs16p32 = insert(svec, selm, const idx) or (svec, const i32, const idx) */
+    setOperationAction(ISD::BUILD_VECTOR, VT, Custom);  /* vs1p32-vs16p32 = build_vector(svec, selm, const idx) or (svec, const i32, const idx) */
+    setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);  /* vs1p32-vs16p32 = extract(svec, selm, const idx) or (svec, const i32, const idx) */
   }
+
   if (Subtarget->is64Bit()) {
     addRegisterClass(MVT::i64, &SP::I64RegsRegClass);
   } else {
@@ -1465,6 +1520,26 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
     //    AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
   }
 
+  // daiteq
+  if (Subtarget->usePackedHalf()) {
+    setOperationAction(ISD::LOAD, MVT::v2f16, Legal);
+    setOperationAction(ISD::STORE, MVT::v2f16, Legal);
+    setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom); /* use different operations for each element */
+    setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f16, Custom);  /* v2f16 = insert(v2f16, f16, const idx) */
+    setOperationAction(ISD::BUILD_VECTOR, MVT::v2f16, Custom);
+    setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f16, Custom);
+  }
+
+  if (Subtarget->usePackedSingle()) {
+    setOperationAction(ISD::LOAD, MVT::v2f32, Custom);
+    setOperationAction(ISD::STORE, MVT::v2f32, Custom);
+    setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f32, Legal);
+    setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Legal);
+    setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Legal);
+    setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f32, Expand);
+  }
+
+
   // Turn FP extload into load/fpextend
   for (MVT VT : MVT::fp_valuetypes()) {
     setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
@@ -1529,16 +1604,21 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::FP16_TO_FP, MVT::f128, Expand);
   setOperationAction(ISD::FP_TO_FP16, MVT::f128, Expand);
 
+  setOperationAction(ISD::BITCAST, MVT::f16, Expand);
+  setOperationAction(ISD::BITCAST, MVT::i16, Expand);
   setOperationAction(ISD::BITCAST, MVT::f32, Expand);
   setOperationAction(ISD::BITCAST, MVT::i32, Expand);
+  setOperationAction(ISD::BITCAST, MVT::f64, Expand);
 
   // Sparc has no select or setcc: expand to SELECT_CC.
   setOperationAction(ISD::SELECT, MVT::i32, Expand);
+  setOperationAction(ISD::SELECT, MVT::f16, Expand);
   setOperationAction(ISD::SELECT, MVT::f32, Expand);
   setOperationAction(ISD::SELECT, MVT::f64, Expand);
   setOperationAction(ISD::SELECT, MVT::f128, Expand);
 
   setOperationAction(ISD::SETCC, MVT::i32, Expand);
+  setOperationAction(ISD::SETCC, MVT::f16, Expand);
   setOperationAction(ISD::SETCC, MVT::f32, Expand);
   setOperationAction(ISD::SETCC, MVT::f64, Expand);
   setOperationAction(ISD::SETCC, MVT::f128, Expand);
@@ -1548,11 +1628,13 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::BRIND, MVT::Other, Expand);
   setOperationAction(ISD::BR_JT, MVT::Other, Expand);
   setOperationAction(ISD::BR_CC, MVT::i32, Custom);
+  setOperationAction(ISD::BR_CC, MVT::f16, Custom);
   setOperationAction(ISD::BR_CC, MVT::f32, Custom);
   setOperationAction(ISD::BR_CC, MVT::f64, Custom);
   setOperationAction(ISD::BR_CC, MVT::f128, Custom);
 
   setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
+  setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
   setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
   setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
   setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
@@ -1800,14 +1882,237 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
   if (Subtarget->fixAllFDIVSQRT()) {
     // Promote FDIVS and FSQRTS to FDIVD and FSQRTD instructions instead as
     // the former instructions generate errata on LEON processors.
-    setOperationAction(ISD::FDIV, MVT::f32, Promote);
-    setOperationAction(ISD::FSQRT, MVT::f32, Promote);
+    if (Subtarget->useSoftFopDouble(SoftFops::SOFTFP_DIV) &&
+       !Subtarget->useSoftFopSingle(SoftFops::SOFTFP_DIV)) {
+      setOperationAction(ISD::FDIV, MVT::f32, Promote);
+    }
+
+    if (Subtarget->useSoftFopDouble(SoftFops::SOFTFP_SQRT) &&
+       !Subtarget->useSoftFopSingle(SoftFops::SOFTFP_SQRT)) {
+      setOperationAction(ISD::FSQRT, MVT::f32, Promote);
+    }
   }
 
   if (Subtarget->hasNoFMULS()) {
     setOperationAction(ISD::FMUL, MVT::f32, Promote);
   }
 
+  if (Subtarget->usePackedHalf())
+    setOperationAction(ISD::BITCAST, MVT::v2f16, Expand);
+
+  if (Subtarget->usePackedSingle())
+    setOperationAction(ISD::BITCAST, MVT::v2f32, Expand);
+
+  if (Subtarget->useSoftFopHalf(SoftFops::SOFTFP_ADD)) {
+    setOperationAction(ISD::FADD, MVT::f16, Custom);
+  } else {
+    setOperationAction(ISD::FADD, MVT::f16, Legal);
+  }
+
+  if (!Subtarget->useSoftFopHalf(SoftFops::SOFTFP_ADD) &&
+        Subtarget->usePackedHalf())
+    setOperationAction(ISD::FADD,  MVT::v2f16, Legal);
+  else
+    setOperationAction(ISD::FADD,  MVT::v2f16, Custom);
+
+  if (Subtarget->useSoftFopHalf(SoftFops::SOFTFP_SUB))
+    setOperationAction(ISD::FSUB, MVT::f16, Custom);
+  else
+    setOperationAction(ISD::FSUB,  MVT::f16, Legal);
+
+  if (!Subtarget->useSoftFopHalf(SoftFops::SOFTFP_SUB) &&
+        Subtarget->usePackedHalf())
+    setOperationAction(ISD::FSUB,  MVT::v2f16, Legal);
+  else
+    setOperationAction(ISD::FSUB,  MVT::v2f16, Custom);
+
+  if (Subtarget->useSoftFopHalf(SoftFops::SOFTFP_MUL))
+    setOperationAction(ISD::FMUL, MVT::f16, Custom);
+  else
+    setOperationAction(ISD::FMUL, MVT::f16, Legal);
+
+  if (!Subtarget->useSoftFopHalf(SoftFops::SOFTFP_MUL) &&
+        Subtarget->usePackedHalf())
+    setOperationAction(ISD::FMUL,  MVT::v2f16, Legal);
+  else
+    setOperationAction(ISD::FMUL,  MVT::v2f16, Custom);
+
+  if (Subtarget->useSoftFopHalf(SoftFops::SOFTFP_DIV))
+    setOperationAction(ISD::FDIV, MVT::f16, Custom);
+  else
+    setOperationAction(ISD::FDIV, MVT::f16, Legal);
+
+  if (!Subtarget->useSoftFopHalf(SoftFops::SOFTFP_DIV) &&
+        Subtarget->usePackedHalf())
+    setOperationAction(ISD::FDIV,  MVT::v2f16, Legal);
+  else
+    setOperationAction(ISD::FDIV,  MVT::v2f16, Custom);
+
+  if (Subtarget->useSoftFopHalf(SoftFops::SOFTFP_SQRT))
+    setOperationAction(ISD::FSQRT, MVT::f16, Custom);
+  else
+    setOperationAction(ISD::FSQRT, MVT::f16, Legal);
+
+  if (!Subtarget->useSoftFopHalf(SoftFops::SOFTFP_SQRT) &&
+        Subtarget->usePackedHalf())
+    setOperationAction(ISD::FSQRT,  MVT::v2f16, Legal);
+  else
+    setOperationAction(ISD::FSQRT,  MVT::v2f16, Custom);
+
+  if (Subtarget->useSoftFopHalf(SoftFops::SOFTFP_CFUP) ||
+      Subtarget->useSoftFopSingle(SoftFops::SOFTFP_CFDN)) {
+    setOperationAction(ISD::FP_EXTEND, MVT::f32, Custom);
+    setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
+  }
+  if (Subtarget->useSoftFopSingle(SoftFops::SOFTFP_CFUP) ||
+      Subtarget->useSoftFopDouble(SoftFops::SOFTFP_CFDN)) {
+    setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
+    setOperationAction(ISD::FP_ROUND,  MVT::f32, Custom);
+  }
+  setOperationAction(ISD::FP_ROUND,  MVT::f64, Custom);
+
+  if (Subtarget->useSoftFopHalf(SoftFops::SOFTFP_CFUP) ||
+      Subtarget->useSoftFopDouble(SoftFops::SOFTFP_CFDN)) {
+    setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
+    setOperationAction(ISD::FP_ROUND,  MVT::f16, Custom);
+//  } else {
+//    setOperationAction(ISD::FP_ROUND,  MVT::f16, Custom);
+  }
+  if (Subtarget->useSoftFopHalf(SoftFops::SOFTFP_CFDN))
+    setOperationAction(ISD::FP_ROUND,  MVT::f16, Custom);
+
+
+  if (Subtarget->useSoftFopHalf(SoftFops::SOFTFP_ABS))
+    setOperationAction(ISD::FABS, MVT::f16, Custom);
+  else
+    setOperationAction(ISD::FABS, MVT::f16, Legal);
+  if (!Subtarget->useSoftFopHalf(SoftFops::SOFTFP_ABS) &&
+       Subtarget->usePackedHalf())
+    setOperationAction(ISD::FABS, MVT::v2f16, Legal);
+  else
+    setOperationAction(ISD::FABS, MVT::v2f16, Expand);
+
+  if (Subtarget->useSoftFopHalf(SoftFops::SOFTFP_NEG))
+    setOperationAction(ISD::FNEG, MVT::f16, Custom);
+  else
+    setOperationAction(ISD::FNEG, MVT::f16, Legal);
+  if (!Subtarget->useSoftFopHalf(SoftFops::SOFTFP_NEG) &&
+       Subtarget->usePackedHalf())
+    setOperationAction(ISD::FNEG, MVT::v2f16, Legal);
+  else
+    setOperationAction(ISD::FNEG, MVT::v2f16, Expand);
+
+  setOperationAction(ISD::FFLOOR, MVT::f16, Promote);
+  setOperationAction(ISD::FFLOOR, MVT::f32, Promote);
+  setOperationAction(ISD::FFLOOR, MVT::v2f16, Promote);
+  setOperationAction(ISD::FFLOOR, MVT::v2f32, Promote);
+
+  if (Subtarget->useSoftFopSingle(SoftFops::SOFTFP_ABS))
+    setOperationAction(ISD::FABS, MVT::f32, Custom);
+  else
+    setOperationAction(ISD::FABS, MVT::f32, Legal);
+
+  if (Subtarget->useSoftFopSingle(SoftFops::SOFTFP_NEG))
+    setOperationAction(ISD::FNEG, MVT::f32, Custom);
+  else
+    setOperationAction(ISD::FNEG, MVT::f32, Legal);
+
+  if (Subtarget->useSoftFopSingle(SoftFops::SOFTFP_ADD))
+    setOperationAction(ISD::FADD, MVT::f32, Custom);
+  else
+    setOperationAction(ISD::FADD, MVT::f32, Legal);
+
+  if (!Subtarget->useSoftFopSingle(SoftFops::SOFTFP_ADD) &&
+        Subtarget->usePackedSingle())
+    setOperationAction(ISD::FADD,  MVT::v2f32, Legal);
+  else
+    setOperationAction(ISD::FADD,  MVT::v2f32, Custom);
+
+  if (Subtarget->useSoftFopSingle(SoftFops::SOFTFP_SUB))
+    setOperationAction(ISD::FSUB, MVT::f32, Custom);
+  else
+    setOperationAction(ISD::FSUB, MVT::f32, Legal);
+
+  if (!Subtarget->useSoftFopSingle(SoftFops::SOFTFP_SUB) &&
+        Subtarget->usePackedSingle())
+    setOperationAction(ISD::FSUB,  MVT::v2f32, Legal);
+  else
+    setOperationAction(ISD::FSUB,  MVT::v2f32, Custom);
+
+  if (Subtarget->useSoftFopSingle(SoftFops::SOFTFP_MUL))
+    setOperationAction(ISD::FMUL, MVT::f32, Custom);
+  else
+    setOperationAction(ISD::FMUL, MVT::f32, Legal);
+
+  if (!Subtarget->useSoftFopSingle(SoftFops::SOFTFP_MUL) &&
+        Subtarget->usePackedSingle())
+    setOperationAction(ISD::FMUL,  MVT::v2f32, Legal);
+  else
+    setOperationAction(ISD::FMUL,  MVT::v2f32, Custom);
+
+  if (Subtarget->useSoftFopSingle(SoftFops::SOFTFP_DIV))
+    setOperationAction(ISD::FDIV, MVT::f32, Custom);
+  else
+    setOperationAction(ISD::FDIV, MVT::f32, Legal);
+
+  if (!Subtarget->useSoftFopSingle(SoftFops::SOFTFP_DIV) &&
+        Subtarget->usePackedSingle())
+    setOperationAction(ISD::FDIV,  MVT::v2f32, Legal);
+  else
+    setOperationAction(ISD::FDIV,  MVT::v2f32, Custom);
+
+  if (Subtarget->useSoftFopSingle(SoftFops::SOFTFP_SQRT))
+    setOperationAction(ISD::FSQRT, MVT::f32, Custom);
+  else
+    setOperationAction(ISD::FSQRT, MVT::f32, Legal);
+
+  if (!Subtarget->useSoftFopSingle(SoftFops::SOFTFP_SQRT) &&
+        Subtarget->usePackedSingle())
+    setOperationAction(ISD::FSQRT,  MVT::v2f32, Legal);
+  else
+    setOperationAction(ISD::FSQRT,  MVT::v2f32, Custom);
+
+//  if (Subtarget->useSoftFopSingle(SoftFops::SOFTFP_CMP))
+
+//  if (Subtarget->useSoftFopSingle(SoftFops::SOFTFP_MULEX))
+//    setOperationAction(ISD::FMUL, MVT::f32, Custom);
+
+//  if (Subtarget->useSoftFopSingle(SoftFops::SOFTFP_CI2F))
+//  if (Subtarget->useSoftFopSingle(SoftFops::SOFTFP_CF2I))
+
+  setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
+  if (Subtarget->useSoftFopSingle(SoftFops::SOFTFP_CFUP) ||
+      Subtarget->useSoftFopSingle(SoftFops::SOFTFP_CFDN)) {
+    setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
+  }
+
+  // --
+  if (Subtarget->useSoftFopDouble(SoftFops::SOFTFP_ADD))
+    setOperationAction(ISD::FADD, MVT::f64, Custom);
+  if (Subtarget->useSoftFopDouble(SoftFops::SOFTFP_SUB))
+    setOperationAction(ISD::FSUB, MVT::f64, Custom);
+  if (Subtarget->useSoftFopDouble(SoftFops::SOFTFP_MUL))
+    setOperationAction(ISD::FMUL, MVT::f64, Custom);
+  if (Subtarget->useSoftFopDouble(SoftFops::SOFTFP_DIV))
+    setOperationAction(ISD::FDIV, MVT::f64, Custom);
+  if (Subtarget->useSoftFopDouble(SoftFops::SOFTFP_SQRT))
+    setOperationAction(ISD::FSQRT, MVT::f64, Custom);
+
+//  if (Subtarget->useSoftFopDouble(SoftFops::SOFTFP_MULEX))
+//  if (Subtarget->useSoftFopDouble(SoftFops::SOFTFP_CMP))
+
+
+  setCmpLibcallCC(RTLIB::OEQ_F16, ISD::SETEQ);
+  setCmpLibcallCC(RTLIB::UNE_F16, ISD::SETNE);
+  setCmpLibcallCC(RTLIB::OGE_F16, ISD::SETGE);
+  setCmpLibcallCC(RTLIB::OLT_F16, ISD::SETLT);
+  setCmpLibcallCC(RTLIB::OLE_F16, ISD::SETLE);
+  setCmpLibcallCC(RTLIB::OGT_F16, ISD::SETGT);
+//  setCmpLibcallCC(RTLIB::UO_F16, ISD::SETO);
+//  setCmpLibcallCC(RTLIB::O_F16, ISD::SETUO);
+
+
+
   // Custom combine bitcast between f64 and v2i32
   if (!Subtarget->is64Bit())
     setTargetDAGCombine(ISD::BITCAST);
@@ -1826,6 +2131,33 @@ bool SparcTargetLowering::useSoftFloat() const {
   return Subtarget->useSoftFloat();
 }
 
+bool SparcTargetLowering::isHalfFopSoft(unsigned softfp) const {
+  return Subtarget->useSoftFopHalf(softfp);
+}
+bool SparcTargetLowering::isSingleFopSoft(unsigned softfp) const {
+  return Subtarget->useSoftFopSingle(softfp);
+}
+bool SparcTargetLowering::isDoubleFopSoft(unsigned softfp) const {
+  return Subtarget->useSoftFopDouble(softfp);
+}
+
+bool SparcTargetLowering::isAnySoftHalf() const {
+  return Subtarget->useSoftHalf();
+}
+bool SparcTargetLowering::isAnySingle() const {
+  return Subtarget->useSoftSingle();
+}
+bool SparcTargetLowering::isAnySoftDouble() const {
+  return Subtarget->useSoftDouble();
+}
+bool SparcTargetLowering::isPackedHalf() const {
+  return Subtarget->usePackedHalf();
+}
+bool SparcTargetLowering::isPackedSingle() const {
+  return Subtarget->usePackedSingle();
+}
+
+
 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
   switch ((SPISD::NodeType)Opcode) {
   case SPISD::FIRST_NUMBER:    break;
@@ -1850,6 +2182,20 @@ const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case SPISD::TLS_ADD:         return "SPISD::TLS_ADD";
   case SPISD::TLS_LD:          return "SPISD::TLS_LD";
   case SPISD::TLS_CALL:        return "SPISD::TLS_CALL";
+  case SPISD::PACKINSHI:       return "SPISD::PACKINSHI";
+  case SPISD::PACKINSLO:       return "SPISD::PACKINSLO";
+  case SPISD::PACKEXT:         return "SPISD::PACKEXT";
+  case SPISD::SWAR:            return "SPISD::SWAR";
+  case SPISD::SWARCC:          return "SPISD::SWARACC";
+  case SPISD::SWARCTRL:        return "SPISD::SWARCTRL";
+  case SPISD::SWAPPH:          return "SPISD::SWAPPH";
+  case SPISD::MOVVUU:          return "SPISD::MOVVUU";
+  case SPISD::MOVVLL:          return "SPISD::MOVVLL";
+  case SPISD::MOVVUL:          return "SPISD::MOVVUL";
+  case SPISD::MOVVLU:          return "SPISD::MOVVLU";
+  case SPISD::MOVVZL:          return "SPISD::MOVVZL";
+  case SPISD::MOVVZU:          return "SPISD::MOVVZU";
+  case SPISD::ANDCC:           return "SPISD::ANDCC";
   }
   return nullptr;
 }
@@ -2126,6 +2472,75 @@ SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op,
                      DAG.getRegister(SP::G7, PtrVT), Offset);
 }
 
+/* universal function based on LowerF128Op */
+SDValue SparcTargetLowering::LowerFloatOp(SDValue Op, SelectionDAG &DAG,
+                            const char *LibFuncName, unsigned numArgs) const {
+  ArgListTy Args;
+
+  MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
+  auto PtrVT = getPointerTy(DAG.getDataLayout());
+
+  SDValue Callee = DAG.getExternalSymbol(LibFuncName, PtrVT);
+  Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext());
+  Type *RetTyABI = RetTy;
+  SDValue Chain = DAG.getEntryNode();
+  SDValue RetPtr;
+
+  // Create a Stack Object to receive the return value of type f128.
+  ArgListEntry Entry;
+  int RetFI;
+  switch (RetTy->getTypeID()) {
+    case Type::HalfTyID:
+      RetFI = MFI.CreateStackObject(2, Align(4), false);
+      break;
+    case Type::FloatTyID:
+      RetFI = MFI.CreateStackObject(4, Align(4), false);
+      break;
+    case Type::DoubleTyID:
+      RetFI = MFI.CreateStackObject(8, Align(8), false);
+      break;
+    default:
+      llvm_unreachable("Sparc LowerFloatOp RetTp!");
+  }
+  RetPtr = DAG.getFrameIndex(RetFI, PtrVT);
+  Entry.Node = RetPtr;
+  Entry.Ty   = PointerType::getUnqual(RetTy);
+  Entry.IsReturned = false;
+  Args.push_back(Entry);
+  RetTyABI = Type::getVoidTy(*DAG.getContext());
+
+  assert(Op->getNumOperands() >= numArgs && "Not enough operands!");
+  for (unsigned i = 0, e = numArgs; i != e; ++i) {
+    Chain = LowerF128_LibCallArg(Chain, Args, Op.getOperand(i), SDLoc(Op), DAG);
+  }
+  TargetLowering::CallLoweringInfo CLI(DAG);
+  CLI.setDebugLoc(SDLoc(Op)).setChain(Chain)
+    .setCallee(CallingConv::C, RetTyABI, Callee, std::move(Args));
+
+  std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
+
+  // chain is in second result.
+  if (RetTyABI == RetTy)
+    return CallInfo.first;
+
+  Chain = CallInfo.second;
+
+  // Load RetPtr to get the return value.
+    switch (RetTy->getTypeID()) {
+      case Type::HalfTyID:
+      case Type::FloatTyID:
+        return DAG.getLoad(Op.getValueType(), SDLoc(Op), Chain, RetPtr,
+                     MachinePointerInfo(), /* Alignment = */ 4);
+        break;
+      case Type::DoubleTyID:
+        return DAG.getLoad(Op.getValueType(), SDLoc(Op), Chain, RetPtr,
+                     MachinePointerInfo(), /* Alignment = */ 8);
+        break;
+      default:
+        llvm_unreachable("Sparc LowerFloatOp RetTp!");
+    }
+}
+
 SDValue SparcTargetLowering::LowerF128_LibCallArg(SDValue Chain,
                                                   ArgListTy &Args, SDValue Arg,
                                                   const SDLoc &DL,
@@ -2210,23 +2625,82 @@ SDValue SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS,
                                               SelectionDAG &DAG) const {
 
   const char *LibCall = nullptr;
-  bool is64Bit = Subtarget->is64Bit();
-  switch(SPCC) {
-  default: llvm_unreachable("Unhandled conditional code!");
-  case SPCC::FCC_E  : LibCall = is64Bit? "_Qp_feq" : "_Q_feq"; break;
-  case SPCC::FCC_NE : LibCall = is64Bit? "_Qp_fne" : "_Q_fne"; break;
-  case SPCC::FCC_L  : LibCall = is64Bit? "_Qp_flt" : "_Q_flt"; break;
-  case SPCC::FCC_G  : LibCall = is64Bit? "_Qp_fgt" : "_Q_fgt"; break;
-  case SPCC::FCC_LE : LibCall = is64Bit? "_Qp_fle" : "_Q_fle"; break;
-  case SPCC::FCC_GE : LibCall = is64Bit? "_Qp_fge" : "_Q_fge"; break;
-  case SPCC::FCC_UL :
-  case SPCC::FCC_ULE:
-  case SPCC::FCC_UG :
-  case SPCC::FCC_UGE:
-  case SPCC::FCC_U  :
-  case SPCC::FCC_O  :
-  case SPCC::FCC_LG :
-  case SPCC::FCC_UE : LibCall = is64Bit? "_Qp_cmp" : "_Q_cmp"; break;
+  EVT lhsVT = LHS.getValueType();
+  if (lhsVT==MVT::f16) {
+    switch(SPCC) {
+    default: llvm_unreachable("Unhandled F16 conditional code!");
+    case SPCC::FCC_E  : LibCall = getLibcallName(RTLIB::OEQ_F16); break; // LibCall = "__eqhf2"; break;
+    case SPCC::FCC_NE : LibCall = getLibcallName(RTLIB::UNE_F16); break; // LibCall = "__nehf2"; break;
+    case SPCC::FCC_L  : LibCall = getLibcallName(RTLIB::OLT_F16); break; // LibCall = "__lthf2"; break;
+    case SPCC::FCC_G  : LibCall = getLibcallName(RTLIB::OGT_F16); break; // LibCall = "__gthf2"; break;
+    case SPCC::FCC_LE : LibCall = getLibcallName(RTLIB::OLE_F16); break; // LibCall = "__lehf2"; break;
+    case SPCC::FCC_GE : LibCall = getLibcallName(RTLIB::OGE_F16); break; // LibCall = "__gehf2"; break;
+    case SPCC::FCC_UL :
+    case SPCC::FCC_ULE:
+    case SPCC::FCC_UG :
+    case SPCC::FCC_UGE:
+    case SPCC::FCC_U  :
+    case SPCC::FCC_O  :
+    case SPCC::FCC_LG :
+    case SPCC::FCC_UE : LibCall = "_H_cmp"; break;
+    }
+  } else if (lhsVT==MVT::f32) {
+    switch(SPCC) {
+    default: llvm_unreachable("Unhandled F32 conditional code!");
+    case SPCC::FCC_E  : LibCall = getLibcallName(RTLIB::OEQ_F32); break;
+    case SPCC::FCC_NE : LibCall = getLibcallName(RTLIB::UNE_F32); break;
+    case SPCC::FCC_L  : LibCall = getLibcallName(RTLIB::OLT_F32); break;
+    case SPCC::FCC_G  : LibCall = getLibcallName(RTLIB::OGT_F32); break;
+    case SPCC::FCC_LE : LibCall = getLibcallName(RTLIB::OLE_F32); break;
+    case SPCC::FCC_GE : LibCall = getLibcallName(RTLIB::OGE_F32); break;
+    case SPCC::FCC_UL :
+    case SPCC::FCC_ULE:
+    case SPCC::FCC_UG :
+    case SPCC::FCC_UGE:
+    case SPCC::FCC_U  :
+    case SPCC::FCC_O  :
+    case SPCC::FCC_LG :
+    case SPCC::FCC_UE : LibCall = "_S_cmp"; break;
+    }
+  } else if (lhsVT==MVT::f64) {
+    switch(SPCC) {
+    default: llvm_unreachable("Unhandled F64 conditional code!");
+    case SPCC::FCC_E  : LibCall = getLibcallName(RTLIB::OEQ_F64); break;
+    case SPCC::FCC_NE : LibCall = getLibcallName(RTLIB::UNE_F64); break;
+    case SPCC::FCC_L  : LibCall = getLibcallName(RTLIB::OLT_F64); break;
+    case SPCC::FCC_G  : LibCall = getLibcallName(RTLIB::OGT_F64); break;
+    case SPCC::FCC_LE : LibCall = getLibcallName(RTLIB::OLE_F64); break;
+    case SPCC::FCC_GE : LibCall = getLibcallName(RTLIB::OGE_F64); break;
+    case SPCC::FCC_UL :
+    case SPCC::FCC_ULE:
+    case SPCC::FCC_UG :
+    case SPCC::FCC_UGE:
+    case SPCC::FCC_U  :
+    case SPCC::FCC_O  :
+    case SPCC::FCC_LG :
+    case SPCC::FCC_UE : LibCall = "_D_cmp"; break;
+    }
+  } else if (lhsVT==MVT::f128) {
+    bool is64Bit = Subtarget->is64Bit();
+    switch(SPCC) {
+    default: llvm_unreachable("Unhandled conditional code!");
+    case SPCC::FCC_E  : LibCall = is64Bit? "_Qp_feq" : "_Q_feq"; break;
+    case SPCC::FCC_NE : LibCall = is64Bit? "_Qp_fne" : "_Q_fne"; break;
+    case SPCC::FCC_L  : LibCall = is64Bit? "_Qp_flt" : "_Q_flt"; break;
+    case SPCC::FCC_G  : LibCall = is64Bit? "_Qp_fgt" : "_Q_fgt"; break;
+    case SPCC::FCC_LE : LibCall = is64Bit? "_Qp_fle" : "_Q_fle"; break;
+    case SPCC::FCC_GE : LibCall = is64Bit? "_Qp_fge" : "_Q_fge"; break;
+    case SPCC::FCC_UL :
+    case SPCC::FCC_ULE:
+    case SPCC::FCC_UG :
+    case SPCC::FCC_UGE:
+    case SPCC::FCC_U  :
+    case SPCC::FCC_O  :
+    case SPCC::FCC_LG :
+    case SPCC::FCC_UE : LibCall = is64Bit? "_Qp_cmp" : "_Q_cmp"; break;
+    }
+  } else {
+    llvm_unreachable("LowerFcompare for unsupported type");
   }
 
   auto PtrVT = getPointerTy(DAG.getDataLayout());
@@ -2252,11 +2726,29 @@ SDValue SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS,
     SPCC = SPCC::ICC_NE;
     return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
   }
+  case SPCC::FCC_E  : {
+    SDValue RHS = DAG.getConstant(0, DL, Result.getValueType());
+    SPCC = SPCC::ICC_E;
+    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
+  }
+  case SPCC::FCC_G  : {
+    SDValue RHS = DAG.getConstant(1, DL, Result.getValueType());
+    SPCC = SPCC::ICC_E;
+    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
+  }
+  case SPCC::FCC_LE  : { /* not equal to 1 (a<=b : <-1,0> ) */
+    SDValue RHS = DAG.getConstant(1, DL, Result.getValueType());
+    SPCC = SPCC::ICC_NE;
+    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
+  }
+  case SPCC::FCC_L  : {
+    SDValue RHS = DAG.getConstant(-1, DL, Result.getValueType());
+    SPCC = SPCC::ICC_E;
+    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
+  }
   case SPCC::FCC_UL : {
-    SDValue Mask   = DAG.getConstant(1, DL, Result.getValueType());
-    Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
     SDValue RHS    = DAG.getConstant(0, DL, Result.getValueType());
-    SPCC = SPCC::ICC_NE;
+    SPCC = SPCC::ICC_G;
     return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
   }
   case SPCC::FCC_ULE: {
@@ -2265,9 +2757,9 @@ SDValue SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS,
     return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
   }
   case SPCC::FCC_UG :  {
-    SDValue RHS = DAG.getConstant(1, DL, Result.getValueType());
-    SPCC = SPCC::ICC_G;
-    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
+    SDValue RHS = DAG.getConstant(2, DL, Result.getValueType());
+    SPCC = SPCC::ICC_NE;
+    return DAG.getNode(SPISD::ANDCC, DL, MVT::Glue, Result, RHS);
   }
   case SPCC::FCC_UGE: {
     SDValue RHS = DAG.getConstant(1, DL, Result.getValueType());
@@ -2305,11 +2797,32 @@ SDValue SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS,
 static SDValue
 LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG,
                    const SparcTargetLowering &TLI) {
+  // f16->f32
+  if (Op.getOperand(0).getValueType() == MVT::f16 &&
+      Op.getValueType()==MVT::f32) {
+    if (TLI.isHalfFopSoft(SoftFops::SOFTFP_CFUP) || TLI.isSingleFopSoft(SoftFops::SOFTFP_CFDN)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::FPEXT_F16_F32), 1);
+    }
+    return Op;
+  }
+  // f16->f64
+  if (Op.getOperand(0).getValueType() == MVT::f16 &&
+      Op.getValueType()==MVT::f64) {
+    return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::FPEXT_F16_F64), 1);
+  }
+  // f32->f64
+  if (Op.getOperand(0).getValueType() == MVT::f32 &&
+      Op.getValueType()==MVT::f64) {
+    if (TLI.isSingleFopSoft(SoftFops::SOFTFP_CFUP) || TLI.isDoubleFopSoft(SoftFops::SOFTFP_CFDN))
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::FPEXT_F32_F64), 1);
+    return Op;
+  }
 
+  // f64->f128
   if (Op.getOperand(0).getValueType() == MVT::f64)
     return TLI.LowerF128Op(Op, DAG,
                            TLI.getLibcallName(RTLIB::FPEXT_F64_F128), 1);
-
+  // f32->f128
   if (Op.getOperand(0).getValueType() == MVT::f32)
     return TLI.LowerF128Op(Op, DAG,
                            TLI.getLibcallName(RTLIB::FPEXT_F32_F128), 1);
@@ -2321,6 +2834,35 @@ LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG,
 static SDValue
 LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG,
                   const SparcTargetLowering &TLI) {
+  // round f64->f32 but soft-float for double
+  if (Op.getOperand(0).getValueType()==MVT::f64 &&
+      Op.getValueType()==MVT::f32) {
+    if (TLI.isSingleFopSoft(SoftFops::SOFTFP_CFUP) || TLI.isDoubleFopSoft(SoftFops::SOFTFP_CFDN))
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::FPROUND_F64_F32), 1);
+    return Op;
+  }
+  // round f32->f16 but soft-float for single
+  if (Op.getOperand(0).getValueType()==MVT::f32 &&
+      Op.getValueType()==MVT::f16) {
+    if (TLI.isHalfFopSoft(SoftFops::SOFTFP_CFUP) || TLI.isSingleFopSoft(SoftFops::SOFTFP_CFDN)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::FPROUND_F32_F16), 1);
+    }
+    return Op;
+  }
+  // round f64->f16 but soft-float for double
+  if (Op.getOperand(0).getValueType()==MVT::f64 &&
+      Op.getValueType()==MVT::f16) {
+    if (TLI.isHalfFopSoft(SoftFops::SOFTFP_CFUP) || TLI.isSingleFopSoft(SoftFops::SOFTFP_CFDN) ||
+        TLI.isSingleFopSoft(SoftFops::SOFTFP_CFUP) || TLI.isDoubleFopSoft(SoftFops::SOFTFP_CFDN)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::FPROUND_F64_F16), 1);
+    } else {
+      SDLoc dl(Op);
+      SDValue dtos = SDValue(DAG.getMachineNode(SP::FDTOS, dl, MVT::f32, Op.getOperand(0)),0);
+      SDValue stoh = SDValue(DAG.getMachineNode(SP::FSTOH, dl, MVT::f16, dtos),0);
+      return stoh;
+    }
+  }
+
   // FP_ROUND on f64 and f32 are legal.
   if (Op.getOperand(0).getValueType() != MVT::f128)
     return Op;
@@ -2336,6 +2878,268 @@ LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG,
   return SDValue();
 }
 
+// for v2f16 only
+static SDValue LowerBuildVector(SDValue Op, SelectionDAG &DAG,
+                                      const SparcTargetLowering &TLI,
+                                      const SparcSubtarget *Subtarget) {
+// build v2f16 from two f16 values, other combinations are not allowed now.
+  SDLoc dl(Op);
+  EVT VT = Op.getValueType();
+  if (VT == MVT::v2f16) { /* for v2f16 - vector packed half */
+    unsigned NumElts = VT.getVectorNumElements();
+    assert(NumElts==2);
+
+    EVT inVT1 = Op.getOperand(0).getValueType();
+    EVT inVT2 = Op.getOperand(1).getValueType();
+    assert(inVT1 == MVT::f16 && inVT2 == MVT::f16);
+  // build vector with MOVVUL
+  // if the first operand is FP constant 0.0H ... use MOVHZU
+    if (Op.getOperand(0).getOpcode()==ISD::ConstantFP) {
+      ConstantFPSDNode *Const = dyn_cast<ConstantFPSDNode>(Op.getOperand(0));
+      if (Const && Const->isZero()) {
+        return DAG.getNode(SPISD::MOVVZU, dl, MVT::v2f16, Op.getOperand(1));
+      }
+    }
+
+    SDValue El1;
+    if (inVT1!=MVT::f16) {
+      //fprintf(stderr," > Op0 bitcast from '%s'\n", inVT1.getEVTString().c_str());
+      El1 = DAG.getNode(ISD::BITCAST, dl, MVT::f16, Op.getOperand(0));
+    } else
+      El1 = Op.getOperand(0);
+    SDValue El2;
+    if (inVT2!=MVT::f16) {
+      //fprintf(stderr," > Op1 bitcast from '%s'\n", inVT2.getEVTString().c_str());
+      El2 = DAG.getNode(ISD::BITCAST, dl, MVT::f16, Op.getOperand(1));
+    } else
+      El2 = Op.getOperand(1);
+//    return DAG.getNode(SPISD::MOVVUU, dl, MVT::v2f16, El1, El2);
+    return DAG.getNode(SPISD::MOVVUU, dl, MVT::v2f16, Op.getOperand(0), Op.getOperand(1));
+
+  } else if (VT.isSubwordVector()) { /* build subword packed word */
+    unsigned num = Op.getNumOperands();
+    unsigned val = 0;
+    // only constant - compute in compile time
+    unsigned ebw = VT.getSimpleVT().getSubwordElmBitWidth();
+    uint32_t elmMask = ((1<<ebw)-1);
+
+    // step 1 - compute the value
+    for(unsigned n=0;n<num;++n) {
+      ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Op.getOperand(n));
+      if (!Const) return SDValue(); /* not all constants ... TODO: process */
+      assert(Const && "Element for subword vector is not a constant.");
+
+      uint64_t cv = Op.getConstantOperandVal(n);
+      val = val | ((cv & elmMask)<<(ebw*n));
+    }
+    // create and return the output value
+    SDValue out = DAG.getNode(ISD::BITCAST, dl, VT, DAG.getConstant(val, dl, MVT::i32));
+    return out;
+
+  } else {
+    return SDValue();
+  }
+}
+
+static SDValue LowerInsertIntoVector(SDValue Op, SelectionDAG &DAG,
+                                      const SparcTargetLowering &TLI,
+                                      const SparcSubtarget *Subtarget) {
+  SDLoc dl(Op);
+  EVT VT = Op.getValueType();
+
+  if (VT == MVT::v2f16) { /* for v2f16 - vector packed half */
+    EVT inVT1 = Op.getOperand(0).getValueType();
+    EVT inVT2 = Op.getOperand(1).getValueType();
+    assert(inVT1 == MVT::v2f16 && inVT2 == MVT::f16);
+    uint64_t idx = Op->getConstantOperandVal(2);
+
+    if (idx==0) {
+      if (Op.getOperand(1).getOpcode()==ISD::ConstantFP) {
+        ConstantFPSDNode *Const = dyn_cast<ConstantFPSDNode>(Op.getOperand(1));
+        if (Const && Const->isZero()) {
+          return DAG.getNode(SPISD::MOVVZL, dl, MVT::v2f16, Op.getOperand(0));
+        }
+      }
+
+      SDValue Step1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f16, Op.getOperand(0));
+      return DAG.getNode(SPISD::MOVVUL, dl, MVT::v2f16, Step1, Op.getOperand(1));
+    } else {
+      return DAG.getNode(SPISD::MOVVUU, dl, MVT::v2f16, Op.getOperand(0), Op.getOperand(1));
+    }
+
+  } else if (VT.isSubwordVector()) {  /* insert element to subword packed word */
+    unsigned NumElts = VT.getVectorNumElements();
+    EVT inVT1 = Op.getOperand(0).getValueType();
+    EVT inVT2 = Op.getOperand(1).getValueType();
+
+    assert(VT == inVT1); /* the output type is the same as the input type */
+    unsigned bw = inVT1.getSizeInBits();
+    unsigned ebw = inVT1.getSimpleVT().getSubwordElmBitWidth();
+
+    ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Op.getOperand(2));
+    if (Const) { /* index is constant */
+      uint64_t idx = Op->getConstantOperandVal(2);
+
+      unsigned shift = ebw*idx;
+      uint32_t valMask = ((1<<ebw)-1)<<shift;
+      uint32_t remMask = ~valMask;
+
+      // s0=bitcast(newelm) /* useful for vsXp32 */
+      SDValue Step0 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(1));
+      // s1=s0 << shift
+      SDValue Step1 = DAG.getNode(ISD::SHL, dl, MVT::i32, Step0, DAG.getConstant(shift, dl, MVT::i32));
+      // s2 = s1 & valmask
+      SDValue Step2 = DAG.getNode(ISD::AND, dl, MVT::i32, Step1, DAG.getConstant(valMask, dl, MVT::i32));
+      // s3 = bitcast(vec)
+      SDValue Step3 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(0));
+      // s4 = s3 & remmask
+      SDValue Step4 = DAG.getNode(ISD::AND, dl, MVT::i32, Step3, DAG.getConstant(remMask, dl, MVT::i32));
+      // out = s2 or s4
+      SDValue Step5 = DAG.getNode(ISD::OR, dl, MVT::i32, Step2, Step4);
+      // bitcast to subword type
+      return DAG.getNode(ISD::BITCAST, dl, VT, Step5);
+    } else {
+      // shift=Op(2)*ebw
+      SDValue shift = DAG.getNode(ISD::MUL, dl, MVT::i32, Op.getOperand(2), DAG.getConstant(ebw, dl, MVT::i32));
+      // valMask = ((1<<ebw)-1)<<shift
+      SDValue valmask = DAG.getNode(ISD::SHL, dl, MVT::i32, DAG.getConstant( ((1<<ebw)-1) , dl, MVT::i32), shift);
+      // remMask = ~valMask
+      SDValue remmask = DAG.getNode(ISD::XOR, dl, MVT::i32, valmask, DAG.getConstant( -1 , dl, MVT::i32));
+
+      // s0=bitcast(newelm) /* useful for vsXp32 */
+      SDValue Step0 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(1));
+      // s1=s0 << shift
+      SDValue Step1 = DAG.getNode(ISD::SHL, dl, MVT::i32, Step0, shift);
+      // s2 = s1 & valmask
+      SDValue Step2 = DAG.getNode(ISD::AND, dl, MVT::i32, Step1, valmask);
+      // s3 = bitcast(vec)
+      SDValue Step3 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(0));
+      // s4 = s3 & remmask
+      SDValue Step4 = DAG.getNode(ISD::AND, dl, MVT::i32, Step3, remmask);
+      // out = s2 or s4
+      SDValue Step5 = DAG.getNode(ISD::OR, dl, MVT::i32, Step2, Step4);
+      // bitcast to subword type
+      return DAG.getNode(ISD::BITCAST, dl, VT, Step5);
+
+    }
+
+  } else {
+    return SDValue();
+  }
+}
+
+static SDValue LowerExtractFromVector(SDValue Op, SelectionDAG &DAG,
+                                      const SparcTargetLowering &TLI,
+                                      const SparcSubtarget *Subtarget) {
+  SDLoc dl(Op);
+  EVT VT = Op.getValueType();
+  EVT inVT = Op.getOperand(0).getValueType();
+
+  if (VT == MVT::f16) { /* output type */
+    assert(inVT == MVT::v2f16);
+
+    uint64_t idx = Op->getConstantOperandVal(1);
+    if (idx==0) {
+      return DAG.getNode(SPISD::MOVVUU, dl, MVT::f16, Op.getOperand(0), Op.getOperand(0));
+    } else {
+      return DAG.getNode(SPISD::MOVVLL, dl, MVT::f16, Op.getOperand(0), Op.getOperand(0));
+    }
+
+  } else if (inVT.isSubwordVector()) {  /* extract element from subword packed word */
+
+    unsigned NumElts = inVT.getVectorNumElements();
+
+    unsigned bw = inVT.getSizeInBits();
+    unsigned ebw = inVT.getSimpleVT().getSubwordElmBitWidth();
+
+    assert(VT.getSizeInBits() >= ebw); /* the output type has at least the same size as an element of the input type */
+
+    ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Op.getOperand(1));
+    if (Const) { /* index is constant */
+      uint64_t idx = Op.getConstantOperandVal(1);
+
+      unsigned shift = ebw*idx;
+      uint32_t valMask = ((1<<ebw)-1);
+
+      // s0=bitcast(vect)
+      SDValue Step0 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(0));
+      // s1=s0 >> shift
+      SDValue Step1 = DAG.getNode(ISD::SRL, dl, MVT::i32, Step0, DAG.getConstant(shift, dl, MVT::i32));
+      // s2 = s1 & valmask
+      SDValue Step2 = DAG.getNode(ISD::AND, dl, MVT::i32, Step1, DAG.getConstant(valMask, dl, MVT::i32));
+      // return bitcast(s2)
+      return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Step2); // VT
+    } else {
+
+      // shift=Op(1)*ebw
+      SDValue shift = DAG.getNode(ISD::MUL, dl, MVT::i32, Op.getOperand(1), DAG.getConstant(ebw, dl, MVT::i32));
+      // valMask = ((1<<ebw)-1)
+      SDValue valmask = DAG.getConstant( ((1<<ebw)-1) , dl, MVT::i32);
+      // s0=bitcast(vect)
+      SDValue Step0 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(0));
+      // s1=s0 >> shift
+      SDValue Step1 = DAG.getNode(ISD::SRL, dl, MVT::i32, Step0, shift);
+      // s2 = s1 & valmask
+      SDValue Step2 = DAG.getNode(ISD::AND, dl, MVT::i32, Step1, valmask);
+      // return bitcast(vec)
+      return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Step2); // VT
+    }
+  } else {
+    return SDValue();
+  }
+}
+
+static SDValue LowerVectorShuffle(SDValue Op, SelectionDAG &DAG,
+                                  const SparcTargetLowering &TLI,
+                                  const SparcSubtarget *Subtarget) {
+  SDLoc dl(Op);
+
+  /* now only for v2f16 type with one or two operands */
+  EVT VT = Op.getValueType();
+  assert(VT==MVT::v2f16);
+  assert(Op.getNumOperands()==1 || Op.getNumOperands()==2);
+
+  ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
+
+  ArrayRef<int> AM = SVN->getMask();
+  unsigned VecLen = AM.size();
+  if (VecLen!=2) {
+    fprintf(stderr,">RB< VectorShuffle for %u elements is not supported\n", VecLen);
+    return SDValue();
+  }
+  //for (unsigned i=0;i<VecLen;++i) {
+//fprintf(stderr,"  #%u = %d\n", i, (int)AM[i]);
+  //}
+
+  bool oneop = true;
+  if (AM[0]>1 || AM[1]>1) oneop = false;
+
+  EVT inVT1 = Op.getOperand(0).getValueType();
+
+  if (oneop) {
+    if (AM[0]==1 && AM[1]==0) { /* FSWAP */
+      return DAG.getNode(SPISD::SWAPPH, dl, MVT::v2f16, Op.getOperand(0));
+    } else {
+      return SDValue();
+    }
+  } else {
+    EVT inVT2 = Op.getOperand(1).getValueType();
+
+    if (AM[0]==0 && AM[1]==2) { /* MOVVUU */
+      return DAG.getNode(SPISD::MOVVUU, dl, MVT::v2f16, Op.getOperand(0), Op.getOperand(1));
+    } else if (AM[0]==1 && AM[1]==3) { /* MOVVLL */
+      return DAG.getNode(SPISD::MOVVLL, dl, MVT::v2f16, Op.getOperand(0), Op.getOperand(1));
+    } else if (AM[0]==0 && AM[1]==3) { /* MOVVUL */
+      return DAG.getNode(SPISD::MOVVUL, dl, MVT::v2f16, Op.getOperand(0), Op.getOperand(1));
+    } else if (AM[0]==1 && AM[1]==2) { /* MOVVLU */
+      return DAG.getNode(SPISD::MOVVLU, dl, MVT::v2f16, Op.getOperand(0), Op.getOperand(1));
+    } else {
+      return SDValue();
+    }
+  }
+}
+
+
 static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG,
                                const SparcTargetLowering &TLI,
                                bool hasHardQuad) {
@@ -2356,11 +3160,31 @@ static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG,
   if (!TLI.isTypeLegal(VT))
     return SDValue();
 
+  EVT inType = Op.getOperand(0).getValueType();
+
   // Otherwise, Convert the fp value to integer in an FP register.
-  if (VT == MVT::i32)
-    Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
-  else
+  if (VT == MVT::i32) {
+    if (inType==MVT::f16 && TLI.isHalfFopSoft(SoftFops::SOFTFP_CF2I)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::FPTOSINT_F16_I32), 1);
+    } else if (inType==MVT::f32 && TLI.isSingleFopSoft(SoftFops::SOFTFP_CF2I)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::FPTOSINT_F32_I32), 1);
+    } else if (inType==MVT::f64 && TLI.isDoubleFopSoft(SoftFops::SOFTFP_CF2I)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::FPTOSINT_F64_I32), 1);
+    }
+    if (inType==MVT::f32)
+      Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
+    else if (inType==MVT::f16) {
+      Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
+    } else if (inType==MVT::f64)
+      Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
+  } else {
+    if (inType==MVT::f32 && TLI.isSingleFopSoft(SoftFops::SOFTFP_CF2I)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::FPTOSINT_F32_I64), 1);
+    } else if (inType==MVT::f64 && TLI.isDoubleFopSoft(SoftFops::SOFTFP_CF2I)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::FPTOSINT_F64_I64), 1);
+    }
     Op = DAG.getNode(SPISD::FTOX, dl, MVT::f64, Op.getOperand(0));
+  }
 
   return DAG.getNode(ISD::BITCAST, dl, VT, Op);
 }
@@ -2370,7 +3194,7 @@ static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG,
                                bool hasHardQuad) {
   SDLoc dl(Op);
   EVT OpVT = Op.getOperand(0).getValueType();
-  assert(OpVT == MVT::i32 || (OpVT == MVT::i64));
+  assert(OpVT== MVT::i16 || OpVT == MVT::i32 || (OpVT == MVT::i64));
 
   EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64;
 
@@ -2387,6 +3211,32 @@ static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG,
   if (!TLI.isTypeLegal(OpVT))
     return SDValue();
 
+  EVT outType = Op.getValueType();
+  if (OpVT == MVT::i32) {
+    if (outType==MVT::f16 && TLI.isHalfFopSoft(SoftFops::SOFTFP_CI2F)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::SINTTOFP_I32_F16), 1);
+    } else if (outType==MVT::f32 && TLI.isSingleFopSoft(SoftFops::SOFTFP_CI2F)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::SINTTOFP_I32_F32), 1);
+    } else if (outType==MVT::f64 && TLI.isDoubleFopSoft(SoftFops::SOFTFP_CI2F)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::SINTTOFP_I32_F64), 1);
+    }
+  } else {
+    if (outType==MVT::f32 && TLI.isSingleFopSoft(SoftFops::SOFTFP_CI2F)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::SINTTOFP_I64_F32), 1);
+    } else if (outType==MVT::f64 && TLI.isDoubleFopSoft(SoftFops::SOFTFP_CI2F)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::SINTTOFP_I64_F64), 1);
+    }
+  }
+
+  if (outType==MVT::f16) {
+    if (TLI.isHalfFopSoft(SoftFops::SOFTFP_CI2F))
+      return TLI.LowerF128Op(Op, DAG, "__floatsihf", 1);
+    else {
+      SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
+      return DAG.getNode(SPISD::ITOF, dl, outType, Tmp);
+    }
+  }
+
   // Otherwise, Convert the int value to FP in an FP register.
   SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, floatVT, Op.getOperand(0));
   unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF;
@@ -2407,6 +3257,21 @@ static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG,
 
   assert(VT == MVT::i32 || VT == MVT::i64);
 
+  EVT inType = Op.getOperand(0).getValueType();
+  if (VT == MVT::i32) {
+    if (inType==MVT::f32 && TLI.isSingleFopSoft(SoftFops::SOFTFP_CF2I)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::FPTOUINT_F32_I32), 1);
+    } else if (inType==MVT::f64 && TLI.isDoubleFopSoft(SoftFops::SOFTFP_CF2I)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::FPTOUINT_F64_I32), 1);
+    }
+  } else {
+    if (inType==MVT::f32 && TLI.isSingleFopSoft(SoftFops::SOFTFP_CF2I)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::FPTOUINT_F32_I64), 1);
+    } else if (inType==MVT::f64 && TLI.isDoubleFopSoft(SoftFops::SOFTFP_CF2I)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::FPTOUINT_F64_I64), 1);
+    }
+  }
+
   return TLI.LowerF128Op(Op, DAG,
                          TLI.getLibcallName(VT == MVT::i32
                                             ? RTLIB::FPTOUINT_F128_I32
@@ -2426,6 +3291,21 @@ static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG,
   if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(OpVT)))
     return SDValue();
 
+  EVT outType = Op.getValueType();
+  if (OpVT == MVT::i32) {
+    if (outType==MVT::f32 && TLI.isSingleFopSoft(SoftFops::SOFTFP_CI2F)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::UINTTOFP_I32_F32), 1);
+    } else if (outType==MVT::f64 && TLI.isDoubleFopSoft(SoftFops::SOFTFP_CI2F)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::UINTTOFP_I32_F64), 1);
+    }
+  } else {
+    if (outType==MVT::f32 && TLI.isSingleFopSoft(SoftFops::SOFTFP_CI2F)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::UINTTOFP_I64_F32), 1);
+    } else if (outType==MVT::f64 && TLI.isDoubleFopSoft(SoftFops::SOFTFP_CI2F)) {
+      return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::UINTTOFP_I64_F64), 1);
+    }
+  }
+
   return TLI.LowerF128Op(Op, DAG,
                          TLI.getLibcallName(OpVT == MVT::i32
                                             ? RTLIB::UINTTOFP_I32_F128
@@ -2455,11 +3335,26 @@ static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
     if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
     // 32-bit compares use the icc flags, 64-bit uses the xcc flags.
     Opc = LHS.getValueType() == MVT::i32 ? SPISD::BRICC : SPISD::BRXCC;
+
   } else {
     if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
       if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
       CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
       Opc = SPISD::BRICC;
+
+    } else if (TLI.isHalfFopSoft(SoftFops::SOFTFP_CMP) && LHS.getValueType() == MVT::f16) {
+      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
+      CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
+      Opc = SPISD::BRICC;
+    } else if (TLI.isDoubleFopSoft(SoftFops::SOFTFP_CMP) && LHS.getValueType() == MVT::f64) {
+      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
+      CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
+      Opc = SPISD::BRICC;
+    } else if (TLI.isSingleFopSoft(SoftFops::SOFTFP_CMP) && LHS.getValueType() == MVT::f32) {
+      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
+      CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
+      Opc = SPISD::BRICC;
+
     } else {
       CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
       if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
@@ -2491,11 +3386,26 @@ static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
     Opc = LHS.getValueType() == MVT::i32 ?
           SPISD::SELECT_ICC : SPISD::SELECT_XCC;
     if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
+
   } else {
     if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
       if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
       CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
       Opc = SPISD::SELECT_ICC;
+
+    } else if (TLI.isHalfFopSoft(SoftFops::SOFTFP_CMP) && LHS.getValueType() == MVT::f16) {
+      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
+      CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
+      Opc = SPISD::SELECT_ICC;
+    } else if (TLI.isDoubleFopSoft(SoftFops::SOFTFP_CMP) && LHS.getValueType() == MVT::f64) {
+      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
+      CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
+      Opc = SPISD::SELECT_ICC;
+    } else if (TLI.isSingleFopSoft(SoftFops::SOFTFP_CMP) && LHS.getValueType() == MVT::f32) {
+      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
+      CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
+      Opc = SPISD::SELECT_ICC;
+
     } else {
       CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
       Opc = SPISD::SELECT_FCC;
@@ -2534,6 +3444,7 @@ static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
   EVT PtrVT = VAListPtr.getValueType();
   const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
   SDLoc DL(Node);
+
   SDValue VAList =
       DAG.getLoad(PtrVT, DL, InChain, VAListPtr, MachinePointerInfo(SV));
   // Increment the pointer, VAList, to the next vaarg.
@@ -2774,7 +3685,8 @@ static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
   return DAG.getMergeValues(Ops, dl);
 }
 
-static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG)
+static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG,
+                          const SparcSubtarget *Subtarget)
 {
   LoadSDNode *LdNode = cast<LoadSDNode>(Op.getNode());
 
@@ -2782,6 +3694,50 @@ static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG)
   if (MemVT == MVT::f128)
     return LowerF128Load(Op, DAG);
 
+  if (MemVT == MVT::v2f32) {
+    SDLoc dl(Op);
+    unsigned alignment = LdNode->getAlignment();
+    if (alignment==4) {
+
+      SDValue i0_32 =
+        DAG.getLoad(MVT::f32, dl, LdNode->getChain(), LdNode->getBasePtr(),
+                    LdNode->getPointerInfo(), alignment);
+      EVT addrVT = LdNode->getBasePtr().getValueType();
+      SDValue i1_Ptr = DAG.getNode(ISD::ADD, dl, addrVT,
+                                    LdNode->getBasePtr(),
+                                    DAG.getConstant(4, dl, addrVT));
+      SDValue i1_32 = DAG.getLoad(MVT::f32, dl, LdNode->getChain(), i1_Ptr,
+                                  LdNode->getPointerInfo(), alignment);
+      SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even, dl, MVT::i32);
+      SDValue SubRegOdd  = DAG.getTargetConstant(SP::sub_odd, dl, MVT::i32);
+      SDNode *InFPvec = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
+                                       dl, MVT::f64);
+      InFPvec = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
+                               MVT::v2f32,
+                               SDValue(InFPvec, 0),
+                               i0_32,
+                               SubRegEven);
+      InFPvec = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
+                               MVT::v2f32,
+                               SDValue(InFPvec, 0),
+                               i1_32,
+                               SubRegOdd);
+      SDValue OutChains[2] = {  SDValue(i0_32.getNode(), 1),
+                                SDValue(i1_32.getNode(), 1) };
+      SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
+      SDValue Ops[2] = {SDValue(InFPvec,0), OutChain};
+      return DAG.getMergeValues(Ops, dl);
+
+    } else  if (alignment<4) {
+      if (Subtarget->isAllowedUnalignedFP()) {
+        errs() << "Warning: The packed FP variable can be unaligned.\n";
+        //LdNode->getDebugLoc().dump();
+      } else {
+        llvm_unreachable("Packed FP variable must be correctly aligned.");
+      }
+    }
+  }
+
   return Op;
 }
 
@@ -2842,17 +3798,66 @@ static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG)
     return Chain;
   }
 
+  if (MemVT == MVT::f16) {
+    SDValue Val = DAG.getNode(ISD::BITCAST, dl, MVT::i16, St->getValue());
+    SDValue Chain = DAG.getStore(
+        St->getChain(), dl, Val, St->getBasePtr(), St->getPointerInfo(),
+        St->getAlignment(), St->getMemOperand()->getFlags(), St->getAAInfo());
+    return Chain;
+  }
+  if (MemVT == MVT::v2f16) {
+    return SDValue();
+  }
+  if (MemVT == MVT::v2f32) {
+    return SDValue();
+  }
+
+
   return SDValue();
 }
 
-static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
+static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9,
+                                const SparcTargetLowering &TLI) {
   assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS)
          && "invalid opcode");
 
-  SDLoc dl(Op);
+  SDLoc Loc(Op);
+
+  if (Op.getValueType() == MVT::f16) {
+    if (Op.getOpcode() == ISD::FNEG) {
+      if (TLI.isHalfFopSoft(SoftFops::SOFTFP_NEG))
+        return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::NEG_F16), 1);
+    } else { // FABS
+      if (TLI.isHalfFopSoft(SoftFops::SOFTFP_ABS))
+        return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::ABS_F16), 1);
+    }
+  }
+  if (Op.getValueType() == MVT::f32) {
+    if (Op.getOpcode() == ISD::FNEG) {
+      if (TLI.isSingleFopSoft(SoftFops::SOFTFP_NEG))
+        return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::NEG_F32), 1);
+    } else { // FABS
+      if (TLI.isSingleFopSoft(SoftFops::SOFTFP_ABS))
+        return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::ABS_F32), 1);
+    }
+  }
+
+  if (Op.getValueType() == MVT::f64) {
+    if (Op.getOpcode() == ISD::FNEG) { // FNEG - only fnegs, not fnegd -
+      if (TLI.isSingleFopSoft(SoftFops::SOFTFP_NEG)) { // HW fnegd is replaced with HW fnegs, so f32 version has to be tested
+        return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::NEG_F64), 1);
+      } else {
+        return LowerF64Op(Op.getOperand(0), Loc, DAG, Op.getOpcode());
+      }
+    } else { // FABS
+      if (TLI.isSingleFopSoft(SoftFops::SOFTFP_ABS)) { // HW fabsd is replaced with HW fabss
+        return TLI.LowerF128Op(Op, DAG, TLI.getLibcallName(RTLIB::ABS_F64), 1);
+      } else {
+        return LowerF64Op(Op.getOperand(0), Loc, DAG, Op.getOpcode());
+      }
+    }
+  }
 
-  if (Op.getValueType() == MVT::f64)
-    return LowerF64Op(Op.getOperand(0), dl, DAG, Op.getOpcode());
   if (Op.getValueType() != MVT::f128)
     return Op;
 
@@ -2862,28 +3867,28 @@ static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
   // subreg)
 
   SDValue SrcReg128 = Op.getOperand(0);
-  SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64,
+  SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, Loc, MVT::f64,
                                             SrcReg128);
-  SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64,
+  SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, Loc, MVT::f64,
                                             SrcReg128);
 
   if (DAG.getDataLayout().isLittleEndian()) {
     if (isV9)
-      Lo64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Lo64);
+      Lo64 = DAG.getNode(Op.getOpcode(), Loc, MVT::f64, Lo64);
     else
-      Lo64 = LowerF64Op(Lo64, dl, DAG, Op.getOpcode());
+      Lo64 = LowerF64Op(Lo64, Loc, DAG, Op.getOpcode());
   } else {
     if (isV9)
-      Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64);
+      Hi64 = DAG.getNode(Op.getOpcode(), Loc, MVT::f64, Hi64);
     else
-      Hi64 = LowerF64Op(Hi64, dl, DAG, Op.getOpcode());
+      Hi64 = LowerF64Op(Hi64, Loc, DAG, Op.getOpcode());
   }
 
   SDValue DstReg128 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
-                                                 dl, MVT::f128), 0);
-  DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128,
+                                                 Loc, MVT::f128), 0);
+  DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, Loc, MVT::f128,
                                         DstReg128, Hi64);
-  DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128,
+  DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, Loc, MVT::f128,
                                         DstReg128, Lo64);
   return DstReg128;
 }
@@ -3010,6 +4015,38 @@ SDValue SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
   }
 }
 
+/* -------------------------------------------------------------------------- */
+/* swar ops */
+SDValue SparcTargetLowering::LowerSwarOperation(SDValue Op,
+                  SelectionDAG &DAG, const SparcTargetLowering &TLI) const {
+  SDLoc DL(Op);
+  unsigned opcode = Op.getOpcode();
+  SDValue LHS = Op.getOperand(0);
+  SDValue RHS = Op.getOperand(1);
+//  SDValue OutChains[2];
+
+  assert((opcode == ISD::ADD || opcode == ISD::SUB || opcode == ISD::MUL)
+         && "invalid SWAR A/V opcode");
+
+  // add WRASR for setting SWAR module
+  unsigned swarop = 0;
+  switch (opcode) {
+    default: return SDValue();
+
+    case ISD::ADD: swarop = 0x00; break;
+    case ISD::SUB: swarop = 0x08; break;
+    case ISD::MUL: swarop = 0x0C; break;
+  }
+
+  if (LHS.getValueType()!=RHS.getValueType()) {
+    assert(false && "SWAR-AV LHS type != RHS type");
+  }
+
+  return DAG.getNode(SPISD::SWAR, DL, LHS.getValueType(), LHS, RHS);
+}
+/* -------------------------------------------------------------------------- */
+
+
 SDValue SparcTargetLowering::
 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
 
@@ -3019,6 +4056,12 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   switch (Op.getOpcode()) {
   default: llvm_unreachable("Should not custom lower this!");
 
+  case ISD::BUILD_VECTOR:       return LowerBuildVector(Op, DAG, *this, Subtarget);
+  case ISD::INSERT_VECTOR_ELT:  return LowerInsertIntoVector(Op, DAG, *this, Subtarget);
+  case ISD::EXTRACT_VECTOR_ELT: return LowerExtractFromVector(Op, DAG, *this, Subtarget);
+  case ISD::VECTOR_SHUFFLE:     return LowerVectorShuffle(Op, DAG, *this, Subtarget);
+//  case ISD::BITCAST:            return LowerBitcast(Op, DAG, *this, Subtarget);
+
   case ISD::RETURNADDR:         return LowerRETURNADDR(Op, DAG, *this,
                                                        Subtarget);
   case ISD::FRAMEADDR:          return LowerFRAMEADDR(Op, DAG,
@@ -3044,20 +4087,84 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG,
                                                                Subtarget);
 
-  case ISD::LOAD:               return LowerLOAD(Op, DAG);
+  case ISD::LOAD:               return LowerLOAD(Op, DAG, Subtarget);
   case ISD::STORE:              return LowerSTORE(Op, DAG);
-  case ISD::FADD:               return LowerF128Op(Op, DAG,
-                                       getLibcallName(RTLIB::ADD_F128), 2);
-  case ISD::FSUB:               return LowerF128Op(Op, DAG,
-                                       getLibcallName(RTLIB::SUB_F128), 2);
-  case ISD::FMUL:               return LowerF128Op(Op, DAG,
-                                       getLibcallName(RTLIB::MUL_F128), 2);
-  case ISD::FDIV:               return LowerF128Op(Op, DAG,
-                                       getLibcallName(RTLIB::DIV_F128), 2);
-  case ISD::FSQRT:              return LowerF128Op(Op, DAG,
-                                       getLibcallName(RTLIB::SQRT_F128),1);
+
+
+  case ISD::FADD:
+    if (Op.getValueType()==MVT::f16)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::ADD_F16), 2);
+    else if (Op.getValueType()==MVT::f32)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::ADD_F32), 2);
+    else if (Op.getValueType()==MVT::f64)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::ADD_F64), 2);
+    else if (Op.getValueType()==MVT::v2f16)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::ADD_V2F16), 2);
+    else if (Op.getValueType()==MVT::v2f32)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::ADD_V2F32), 2);
+    else
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::ADD_F128), 2);
+
+  case ISD::FSUB:
+    if (Op.getValueType()==MVT::f16)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::SUB_F16), 2);
+    else if (Op.getValueType()==MVT::f32)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::SUB_F32), 2);
+    else if (Op.getValueType()==MVT::f64)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::SUB_F64), 2);
+    else if (Op.getValueType()==MVT::v2f16)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::SUB_V2F16), 2);
+    else if (Op.getValueType()==MVT::v2f32)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::SUB_V2F32), 2);
+    else
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::SUB_F128), 2);
+
+  case ISD::FMUL:
+    if (Op.getValueType()==MVT::f16)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::MUL_F16), 2);
+    else if (Op.getValueType()==MVT::f32)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::MUL_F32), 2);
+    else if (Op.getValueType()==MVT::f64)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::MUL_F64), 2);
+    else if (Op.getValueType()==MVT::v2f16)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::MUL_V2F16), 2);
+    else if (Op.getValueType()==MVT::v2f32)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::MUL_V2F32), 2);
+    else
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::MUL_F128), 2);
+
+  case ISD::FDIV:
+    if (Op.getValueType()==MVT::f16)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::DIV_F16), 2);
+    else if (Op.getValueType()==MVT::f32)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::DIV_F32), 2);
+    else if (Op.getValueType()==MVT::f64)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::DIV_F64), 2);
+    else if (Op.getValueType()==MVT::v2f16)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::DIV_V2F16), 2);
+    else if (Op.getValueType()==MVT::v2f32)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::DIV_V2F32), 2);
+    else
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::DIV_F128), 2);
+
+  case ISD::FSQRT:
+    if (Op.getValueType()==MVT::f16)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::SQRT_F16), 1);
+    else if (Op.getValueType()==MVT::f32)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::SQRT_F32), 1);
+    else if (Op.getValueType()==MVT::f64)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::SQRT_F64), 1);
+    else if (Op.getValueType()==MVT::v2f16)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::SQRT_V2F16), 1);
+    else if (Op.getValueType()==MVT::v2f32)
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::SQRT_V2F32), 1);
+    else
+      return LowerF128Op(Op, DAG, getLibcallName(RTLIB::SQRT_F128),1);
+
   case ISD::FABS:
-  case ISD::FNEG:               return LowerFNEGorFABS(Op, DAG, isV9);
+  case ISD::FNEG:
+    return LowerFNEGorFABS(Op, DAG, isV9, *this);
+
   case ISD::FP_EXTEND:          return LowerF128_FPEXTEND(Op, DAG, *this);
   case ISD::FP_ROUND:           return LowerF128_FPROUND(Op, DAG, *this);
   case ISD::ADDC:
@@ -3069,10 +4176,16 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   case ISD::ATOMIC_LOAD:
   case ISD::ATOMIC_STORE:       return LowerATOMIC_LOAD_STORE(Op, DAG);
   case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
+
+// swar custom operations
+  case ISD::ADD:
+  case ISD::SUB:
+  case ISD::MUL:
+    return LowerSwarOperation(Op, DAG,*this);
   }
 }
 
-SDValue SparcTargetLowering::bitcastConstantFPToInt(ConstantFPSDNode *C,
+SDValue SparcTargetLowering::bitcastConstantFPToInt64(ConstantFPSDNode *C,
                                                     const SDLoc &DL,
                                                     SelectionDAG &DAG) const {
   APInt V = C->getValueAPF().bitcastToAPInt();
@@ -3083,6 +4196,14 @@ SDValue SparcTargetLowering::bitcastConstantFPToInt(ConstantFPSDNode *C,
   return DAG.getBuildVector(MVT::v2i32, DL, {Hi, Lo});
 }
 
+SDValue SparcTargetLowering::bitcastConstantFPToInt16(ConstantFPSDNode *C,
+                                                    const SDLoc &DL,
+                                                    SelectionDAG &DAG) const {
+  APInt V = C->getValueAPF().bitcastToAPInt();
+  SDValue IVal = DAG.getConstant(V.zext(16), DL, MVT::i16);
+  return IVal;
+}
+
 SDValue SparcTargetLowering::PerformBITCASTCombine(SDNode *N,
                                                    DAGCombinerInfo &DCI) const {
   SDLoc dl(N);
@@ -3090,7 +4211,11 @@ SDValue SparcTargetLowering::PerformBITCASTCombine(SDNode *N,
 
   if (isa<ConstantFPSDNode>(Src) && N->getSimpleValueType(0) == MVT::v2i32 &&
       Src.getSimpleValueType() == MVT::f64)
-    return bitcastConstantFPToInt(cast<ConstantFPSDNode>(Src), dl, DCI.DAG);
+    return bitcastConstantFPToInt64(cast<ConstantFPSDNode>(Src), dl, DCI.DAG);
+
+  if (isa<ConstantFPSDNode>(Src) && N->getSimpleValueType(0) == MVT::i16 &&
+      Src.getSimpleValueType() == MVT::f16)
+    return bitcastConstantFPToInt16(cast<ConstantFPSDNode>(Src), dl, DCI.DAG);
 
   return SDValue();
 }
@@ -3115,11 +4240,17 @@ SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
   case SP::SELECT_CC_FP_ICC:
   case SP::SELECT_CC_DFP_ICC:
   case SP::SELECT_CC_QFP_ICC:
+  case SP::SELECT_CC_HFP_ICC:
+  case SP::SELECT_CC_PFPH_ICC:
+  case SP::SELECT_CC_PFPS_ICC:
     return expandSelectCC(MI, BB, SP::BCOND);
   case SP::SELECT_CC_Int_FCC:
   case SP::SELECT_CC_FP_FCC:
   case SP::SELECT_CC_DFP_FCC:
   case SP::SELECT_CC_QFP_FCC:
+  case SP::SELECT_CC_HFP_FCC:
+  case SP::SELECT_CC_PFPH_FCC:
+  case SP::SELECT_CC_PFPS_FCC:
     return expandSelectCC(MI, BB, SP::FBCOND);
   }
 }
@@ -3282,6 +4413,12 @@ SparcTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
         return std::make_pair(0U, &SP::LowDFPRegsRegClass);
       else if (VT == MVT::f128)
         return std::make_pair(0U, &SP::LowQFPRegsRegClass);
+      else if (VT == MVT::f16)
+        return std::make_pair(0U, &SP::HFPRegsRegClass);
+      else if (VT == MVT::v2f16)
+        return std::make_pair(0U, &SP::PFPHRegsRegClass);
+      else if (VT == MVT::v2f32)
+        return std::make_pair(0U, &SP::PFPSRegsRegClass);
       // This will generate an error message
       return std::make_pair(0U, nullptr);
     case 'e':
@@ -3291,6 +4428,12 @@ SparcTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
         return std::make_pair(0U, &SP::DFPRegsRegClass);
       else if (VT == MVT::f128)
         return std::make_pair(0U, &SP::QFPRegsRegClass);
+      else if (VT == MVT::f16)
+        return std::make_pair(0U, &SP::HFPRegsRegClass);
+      else if (VT == MVT::v2f16)
+        return std::make_pair(0U, &SP::PFPHRegsRegClass);
+      else if (VT == MVT::v2f32)
+        return std::make_pair(0U, &SP::PFPSRegsRegClass);
       // This will generate an error message
       return std::make_pair(0U, nullptr);
     }
@@ -3319,9 +4462,9 @@ SparcTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
         !name.substr(1).getAsInteger(10, intVal) && intVal <= 63) {
       std::string newConstraint;
 
-      if (VT == MVT::f32 || VT == MVT::Other) {
+      if (VT == MVT::f32 || VT == MVT::f16 || VT == MVT::v2f16 || VT == MVT::Other) {
         newConstraint = "{f" + utostr(intVal) + "}";
-      } else if (VT == MVT::f64 && (intVal % 2 == 0)) {
+      } else if ((VT == MVT::f64 || VT == MVT::v2f32) && (intVal % 2 == 0)) {
         newConstraint = "{d" + utostr(intVal / 2) + "}";
       } else if (VT == MVT::f128 && (intVal % 4 == 0)) {
         newConstraint = "{q" + utostr(intVal / 4) + "}";
@@ -3414,6 +4557,27 @@ void SparcTargetLowering::ReplaceNodeResults(SDNode *N,
     Results.push_back(LoadRes.getValue(1));
     return;
   }
+
+  case ISD::BITCAST:
+  {
+    return;
+  }
+
+  case ISD::FDIV:
+  case ISD::FMUL:
+  case ISD::FADD:
+  case ISD::FSUB:
+  case ISD::FSQRT:
+  case ISD::FABS:
+  case ISD::FNEG:
+  case ISD::FP_EXTEND:
+  case ISD::FP_ROUND:
+  {
+    if (N->getValueType(0) != MVT::f16) return;
+    Results.push_back(LowerOperation(SDValue(N,0), DAG));
+    return;
+  }
+
   }
 }
 
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.h b/llvm/lib/Target/Sparc/SparcISelLowering.h
index 5c9703823a64..bc161989df89 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.h
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.h
@@ -46,7 +46,26 @@ namespace llvm {
 
       TLS_ADD,     // For Thread Local Storage (TLS).
       TLS_LD,
-      TLS_CALL
+      TLS_CALL,
+
+      PACKINSHI,   // insert into packed type as higher value
+      PACKINSLO,   // insert into packed type as lower value
+      PACKEXT,    // extract from packed value
+
+      SWAR,       // swar direct operation
+      SWARCC,    // swar direct operation with accumulation
+      SWARCTRL,   // swar control -> currently wrasr
+
+      SWAPPH,     // SWAP for floating point packed half type (AuAl -> AlAu)
+      MOVVUU,     // copy upper elements from two v2f16 into one v2f16 (AuAl,BuBl -> AuBu)
+      MOVVLL,     // copy lower elements from two v2f16 into one v2f16 (AuAl,BuBl -> AlBl)
+      MOVVUL,     // copy upper element from the first register and lower element from the second register into one v2f16 (AuAl,BuBl -> AuBl)
+      MOVVLU,     // copy lower element from the first register and upper element from the second register and swap them into one v2f16 (AuAl,BuBl -> AlBu)
+
+      MOVVZU,     // copy upper element of v2f16 to lower element and set zero to upper element of v2f16 (AuAl -> 0Au)
+      MOVVZL,     // copy lower element of v2f16 to lower element and set zero to upper element of v2f16 (AuAl -> 0Al)
+
+      ANDCC,      // BTST (ANDCC) instruction
     };
   }
 
@@ -58,6 +77,15 @@ namespace llvm {
 
     bool useSoftFloat() const override;
 
+    bool isHalfFopSoft(unsigned softfp) const;
+    bool isSingleFopSoft(unsigned softfp) const;
+    bool isDoubleFopSoft(unsigned softfp) const;
+    bool isAnySoftHalf() const;
+    bool isAnySingle() const;
+    bool isAnySoftDouble() const;
+    bool isPackedHalf() const;
+    bool isPackedSingle() const;
+
     /// computeKnownBitsForTargetNode - Determine which of the bits specified
     /// in Mask are known to be either zero or one and return them in the
     /// KnownZero/KnownOne bitsets.
@@ -82,6 +110,13 @@ namespace llvm {
                                       std::vector<SDValue> &Ops,
                                       SelectionDAG &DAG) const override;
 
+    unsigned
+    getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
+      if (ConstraintCode == "o")
+        return InlineAsm::Constraint_o;
+      return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
+    }
+
     std::pair<unsigned, const TargetRegisterClass *>
     getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
                                  StringRef Constraint, MVT VT) const override;
@@ -165,6 +200,9 @@ namespace llvm {
                          SelectionDAG &DAG) const;
     SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const;
 
+    SDValue LowerFloatOp(SDValue Op, SelectionDAG &DAG, const char *LibFuncName,
+                         unsigned numArgs) const;
+
     SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, SDValue Arg,
                                  const SDLoc &DL, SelectionDAG &DAG) const;
     SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG,
@@ -175,9 +213,14 @@ namespace llvm {
 
     SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
 
+    SDValue LowerSwarOperation(SDValue Op, SelectionDAG &DAG,
+                                  const SparcTargetLowering &TLI) const;
+
     SDValue PerformBITCASTCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 
-    SDValue bitcastConstantFPToInt(ConstantFPSDNode *C, const SDLoc &DL,
+    SDValue bitcastConstantFPToInt64(ConstantFPSDNode *C, const SDLoc &DL,
+                                   SelectionDAG &DAG) const;
+    SDValue bitcastConstantFPToInt16(ConstantFPSDNode *C, const SDLoc &DL,
                                    SelectionDAG &DAG) const;
 
     SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
index dc3a41c63098..38aeb4b8b654 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
@@ -44,7 +44,9 @@ unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
                                              int &FrameIndex) const {
   if (MI.getOpcode() == SP::LDri || MI.getOpcode() == SP::LDXri ||
       MI.getOpcode() == SP::LDFri || MI.getOpcode() == SP::LDDFri ||
-      MI.getOpcode() == SP::LDQFri) {
+      MI.getOpcode() == SP::LDQFri ||
+      MI.getOpcode() == SP::LDPFHri || MI.getOpcode() == SP::LDPFSri ||
+      MI.getOpcode() == SP::LDHFri) {
     if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
         MI.getOperand(2).getImm() == 0) {
       FrameIndex = MI.getOperand(1).getIndex();
@@ -63,7 +65,9 @@ unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
                                             int &FrameIndex) const {
   if (MI.getOpcode() == SP::STri || MI.getOpcode() == SP::STXri ||
       MI.getOpcode() == SP::STFri || MI.getOpcode() == SP::STDFri ||
-      MI.getOpcode() == SP::STQFri) {
+      MI.getOpcode() == SP::STQFri ||
+      MI.getOpcode() == SP::STPFHri || MI.getOpcode() == SP::STPFSri ||
+      MI.getOpcode() == SP::STHFri) {
     if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
         MI.getOperand(1).getImm() == 0) {
       FrameIndex = MI.getOperand(0).getIndex();
@@ -326,10 +330,19 @@ void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
     numSubRegs = 2;
     movOpc     = SP::ORrr;
     ExtraG0 = true;
-  } else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
-    BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
-      .addReg(SrcReg, getKillRegState(KillSrc));
-  else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) {
+  } else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) {
+    if (!Subtarget.useSoftFopSingle(SoftFops::SOFTFP_MOV)) {
+      BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
+        .addReg(SrcReg, getKillRegState(KillSrc));
+    } else if (!Subtarget.useSoftFopHalf(SoftFops::SOFTFP_MOV)) {
+      BuildMI(MBB, I, DL, get(SP::FMOVH), DestReg)
+        .addReg(SrcReg, getKillRegState(KillSrc));
+    } else { // neither FMOVS nor FMOVH
+fprintf(stderr," Warning: Copy FP registers with instruction FMOVS in soft-float mode\n");
+      BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
+        .addReg(SrcReg, getKillRegState(KillSrc));
+    }
+  } else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) {
     if (Subtarget.isV9()) {
       BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg)
         .addReg(SrcReg, getKillRegState(KillSrc));
@@ -337,7 +350,14 @@ void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
       // Use two FMOVS instructions.
       subRegIdx  = DFP_FP_SubRegsIdx;
       numSubRegs = 2;
-      movOpc     = SP::FMOVS;
+      if (!Subtarget.useSoftFopSingle(SoftFops::SOFTFP_MOV)) {
+        movOpc     = SP::FMOVS;
+      } else if (!Subtarget.useSoftFopHalf(SoftFops::SOFTFP_MOV)) {
+        movOpc     = SP::FMOVH;
+      } else {
+fprintf(stderr," Warning: Copy FP registers with instruction FMOVS in soft-float mode\n");
+        movOpc     = SP::FMOVS;
+      }
     }
   } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) {
     if (Subtarget.isV9()) {
@@ -354,8 +374,29 @@ void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
       // Use four FMOVS instructions.
       subRegIdx  = QFP_FP_SubRegsIdx;
       numSubRegs = 4;
-      movOpc     = SP::FMOVS;
+      if (!Subtarget.useSoftFopSingle(SoftFops::SOFTFP_MOV)) {
+        movOpc     = SP::FMOVS;
+      } else if (!Subtarget.useSoftFopHalf(SoftFops::SOFTFP_MOV)) {
+        movOpc     = SP::FMOVH;
+      } else {
+fprintf(stderr," Warning: Copy FP registers with instruction FMOVS in soft-float mode\n");
+        movOpc     = SP::FMOVS;
+      }
+    }
+
+  } else if (SP::HFPRegsRegClass.contains(DestReg, SrcReg)) {
+    BuildMI(MBB, I, DL, get(SP::FMOVH), DestReg)
+      .addReg(SrcReg, getKillRegState(KillSrc));
+
+  } else if (SP::PFPHRegsRegClass.contains(DestReg, SrcReg)) {
+    if (!Subtarget.useSoftFopSingle(SoftFops::SOFTFP_MOV)) {
+      BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
+        .addReg(SrcReg, getKillRegState(KillSrc));
+    } else if (!Subtarget.useSoftFopHalf(SoftFops::SOFTFP_MOV)) {
+      BuildMI(MBB, I, DL, get(SP::FMOVH), DestReg)
+        .addReg(SrcReg, getKillRegState(KillSrc));
     }
+
   } else if (SP::ASRRegsRegClass.contains(DestReg) &&
              SP::IntRegsRegClass.contains(SrcReg)) {
     BuildMI(MBB, I, DL, get(SP::WRASRrr), DestReg)
@@ -365,8 +406,14 @@ void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
              SP::ASRRegsRegClass.contains(SrcReg)) {
     BuildMI(MBB, I, DL, get(SP::RDASR), DestReg)
         .addReg(SrcReg, getKillRegState(KillSrc));
-  } else
+
+  } else if (SP::HFPRegsRegClass.contains(SrcReg) &&
+             SP::IntRegsRegClass.contains(DestReg)) {           // copy from F16 to Int
+// copy only over SP
+    llvm_unreachable("No HFPreg to Ireg copy");
+  } else {
     llvm_unreachable("Impossible reg-to-reg copy");
+  }
 
   if (numSubRegs == 0 || subRegIdx == nullptr || movOpc == 0)
     return;
@@ -426,6 +473,14 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
     // lowered into two STDs in eliminateFrameIndex.
     BuildMI(MBB, I, DL, get(SP::STQFri)).addFrameIndex(FI).addImm(0)
       .addReg(SrcReg,  getKillRegState(isKill)).addMemOperand(MMO);
+
+  else if (RC == &SP::HFPRegsRegClass)
+    BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
+      .addReg(SrcReg,  getKillRegState(isKill)).addMemOperand(MMO);
+  else if (RC == &SP::PFPHRegsRegClass)
+    BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
+      .addReg(SrcReg,  getKillRegState(isKill)).addMemOperand(MMO);
+
   else
     llvm_unreachable("Can't store this register to stack slot");
 }
@@ -464,6 +519,14 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
     // lowered into two LDDs in eliminateFrameIndex.
     BuildMI(MBB, I, DL, get(SP::LDQFri), DestReg).addFrameIndex(FI).addImm(0)
       .addMemOperand(MMO);
+
+  else if (RC == &SP::HFPRegsRegClass)
+    BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0)
+      .addMemOperand(MMO);
+  else if (RC == &SP::PFPHRegsRegClass)
+    BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0)
+      .addMemOperand(MMO);
+
   else
     llvm_unreachable("Can't load this register from stack slot");
 }
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td
index b161e2a9d087..4daf2021ab56 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.td
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td
@@ -20,6 +20,12 @@ include "SparcInstrFormats.td"
 // Feature predicates.
 //===----------------------------------------------------------------------===//
 
+class PatFPH<SDPatternOperator OpNode, InstSP Inst>
+    : Pat<(OpNode PFPHRegs:$rs1), (Inst PFPHRegs:$rs1)>;
+
+class PatFPHFPH<SDPatternOperator OpNode, InstSP Inst>
+    : Pat<(OpNode PFPHRegs:$rs1, PFPHRegs:$rs2), (Inst PFPHRegs:$rs1, PFPHRegs:$rs2)>;
+
 // True when generating 32-bit code.
 def Is32Bit : Predicate<"!Subtarget->is64Bit()">;
 
@@ -74,6 +80,32 @@ def HasFSMULD : Predicate<"!Subtarget->hasNoFSMULD()">;
 // will pick deprecated instructions.
 def UseDeprecatedInsts : Predicate<"Subtarget->useDeprecatedV8Instructions()">;
 
+// daiteq ESA extensions
+def HasAnyHalf : Predicate<"Subtarget->useHardHalf()">;
+def HasFMOVh : Predicate<"!Subtarget->useSoftFopHalf(llvm::SoftFops::SOFTFP_MOV)">;
+def HasFNEGh : Predicate<"!Subtarget->useSoftFopHalf(llvm::SoftFops::SOFTFP_NEG)">;
+def HasFABSh : Predicate<"!Subtarget->useSoftFopHalf(llvm::SoftFops::SOFTFP_ABS)">;
+def HasFSQRTh : Predicate<"!Subtarget->useSoftFopHalf(llvm::SoftFops::SOFTFP_SQRT)">;
+def HasFADDh : Predicate<"!Subtarget->useSoftFopHalf(llvm::SoftFops::SOFTFP_ADD)">;
+def HasFSUBh : Predicate<"!Subtarget->useSoftFopHalf(llvm::SoftFops::SOFTFP_SUB)">;
+def HasFMULh : Predicate<"!Subtarget->useSoftFopHalf(llvm::SoftFops::SOFTFP_MUL)">;
+def HasFDIVh : Predicate<"!Subtarget->useSoftFopHalf(llvm::SoftFops::SOFTFP_DIV)">;
+def HasFhMULs: Predicate<"!Subtarget->useSoftFopHalf(llvm::SoftFops::SOFTFP_MULEX)">;
+def HasFiTOh : Predicate<"!Subtarget->useSoftFopHalf(llvm::SoftFops::SOFTFP_CI2F)">;
+def HasFhTOi : Predicate<"!Subtarget->useSoftFopHalf(llvm::SoftFops::SOFTFP_CF2I)">;
+def HasFhTOs : Predicate<"!Subtarget->useSoftFopHalf(llvm::SoftFops::SOFTFP_CFUP)">;
+def HasFCMPh : Predicate<"!Subtarget->useSoftFopHalf(llvm::SoftFops::SOFTFP_CMP)">;
+
+def HasFPPackHalf : Predicate<"Subtarget->usePackedHalf()">;
+
+def HasFPPackSingle : Predicate<"Subtarget->usePackedSingle()">;
+
+def HasFsTOh : Predicate<"!Subtarget->useSoftFopSingle(llvm::SoftFops::SOFTFP_CFDN)">;
+
+def HasFMOVs : Predicate<"!Subtarget->useSoftFopSingle(llvm::SoftFops::SOFTFP_MOV)">;
+def HasFNEGs : Predicate<"!Subtarget->useSoftFopSingle(llvm::SoftFops::SOFTFP_NEG)">;
+def HasFABSs : Predicate<"!Subtarget->useSoftFopSingle(llvm::SoftFops::SOFTFP_ABS)">;
+
 //===----------------------------------------------------------------------===//
 // Instruction Pattern Stuff
 //===----------------------------------------------------------------------===//
@@ -220,6 +252,8 @@ def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
 def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
 def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
 
+def SPandcc : SDNode<"SPISD::ANDCC", SDTSPcmpicc, [SDNPOutGlue]>;
+
 def SPhi    : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
 def SPlo    : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
 
@@ -265,6 +299,24 @@ def getPCX        : Operand<iPTR> {
   let PrintMethod = "printGetPCX";
 }
 
+// support for swar
+def SDTPSWAR32  : SDTypeProfile<1, 2, [SDTCisVT<0, vswp32>, SDTCisVT<1, vswp32>, SDTCisVT<2, vswp32>]>;
+def SPswar32b   : SDNode<"SPISD::SWAR", SDTPSWAR32>;
+
+def SDTPSWARcc32 : SDTypeProfile<1, 3, [SDTCisVT<0, vswp32>, SDTCisVT<1, vswp32>, SDTCisVT<2, vswp32>, SDTCisVT<3, i32>]>;
+def SPswarcc32b  : SDNode<"SPISD::SWARCC", SDTPSWARcc32, [SDNPInGlue]>;
+
+
+def SDTv2f16UnOp : SDTypeProfile<1, 1, [SDTCisVT<0, v2f16>, SDTCisVT<1, v2f16>]>;
+def SDTv2f16BinOp : SDTypeProfile<1, 2, [SDTCisVT<0, v2f16>, SDTCisVT<1, v2f16>, SDTCisVT<2, v2f16>]>;
+def SPswapph : SDNode<"SPISD::SWAPPH", SDTv2f16UnOp>;
+def SPmovhzu : SDNode<"SPISD::MOVVZU", SDTv2f16UnOp>;
+def SPmovhzl : SDNode<"SPISD::MOVVZL", SDTv2f16UnOp>;
+def SPmovhuu : SDNode<"SPISD::MOVVUU", SDTv2f16BinOp>;
+def SPmovhll : SDNode<"SPISD::MOVVLL", SDTv2f16BinOp>;
+def SPmovhlu : SDNode<"SPISD::MOVVLU", SDTv2f16BinOp>;
+def SPmovhul : SDNode<"SPISD::MOVVUL", SDTv2f16BinOp>;
+
 //===----------------------------------------------------------------------===//
 // SPARC Flag Conditions
 //===----------------------------------------------------------------------===//
@@ -485,6 +537,20 @@ let Uses = [ICC], usesCustomInserter = 1 in {
    : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
             "; SELECT_CC_QFP_ICC PSEUDO!",
             [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>;
+
+  def SELECT_CC_HFP_ICC
+   : Pseudo<(outs HFPRegs:$dst), (ins HFPRegs:$T, HFPRegs:$F, i32imm:$Cond),
+            "; SELECT_CC_HFP_ICC PSEUDO!",
+            [(set f16:$dst, (SPselecticc f16:$T, f16:$F, imm:$Cond))]>;
+  def SELECT_CC_PFPH_ICC
+   : Pseudo<(outs PFPHRegs:$dst), (ins PFPHRegs:$T, PFPHRegs:$F, i32imm:$Cond),
+            "; SELECT_CC_PFPH_ICC PSEUDO!",
+            [(set v2f16:$dst, (SPselecticc v2f16:$T, v2f16:$F, imm:$Cond))]>;
+  def SELECT_CC_PFPS_ICC
+   : Pseudo<(outs PFPSRegs:$dst), (ins PFPSRegs:$T, PFPSRegs:$F, i32imm:$Cond),
+            "; SELECT_CC_PFPS_ICC PSEUDO!",
+            [(set v2f32:$dst, (SPselecticc v2f32:$T, v2f32:$F, imm:$Cond))]>;
+
 }
 
 let usesCustomInserter = 1, Uses = [FCC0] in {
@@ -506,6 +572,20 @@ let usesCustomInserter = 1, Uses = [FCC0] in {
    : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
             "; SELECT_CC_QFP_FCC PSEUDO!",
             [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>;
+
+  def SELECT_CC_HFP_FCC
+   : Pseudo<(outs HFPRegs:$dst), (ins HFPRegs:$T, HFPRegs:$F, i32imm:$Cond),
+            "; SELECT_CC_HFP_FCC PSEUDO!",
+            [(set f16:$dst, (SPselectfcc f16:$T, f16:$F, imm:$Cond))]>;
+  def SELECT_CC_PFPH_FCC
+   : Pseudo<(outs PFPHRegs:$dst), (ins PFPHRegs:$T, PFPHRegs:$F, i32imm:$Cond),
+            "; SELECT_CC_PFPH_FCC PSEUDO!",
+            [(set v2f16:$dst, (SPselectfcc v2f16:$T, v2f16:$F, imm:$Cond))]>;
+  def SELECT_CC_PFPS_FCC
+   : Pseudo<(outs PFPSRegs:$dst), (ins PFPSRegs:$T, PFPSRegs:$F, i32imm:$Cond),
+            "; SELECT_CC_PFPS_FCC PSEUDO!",
+            [(set v2f32:$dst, (SPselectfcc v2f32:$T, v2f32:$F, imm:$Cond))]>;
+
 }
 
 // Section B.1 - Load Integer Instructions, p. 90
@@ -520,7 +600,16 @@ let DecoderMethod = "DecodeLoadInt" in {
 let DecoderMethod = "DecodeLoadIntPair" in
   defm LDD : LoadA<"ldd", 0b000011, 0b010011, load, IntPair, v2i32, IIC_ldd>;
 
+let DecoderMethod = "DecodeLoadSwar" in {
+  defm LDVSWP32   : LoadA<"ld", 0b000000, 0b010000, load, SwarRegs, vswp32>;
+}
+
 // Section B.2 - Load Floating-point Instructions, p. 92
+let DecoderMethod = "DecodeLoadHFP" in {
+  defm LDHF   : Load<"ldh",  0b101010, load, HFPRegs, f16, IIC_iu_or_fpu_instr>,
+                 Requires<[HasAnyHalf]>;
+}
+
 let DecoderMethod = "DecodeLoadFP" in {
   defm LDF   : Load<"ld",  0b100000, load,    FPRegs,  f32, IIC_iu_or_fpu_instr>;
   def LDFArr : LoadASI<"ld",  0b110000, load, FPRegs,  f32, IIC_iu_or_fpu_instr>,
@@ -535,6 +624,14 @@ let DecoderMethod = "DecodeLoadQFP" in
   defm LDQF  : LoadA<"ldq", 0b100010, 0b110010, load, QFPRegs, f128>,
                Requires<[HasV9, HasHardQuad]>;
 
+let DecoderMethod = "DecodeLoadPFPH" in {
+  defm LDPFH   : Load<"ld",  0b100000, load,    PFPHRegs,  v2f16, IIC_iu_or_fpu_instr>;
+}
+
+let DecoderMethod = "DecodeLoadPFPS" in {
+  defm LDPFS   : Load<"ldd",  0b100011, load,    PFPSRegs,  v2f32, IIC_iu_or_fpu_instr>;
+}
+
 let DecoderMethod = "DecodeLoadCP" in
   defm LDC   : Load<"ld", 0b110000, load, CoprocRegs, i32>;
 let DecoderMethod = "DecodeLoadCPPair" in
@@ -575,7 +672,16 @@ let DecoderMethod = "DecodeStoreInt" in {
 let DecoderMethod = "DecodeStoreIntPair" in
   defm STD   : StoreA<"std", 0b000111, 0b010111, store, IntPair, v2i32, IIC_std>;
 
+let DecoderMethod = "DecodeStoreInt" in {
+  defm STVSWP32    : StoreA<"st",  0b000100, 0b010100, store,  SwarRegs, vswp32>;
+}
+
 // Section B.5 - Store Floating-point Instructions, p. 97
+let DecoderMethod = "DecodeStoreHFP" in {
+  defm STHF  : Store<"sth",  0b101110, store, HFPRegs, f16>,
+                Requires<[HasAnyHalf]>;
+}
+
 let DecoderMethod = "DecodeStoreFP" in {
   defm STF   : Store<"st",  0b100100, store,         FPRegs,  f32>;
   def STFArr : StoreASI<"st",  0b110100, store,      FPRegs,  f32>,
@@ -590,6 +696,13 @@ let DecoderMethod = "DecodeStoreQFP" in
   defm STQF  : StoreA<"stq", 0b100110, 0b110110, store, QFPRegs, f128>,
                Requires<[HasV9, HasHardQuad]>;
 
+let DecoderMethod = "DecodeStorePFPH" in
+  defm STPFH   : Store<"st",  0b100100, store,         PFPHRegs,  v2f16>;
+
+let DecoderMethod = "DecodeStorePFPS" in
+  defm STPFS   : Store<"std",  0b100111, store,        PFPSRegs,  v2f32>;
+
+
 let DecoderMethod = "DecodeStoreCP" in
   defm STC   : Store<"st", 0b110100, store, CoprocRegs, i32>;
 
@@ -694,6 +807,19 @@ def XNORri  : F3_2<2, 0b000111,
                    (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
                    "xnor $rs1, $simm13, $rd", []>;
 
+// SWAR
+def SWAR_VS1      : F3_1<2, 0b001001,
+                  (outs SwarRegs:$rd), (ins SwarRegs:$rs1, SwarRegs:$rs2),
+                  "swar $rs1, $rs2, $rd",
+                  [(set vswp32:$rd, (SPswar32b vswp32:$rs1, vswp32:$rs2))]>;
+
+// SWARCC
+def SWARCC_VS1    : F3_1<2, 0b011001,
+                  (outs SwarRegs:$rd), (ins SwarRegs:$rs1, SwarRegs:$rs2, i32imm:$Cond),
+                  "swarcc $rs1, $rs2, $rd",
+                  [(set vswp32:$rd, (SPswarcc32b vswp32:$rs1, vswp32:$rs2, imm:$Cond))]>;
+
+
 def : Pat<(and IntRegs:$rs1, SETHIimm_not:$rs2),
           (ANDNrr i32:$rs1, (SETHIi SETHIimm_not:$rs2))>;
 
@@ -701,7 +827,15 @@ def : Pat<(or IntRegs:$rs1, SETHIimm_not:$rs2),
           (ORNrr i32:$rs1,  (SETHIi SETHIimm_not:$rs2))>;
 
 let Defs = [ICC] in {
-  defm ANDCC  : F3_12np<"andcc",  0b010001>;
+  def ANDCCrr   : F3_1<2, 0b010001,
+                     (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
+                     "btst $rs2, $rs1",
+                     [(set i32:$rd, (SPandcc i32:$rs1, i32:$rs2))]>;
+  def ANDCCri   : F3_2<2, 0b010001,
+                     (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
+                     "btst $simm13, $rs1",
+                     [(set i32:$rd, (SPandcc i32:$rs1, (i32 simm13:$simm13)))]>;
+
   defm ANDNCC : F3_12np<"andncc", 0b010101>;
   defm ORCC   : F3_12np<"orcc",   0b010010>;
   defm ORNCC  : F3_12np<"orncc",  0b010110>;
@@ -1129,6 +1263,12 @@ let rd = 0 in {
 // Section B.33 - Floating-point Operate (FPop) Instructions
 
 // Convert Integer to Floating-point Instructions, p. 141
+def FITOH : F3_3u<2, 0b110100, 0b011000000,
+                 (outs HFPRegs:$rd), (ins FPRegs:$rs2),
+                 "fitoh $rs2, $rd",
+                 [(set HFPRegs:$rd, (SPitof FPRegs:$rs2))],
+                 IIC_fpu_fast_instr>,
+                 Requires<[HasFiTOh]>;
 def FITOS : F3_3u<2, 0b110100, 0b011000100,
                  (outs FPRegs:$rd), (ins FPRegs:$rs2),
                  "fitos $rs2, $rd",
@@ -1146,6 +1286,13 @@ def FITOQ : F3_3u<2, 0b110100, 0b011001100,
                  Requires<[HasHardQuad]>;
 
 // Convert Floating-point to Integer Instructions, p. 142
+def FHTOI : F3_3u<2, 0b110100, 0b011010000,
+                 (outs FPRegs:$rd), (ins HFPRegs:$rs2),
+                 "fhtoi $rs2, $rd",
+                 [(set FPRegs:$rd, (SPftoi HFPRegs:$rs2))],
+                 IIC_fpu_fast_instr>,
+                 Requires<[HasFhTOi]>;
+
 def FSTOI : F3_3u<2, 0b110100, 0b011010001,
                  (outs FPRegs:$rd), (ins FPRegs:$rs2),
                  "fstoi $rs2, $rd",
@@ -1163,6 +1310,17 @@ def FQTOI : F3_3u<2, 0b110100, 0b011010011,
                  Requires<[HasHardQuad]>;
 
 // Convert between Floating-point Formats Instructions, p. 143
+def FSTOH : F3_3u<2, 0b110100, 0b011000001,
+                 (outs HFPRegs:$rd), (ins FPRegs:$rs2),
+                 "fstoh $rs2, $rd",
+                 [(set f16:$rd, (fpround f32:$rs2))]>,
+                 Requires<[HasFsTOh]>;
+def FHTOS : F3_3u<2, 0b110100, 0b011000101,
+                 (outs FPRegs:$rd), (ins HFPRegs:$rs2),
+                 "fhtos $rs2, $rd",
+                 [(set f32:$rd, (fpextend f16:$rs2))]>,
+                 Requires<[HasFhTOs]>;
+
 def FSTOD : F3_3u<2, 0b110100, 0b011001001,
                  (outs DFPRegs:$rd), (ins FPRegs:$rs2),
                  "fstod $rs2, $rd",
@@ -1194,45 +1352,154 @@ def FQTOD : F3_3u<2, 0b110100, 0b011001011,
                  [(set f64:$rd, (fpround f128:$rs2))]>,
                  Requires<[HasHardQuad]>;
 
+// daiteq - Floating-point packing/unpacking Instructions
+def FPMOVHU : F3_3u<2, 0b110100, 0b000100000,
+                   (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                   "fmovhu $rs1, $rs2, $rd",
+                   []>,
+                   Requires<[HasFPPackHalf]>;
+def : PatFPHFPH<SPmovhuu, FPMOVHU>;
+
+def FPMOVHL : F3_3u<2, 0b110100, 0b000100001,
+                   (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                   "fmovhl $rs1, $rs2, $rd",
+                   []>,
+                   Requires<[HasFPPackHalf]>;
+def : PatFPHFPH<SPmovhll, FPMOVHL>;
+
+def FPMOVHUL : F3_3u<2, 0b110100, 0b000100010,
+                   (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                   "fmovhul $rs1, $rs2, $rd",
+                   []>,
+                   Requires<[HasFPPackHalf]>;
+def : PatFPHFPH<SPmovhul, FPMOVHUL>;
+
+def FPMOVHLU : F3_3u<2, 0b110100, 0b000100011,
+                   (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                   "fmovhlu $rs1, $rs2, $rd",
+                   []>,
+                   Requires<[HasFPPackHalf]>;
+def : PatFPHFPH<SPmovhlu, FPMOVHLU>;
+
+def FPSWAPH : F3_3u<2, 0b110100, 0b000100100,
+                   (outs PFPHRegs:$rd), (ins PFPHRegs:$rs2),
+                   "fswaph $rs2, $rd",
+                   []>,
+                   Requires<[HasFPPackHalf]>;
+def : PatFPH<SPswapph, FPSWAPH>;
+
+
+def FPMOVHZU : F3_3u<2, 0b110100, 0b000100101,
+                   (outs PFPHRegs:$rd), (ins PFPHRegs:$rs2),
+                   "fmovhzu $rs2, $rd",
+                   []>,
+                   Requires<[HasFPPackHalf]>;
+def : PatFPH<SPmovhzu, FPMOVHZU>;
+
+
+def FPMOVHZL : F3_3u<2, 0b110100, 0b000100110,
+                   (outs PFPHRegs:$rd), (ins PFPHRegs:$rs2),
+                   "fmovhzl $rs2, $rd",
+                   []>,
+                   Requires<[HasFPPackHalf]>;
+def : PatFPH<SPmovhzl, FPMOVHZL>;
+
+
 // Floating-point Move Instructions, p. 144
+def FMOVH : F3_3u<2, 0b110100, 0b000000000,
+                 (outs HFPRegs:$rd), (ins HFPRegs:$rs2),
+                 "fmovh $rs2, $rd", []>,
+                 Requires<[HasFMOVh]>;
 def FMOVS : F3_3u<2, 0b110100, 0b000000001,
                  (outs FPRegs:$rd), (ins FPRegs:$rs2),
-                 "fmovs $rs2, $rd", []>;
+                 "fmovs $rs2, $rd", [], IIC_fpu_movs>;
+//                 , Requires<[HasFMOVs]>;
+
+def FNEGH : F3_3u<2, 0b110100, 0b000000100,
+                 (outs HFPRegs:$rd), (ins HFPRegs:$rs2),
+                 "fnegh $rs2, $rd",
+                 [(set f16:$rd, (fneg f16:$rs2))]>,
+                 Requires<[HasFNEGh]>;
+// fnegh can be used also for packed variables - it change both halves
+def FNEGPH: F3_3u<2, 0b110100, 0b000000100,
+                 (outs PFPHRegs:$rd), (ins PFPHRegs:$rs2),
+                 "fnegh $rs2, $rd",
+                 [(set v2f16:$rd, (fneg v2f16:$rs2))]>,
+                 Requires<[HasFNEGh]>;
 def FNEGS : F3_3u<2, 0b110100, 0b000000101,
                  (outs FPRegs:$rd), (ins FPRegs:$rs2),
                  "fnegs $rs2, $rd",
                  [(set f32:$rd, (fneg f32:$rs2))],
-                 IIC_fpu_negs>;
+                 IIC_fpu_negs>,
+                 Requires<[HasFNEGs]>;
+def FABSH : F3_3u<2, 0b110100, 0b000001000,
+                 (outs HFPRegs:$rd), (ins HFPRegs:$rs2),
+                 "fabsh $rs2, $rd",
+                 [(set f16:$rd, (fabs f16:$rs2))],
+                 IIC_fpu_abs>,
+                 Requires<[HasFABSh]>;
+def FABSPH : F3_3u<2, 0b110100, 0b000001000,
+                 (outs PFPHRegs:$rd), (ins PFPHRegs:$rs2),
+                 "fabsh $rs2, $rd",
+                 [(set v2f16:$rd, (fabs v2f16:$rs2))],
+                 IIC_fpu_abs>,
+                 Requires<[HasFABSh]>;
 def FABSS : F3_3u<2, 0b110100, 0b000001001,
                  (outs FPRegs:$rd), (ins FPRegs:$rs2),
                  "fabss $rs2, $rd",
                  [(set f32:$rd, (fabs f32:$rs2))],
-                 IIC_fpu_abs>;
+                 IIC_fpu_abs>,
+                 Requires<[HasFABSs]>;
 
 
 // Floating-point Square Root Instructions, p.145
+def FSQRTH : F3_3u<2, 0b110100, 0b000101000,
+                  (outs HFPRegs:$rd), (ins HFPRegs:$rs2),
+                  "fsqrth $rs2, $rd",
+                  [(set f16:$rd, (fsqrt f16:$rs2))]>,
+                  Requires<[HasFSQRTh]>;
 // FSQRTS generates an erratum on LEON processors, so by disabling this instruction
 // this will be promoted to use FSQRTD with doubles instead.
-let Predicates = [HasNoFdivSqrtFix] in
+let Predicates = [HasNoFdivSqrtFix] in {
 def FSQRTS : F3_3u<2, 0b110100, 0b000101001,
                   (outs FPRegs:$rd), (ins FPRegs:$rs2),
                   "fsqrts $rs2, $rd",
                   [(set f32:$rd, (fsqrt f32:$rs2))],
                   IIC_fpu_sqrts>;
+}
+
 def FSQRTD : F3_3u<2, 0b110100, 0b000101010,
                   (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
                   "fsqrtd $rs2, $rd",
                   [(set f64:$rd, (fsqrt f64:$rs2))],
                   IIC_fpu_sqrtd>;
+
 def FSQRTQ : F3_3u<2, 0b110100, 0b000101011,
                   (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
                   "fsqrtq $rs2, $rd",
                   [(set f128:$rd, (fsqrt f128:$rs2))]>,
                   Requires<[HasHardQuad]>;
 
+def FPSQRTH : F3_3<2, 0b110100, 0b010101001,
+                  (outs PFPHRegs:$rd), (ins PFPHRegs:$rs2),
+                  "fsqrtph $rs2, $rd",
+                  [(set v2f16:$rd, (fsqrt v2f16:$rs2))]>,
+                  Requires<[HasFPPackHalf]>;
+def FPSQRTS : F3_3<2, 0b110100, 0b010101010,
+                  (outs PFPSRegs:$rd), (ins PFPSRegs:$rs2),
+                  "fsqrtps $rs2, $rd",
+                  [(set v2f32:$rd, (fsqrt v2f32:$rs2))]>,
+                  Requires<[HasFPPackSingle]>;
+
 
 
 // Floating-point Add and Subtract Instructions, p. 146
+def FADDH  : F3_3<2, 0b110100, 0b001000000,
+                  (outs HFPRegs:$rd), (ins HFPRegs:$rs1, HFPRegs:$rs2),
+                  "faddh $rs1, $rs2, $rd",
+                  [(set f16:$rd, (fadd f16:$rs1, f16:$rs2))],
+                  IIC_fpu_fast_instr>,
+                  Requires<[HasFADDh]>;
 def FADDS  : F3_3<2, 0b110100, 0b001000001,
                   (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
                   "fadds $rs1, $rs2, $rd",
@@ -1248,7 +1515,44 @@ def FADDQ  : F3_3<2, 0b110100, 0b001000011,
                   "faddq $rs1, $rs2, $rd",
                   [(set f128:$rd, (fadd f128:$rs1, f128:$rs2))]>,
                   Requires<[HasHardQuad]>;
-
+def FPADDH : F3_3<2, 0b110100, 0b010010001,
+                  (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                  "faddph $rs1, $rs2, $rd",
+                  [(set v2f16:$rd, (fadd v2f16:$rs1, v2f16:$rs2))]>,
+                  Requires<[HasFPPackHalf]>;
+def FPADDS : F3_3<2, 0b110100, 0b010010010,
+                  (outs PFPSRegs:$rd), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                  "faddps $rs1, $rs2, $rd",
+                  [(set v2f32:$rd, (fadd v2f32:$rs1, v2f32:$rs2))]>,
+                  Requires<[HasFPPackSingle]>;
+
+def FADDRPH : F3_3<2, 0b110100, 0b010000001,
+                  (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                  "faddrph $rs1, $rs2, $rd",
+                  [(set v2f16:$rd, (fadd v2f16:$rs1, v2f16:$rs2))]>,
+                  Requires<[HasFPPackHalf]>;
+def FADDRPS : F3_3<2, 0b110100, 0b010000010,
+                  (outs PFPSRegs:$rd), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                  "faddrps $rs1, $rs2, $rd",
+                  [(set v2f32:$rd, (fadd v2f32:$rs1, v2f32:$rs2))]>,
+                  Requires<[HasFPPackSingle]>;
+def FADDXPH : F3_3<2, 0b110100, 0b010110001,
+                  (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                  "faddxph $rs1, $rs2, $rd",
+                  [(set v2f16:$rd, (fadd v2f16:$rs1, v2f16:$rs2))]>,
+                  Requires<[HasFPPackHalf]>;
+def FADDXPS : F3_3<2, 0b110100, 0b010110010,
+                  (outs PFPSRegs:$rd), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                  "faddxps $rs1, $rs2, $rd",
+                  [(set v2f32:$rd, (fadd v2f32:$rs1, v2f32:$rs2))]>,
+                  Requires<[HasFPPackSingle]>;
+
+
+def FSUBH  : F3_3<2, 0b110100, 0b001000100,
+                  (outs HFPRegs:$rd), (ins HFPRegs:$rs1, HFPRegs:$rs2),
+                  "fsubh $rs1, $rs2, $rd",
+                  [(set f16:$rd, (fsub f16:$rs1, f16:$rs2))]>,
+                  Requires<[HasFSUBh]>;
 def FSUBS  : F3_3<2, 0b110100, 0b001000101,
                   (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
                   "fsubs $rs1, $rs2, $rd",
@@ -1264,15 +1568,73 @@ def FSUBQ  : F3_3<2, 0b110100, 0b001000111,
                   "fsubq $rs1, $rs2, $rd",
                   [(set f128:$rd, (fsub f128:$rs1, f128:$rs2))]>,
                   Requires<[HasHardQuad]>;
+def FSUBPH : F3_3<2, 0b110100, 0b010010101,
+                  (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                  "fsubph $rs1, $rs2, $rd",
+                  [(set v2f16:$rd, (fsub v2f16:$rs1, v2f16:$rs2))]>,
+                  Requires<[HasFPPackHalf]>;
+def FSUBPS : F3_3<2, 0b110100, 0b010010110,
+                  (outs PFPSRegs:$rd), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                  "fsubps $rs1, $rs2, $rd",
+                  [(set v2f32:$rd, (fsub v2f32:$rs1, v2f32:$rs2))]>,
+                  Requires<[HasFPPackSingle]>;
+
+def FSUBRPH : F3_3<2, 0b110100, 0b010000101,
+                  (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                  "fsubrph $rs1, $rs2, $rd",
+                  [(set v2f16:$rd, (fsub v2f16:$rs1, v2f16:$rs2))]>,
+                  Requires<[HasFPPackHalf]>;
+def FSUBRPS : F3_3<2, 0b110100, 0b010000110,
+                  (outs PFPSRegs:$rd), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                  "fsubrps $rs1, $rs2, $rd",
+                  [(set v2f32:$rd, (fsub v2f32:$rs1, v2f32:$rs2))]>,
+                  Requires<[HasFPPackSingle]>;
+def FSUBXPH : F3_3<2, 0b110100, 0b010110101,
+                  (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                  "fsubxph $rs1, $rs2, $rd",
+                  [(set v2f16:$rd, (fsub v2f16:$rs1, v2f16:$rs2))]>,
+                  Requires<[HasFPPackHalf]>;
+def FSUBXPS : F3_3<2, 0b110100, 0b010110110,
+                  (outs PFPSRegs:$rd), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                  "fsubxps $rs1, $rs2, $rd",
+                  [(set v2f32:$rd, (fsub v2f32:$rs1, v2f32:$rs2))]>,
+                  Requires<[HasFPPackSingle]>;
+
+def FADDSUBRPH : F3_3<2, 0b110100, 0b010100001,
+                  (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                  "faddsubrph $rs1, $rs2, $rd",
+                  []>,
+                  Requires<[HasFPPackHalf]>;
+def FADDSUBRPS : F3_3<2, 0b110100, 0b010100010,
+                  (outs PFPSRegs:$rd), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                  "faddsubrps $rs1, $rs2, $rd",
+                  []>,
+                  Requires<[HasFPPackSingle]>;
+def FSUBADDRPH : F3_3<2, 0b110100, 0b010100101,
+                  (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                  "fsubaddrph $rs1, $rs2, $rd",
+                  []>,
+                  Requires<[HasFPPackHalf]>;
+def FSUBADDRPS : F3_3<2, 0b110100, 0b010100110,
+                  (outs PFPSRegs:$rd), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                  "fsubaddrps $rs1, $rs2, $rd",
+                  []>,
+                  Requires<[HasFPPackSingle]>;
 
 
 // Floating-point Multiply and Divide Instructions, p. 147
+def FMULH  : F3_3<2, 0b110100, 0b001001000,
+                  (outs HFPRegs:$rd), (ins HFPRegs:$rs1, HFPRegs:$rs2),
+                  "fmulh $rs1, $rs2, $rd",
+                  [(set f16:$rd, (fmul f16:$rs1, f16:$rs2))],
+                  IIC_fpu_mulh>,
+                  Requires<[HasFMULh]>;
 def FMULS  : F3_3<2, 0b110100, 0b001001001,
                   (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
                   "fmuls $rs1, $rs2, $rd",
                   [(set f32:$rd, (fmul f32:$rs1, f32:$rs2))],
                   IIC_fpu_muls>,
-		  Requires<[HasFMULS]>;
+                  Requires<[HasFMULS]>;
 def FMULD  : F3_3<2, 0b110100, 0b001001010,
                   (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
                   "fmuld $rs1, $rs2, $rd",
@@ -1283,14 +1645,52 @@ def FMULQ  : F3_3<2, 0b110100, 0b001001011,
                   "fmulq $rs1, $rs2, $rd",
                   [(set f128:$rd, (fmul f128:$rs1, f128:$rs2))]>,
                   Requires<[HasHardQuad]>;
-
+def FMULPH : F3_3<2, 0b110100, 0b010011001,
+                  (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                  "fmulph $rs1, $rs2, $rd",
+                  [(set v2f16:$rd, (fmul v2f16:$rs1, v2f16:$rs2))]>,
+                  Requires<[HasFPPackHalf]>;
+def FMULPS : F3_3<2, 0b110100, 0b010011010,
+                  (outs PFPSRegs:$rd), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                  "fmulps $rs1, $rs2, $rd",
+                  [(set v2f32:$rd, (fmul v2f32:$rs1, v2f32:$rs2))]>,
+                  Requires<[HasFPPackSingle]>;
+
+def FMULRPH : F3_3<2, 0b110100, 0b010001001,
+                  (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                  "fmulrph $rs1, $rs2, $rd",
+                  [(set v2f16:$rd, (fmul v2f16:$rs1, v2f16:$rs2))]>,
+                  Requires<[HasFPPackHalf]>;
+def FMULRPS : F3_3<2, 0b110100, 0b010001010,
+                  (outs PFPSRegs:$rd), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                  "fmulrps $rs1, $rs2, $rd",
+                  [(set v2f32:$rd, (fmul v2f32:$rs1, v2f32:$rs2))]>,
+                  Requires<[HasFPPackSingle]>;
+def FMULXPH : F3_3<2, 0b110100, 0b010111001,
+                  (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                  "fmulxph $rs1, $rs2, $rd",
+                  [(set v2f16:$rd, (fmul v2f16:$rs1, v2f16:$rs2))]>,
+                  Requires<[HasFPPackHalf]>;
+def FMULXPS : F3_3<2, 0b110100, 0b010111010,
+                  (outs PFPSRegs:$rd), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                  "fmulxps $rs1, $rs2, $rd",
+                  [(set v2f32:$rd, (fmul v2f32:$rs1, v2f32:$rs2))]>,
+                  Requires<[HasFPPackSingle]>;
+
+
+def FHMULS : F3_3<2, 0b110100, 0b001101000,
+                  (outs FPRegs:$rd), (ins HFPRegs:$rs1, HFPRegs:$rs2),
+                  "fhmuls $rs1, $rs2, $rd",
+                  [(set f32:$rd, (fmul (fpextend f16:$rs1),
+                                        (fpextend f16:$rs2)))]>,
+                  Requires<[HasFhMULs]>;
 def FSMULD : F3_3<2, 0b110100, 0b001101001,
                   (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
                   "fsmuld $rs1, $rs2, $rd",
                   [(set f64:$rd, (fmul (fpextend f32:$rs1),
                                         (fpextend f32:$rs2)))],
                   IIC_fpu_muld>,
-		  Requires<[HasFSMULD]>;
+                  Requires<[HasFSMULD]>;
 def FDMULQ : F3_3<2, 0b110100, 0b001101110,
                   (outs QFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
                   "fdmulq $rs1, $rs2, $rd",
@@ -1298,6 +1698,11 @@ def FDMULQ : F3_3<2, 0b110100, 0b001101110,
                                          (fpextend f64:$rs2)))]>,
                   Requires<[HasHardQuad]>;
 
+def FDIVH  : F3_3<2, 0b110100, 0b001001100,
+                  (outs HFPRegs:$rd), (ins HFPRegs:$rs1, HFPRegs:$rs2),
+                  "fdivh $rs1, $rs2, $rd",
+                  [(set f16:$rd, (fdiv f16:$rs1, f16:$rs2))]>,
+                  Requires<[HasFDIVh]>;
 // FDIVS generates an erratum on LEON processors, so by disabling this instruction
 // this will be promoted to use FDIVD with doubles instead.
 def FDIVS  : F3_3<2, 0b110100, 0b001001101,
@@ -1315,6 +1720,37 @@ def FDIVQ  : F3_3<2, 0b110100, 0b001001111,
                  "fdivq $rs1, $rs2, $rd",
                  [(set f128:$rd, (fdiv f128:$rs1, f128:$rs2))]>,
                  Requires<[HasHardQuad]>;
+def FPDIVH : F3_3<2, 0b110100, 0b010011101,
+                  (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                  "fdivph $rs1, $rs2, $rd",
+                  [(set v2f16:$rd, (fdiv v2f16:$rs1, v2f16:$rs2))]>,
+                  Requires<[HasFPPackHalf]>;
+def FPDIVS : F3_3<2, 0b110100, 0b010011110,
+                  (outs PFPSRegs:$rd), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                  "fdivps $rs1, $rs2, $rd",
+                  [(set v2f32:$rd, (fdiv v2f32:$rs1, v2f32:$rs2))]>,
+                  Requires<[HasFPPackSingle]>;
+
+def FPDIVRH : F3_3<2, 0b110100, 0b010001101,
+                  (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                  "fdivrph $rs1, $rs2, $rd",
+                  [(set v2f16:$rd, (fdiv v2f16:$rs1, v2f16:$rs2))]>,
+                  Requires<[HasFPPackHalf]>;
+def FPDIVRS : F3_3<2, 0b110100, 0b010001110,
+                  (outs PFPSRegs:$rd), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                  "fdivrps $rs1, $rs2, $rd",
+                  [(set v2f32:$rd, (fdiv v2f32:$rs1, v2f32:$rs2))]>,
+                  Requires<[HasFPPackSingle]>;
+def FPDIVXH : F3_3<2, 0b110100, 0b010111101,
+                  (outs PFPHRegs:$rd), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                  "fdivxph $rs1, $rs2, $rd",
+                  [(set v2f16:$rd, (fdiv v2f16:$rs1, v2f16:$rs2))]>,
+                  Requires<[HasFPPackHalf]>;
+def FPDIVXS : F3_3<2, 0b110100, 0b010111110,
+                  (outs PFPSRegs:$rd), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                  "fdivxps $rs1, $rs2, $rd",
+                  [(set v2f32:$rd, (fdiv v2f32:$rs1, v2f32:$rs2))]>,
+                  Requires<[HasFPPackSingle]>;
 
 // Floating-point Compare Instructions, p. 148
 // Note: the 2nd template arg is different for these guys.
@@ -1341,6 +1777,48 @@ let Defs = [FCC0], rd = 0, isCodeGenOnly = 1 in {
                    Requires<[HasHardQuad]>;
 }
 
+let Defs = [FCC0], rd = 0 in {
+  def FCMPH  : F3_3c<2, 0b110101, 0b001010000,
+                   (outs), (ins HFPRegs:$rs1, HFPRegs:$rs2),
+                   "fcmph $rs1, $rs2",
+                   [(SPcmpfcc f16:$rs1, f16:$rs2)],
+                   IIC_fpu_fast_instr>,
+                   Requires<[HasFCMPh]>;
+  def FCMPPH : F3_3c<2, 0b110101, 0b001011001,
+                   (outs), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                   "fcmpph $rs1, $rs2",
+                   [(SPcmpfcc v2f16:$rs1, v2f16:$rs2)],
+                   IIC_fpu_fast_instr>,
+                   Requires<[HasFPPackHalf]>;
+  def FCMPPS : F3_3c<2, 0b110101, 0b001011010,
+                   (outs), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                   "fcmpps $rs1, $rs2",
+                   [(SPcmpfcc v2f32:$rs1, v2f32:$rs2)],
+                   IIC_fpu_fast_instr>,
+                   Requires<[HasFPPackSingle]>;
+}
+
+let Defs = [FCC0], rd = 0, hasSideEffects = 1 in {
+  def FCMPEH  : F3_3c<2, 0b110101, 0b001010100,
+                   (outs), (ins HFPRegs:$rs1, HFPRegs:$rs2),
+                   "fcmpeh $rs1, $rs2",
+                   [(SPcmpfcc f16:$rs1, f16:$rs2)],
+                   IIC_fpu_fast_instr>,
+                   Requires<[HasFCMPh]>;
+  def FCMPEPH : F3_3c<2, 0b110101, 0b001011101,
+                   (outs), (ins PFPHRegs:$rs1, PFPHRegs:$rs2),
+                   "fcmpeph $rs1, $rs2",
+                   [(SPcmpfcc v2f16:$rs1, v2f16:$rs2)],
+                   IIC_fpu_fast_instr>,
+                   Requires<[HasFPPackHalf]>;
+  def FCMPEPS : F3_3c<2, 0b110101, 0b001011110,
+                   (outs), (ins PFPSRegs:$rs1, PFPSRegs:$rs2),
+                   "fcmpeps $rs1, $rs2",
+                   [(SPcmpfcc v2f32:$rs1, v2f32:$rs2)],
+                   IIC_fpu_fast_instr>,
+                   Requires<[HasFPPackSingle]>;
+}
+
 //===----------------------------------------------------------------------===//
 // Instructions for Thread Local Storage(TLS).
 //===----------------------------------------------------------------------===//
@@ -1735,13 +2213,31 @@ def : Pat<(extractelt (v2i32 IntPair:$Rn), 0),
 def : Pat<(extractelt (v2i32 IntPair:$Rn), 1),
           (i32 (EXTRACT_SUBREG IntPair:$Rn, sub_odd))>;
 
+def : Pat<(extractelt (v2f16 PFPHRegs:$a1), 0),
+          (f16 HFPRegs:$a1)>;
+
 // build_vector
 def : Pat<(build_vector (i32 IntRegs:$a1), (i32 IntRegs:$a2)),
           (INSERT_SUBREG
-	    (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), (i32 IntRegs:$a1), sub_even),
+            (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), (i32 IntRegs:$a1), sub_even),
             (i32 IntRegs:$a2), sub_odd)>;
 
 
+// v2f32 - insert/extract/convert/select v2f32<->f32
+def : Pat<(insertelt (v2f32 PFPSRegs:$a1), (f32 FPRegs:$a2), 0),
+          (INSERT_SUBREG (v2f32 PFPSRegs:$a1), (f32 FPRegs:$a2), sub_even)>;
+def : Pat<(insertelt (v2f32 PFPSRegs:$a1), (f32 FPRegs:$a2), 1),
+          (INSERT_SUBREG (v2f32 PFPSRegs:$a1), (f32 FPRegs:$a2), sub_odd)>;
+
+def : Pat<(extractelt (v2f32 PFPSRegs:$a1), 0),
+          (f32 (EXTRACT_SUBREG PFPSRegs:$a1, sub_even))>;
+def : Pat<(extractelt (v2f32 PFPSRegs:$a1), 1),
+          (f32 (EXTRACT_SUBREG PFPSRegs:$a1, sub_odd))>;
+def : Pat<(build_vector (f32 FPRegs:$a1), (f32 FPRegs:$a2)),
+          (INSERT_SUBREG
+            (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), (f32 FPRegs:$a1), sub_even),
+            (f32 FPRegs:$a2), sub_odd)>;
+
 include "SparcInstr64Bit.td"
 include "SparcInstrVIS.td"
 include "SparcInstrAliases.td"
diff --git a/llvm/lib/Target/Sparc/SparcRegisterInfo.td b/llvm/lib/Target/Sparc/SparcRegisterInfo.td
index 9453efb6fbb4..46d149ad7bfe 100644
--- a/llvm/lib/Target/Sparc/SparcRegisterInfo.td
+++ b/llvm/lib/Target/Sparc/SparcRegisterInfo.td
@@ -345,11 +345,22 @@ def IntPair : RegisterClass<"SP", [v2i32], 64,
 // spill slot is a stricter constraint than only requiring a 32-bit spill slot.
 def I64Regs : RegisterClass<"SP", [i64], 64, (add IntRegs)>;
 
+// Register class for swar data types - swar uses normal i32 registers
+def SwarRegs : RegisterClass<"SP",
+               [vswp32], 32, (add (sequence "I%u", 0, 7),
+                                  (sequence "G%u", 0, 7),
+                                  (sequence "L%u", 0, 7),
+                                  (sequence "O%u", 0, 7))>;
+
 // Floating point register classes.
+def HFPRegs : RegisterClass<"SP", [f16], 32, (sequence "F%u", 0, 31)>;
 def FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>;
 def DFPRegs : RegisterClass<"SP", [f64], 64, (sequence "D%u", 0, 31)>;
 def QFPRegs : RegisterClass<"SP", [f128], 128, (sequence "Q%u", 0, 15)>;
 
+def PFPHRegs : RegisterClass<"SP", [v2f16], 32, (sequence "F%u", 0, 31)>;
+def PFPSRegs : RegisterClass<"SP", [v2f32], 64, (sequence "D%u", 0, 31)>;
+
 // The Low?FPRegs classes are used only for inline-asm constraints.
 def LowDFPRegs : RegisterClass<"SP", [f64], 64, (sequence "D%u", 0, 15)>;
 def LowQFPRegs : RegisterClass<"SP", [f128], 128, (sequence "Q%u", 0, 7)>;
diff --git a/llvm/lib/Target/Sparc/SparcSchedule.td b/llvm/lib/Target/Sparc/SparcSchedule.td
index 0f05372b7050..ea5b905225c9 100644
--- a/llvm/lib/Target/Sparc/SparcSchedule.td
+++ b/llvm/lib/Target/Sparc/SparcSchedule.td
@@ -22,10 +22,13 @@ def IIC_iu_umul : InstrItinClass;
 def IIC_iu_div : InstrItinClass;
 def IIC_ticc : InstrItinClass;
 def IIC_ldstub : InstrItinClass;
+def IIC_fpu_mulh : InstrItinClass;
 def IIC_fpu_muls : InstrItinClass;
 def IIC_fpu_muld : InstrItinClass;
+def IIC_fpu_divh : InstrItinClass;
 def IIC_fpu_divs : InstrItinClass;
 def IIC_fpu_divd : InstrItinClass;
+def IIC_fpu_sqrth : InstrItinClass;
 def IIC_fpu_sqrts : InstrItinClass;
 def IIC_fpu_sqrtd : InstrItinClass;
 def IIC_fpu_abs : InstrItinClass;
@@ -66,6 +69,38 @@ def LEON2Itineraries : ProcessorItineraries<
   InstrItinData<IIC_fpu_stod, [InstrStage<1, [LEONFPU]>], [2, 1]>
 ]>;
 
+/* based on LEON2Itineraries */
+def L2DAIFPUItineraries : ProcessorItineraries<
+[LEONIU, LEONFPU], [], [
+  InstrItinData<IIC_iu_or_fpu_instr, [InstrStage<1, [LEONIU, LEONFPU]>], [1, 1]>,
+  InstrItinData<IIC_iu_instr, [InstrStage<1, [LEONIU]>], [1, 1]>,
+  InstrItinData<IIC_fpu_normal_instr, [InstrStage<1, [LEONFPU]>], [7, 1]>,
+  InstrItinData<IIC_fpu_fast_instr, [InstrStage<1, [LEONFPU]>], [7, 1]>,
+  InstrItinData<IIC_jmp_or_call, [InstrStage<1, [LEONIU, LEONFPU]>], [2, 1]>,
+  InstrItinData<IIC_ldd, [InstrStage<1, [LEONIU, LEONFPU]>], [2, 1]>,
+  InstrItinData<IIC_st, [InstrStage<1, [LEONIU, LEONFPU]>], [2, 1]>,
+  InstrItinData<IIC_std, [InstrStage<1, [LEONIU, LEONFPU]>], [3, 1]>,
+  InstrItinData<IIC_iu_smul, [InstrStage<1, [LEONIU]>], [5, 1]>,
+  InstrItinData<IIC_iu_umul, [InstrStage<1, [LEONIU]>], [5, 1]>,
+  InstrItinData<IIC_iu_div, [InstrStage<1, [LEONIU]>], [35, 1]>,
+  InstrItinData<IIC_ticc, [InstrStage<1, [LEONIU, LEONFPU]>], [4, 1]>,
+  InstrItinData<IIC_ldstub, [InstrStage<1, [LEONIU, LEONFPU]>], [3, 1]>,
+  InstrItinData<IIC_fpu_muls, [InstrStage<1, [LEONFPU]>], [6, 1]>,
+  InstrItinData<IIC_fpu_muld, [InstrStage<1, [LEONFPU]>], [7, 1]>,
+  InstrItinData<IIC_fpu_divh, [InstrStage<1, [LEONFPU]>], [19, 1]>,
+  InstrItinData<IIC_fpu_divs, [InstrStage<1, [LEONFPU]>], [32, 1]>,
+  InstrItinData<IIC_fpu_divd, [InstrStage<1, [LEONFPU]>], [61, 1]>,
+  InstrItinData<IIC_fpu_sqrth, [InstrStage<1, [LEONFPU]>], [19, 1]>,
+  InstrItinData<IIC_fpu_sqrts, [InstrStage<1, [LEONFPU]>], [32, 1]>,
+  InstrItinData<IIC_fpu_sqrtd, [InstrStage<1, [LEONFPU]>], [61, 1]>,
+  InstrItinData<IIC_fpu_abs, [InstrStage<1, [LEONFPU]>], [6, 1]>,
+  InstrItinData<IIC_fpu_movs, [InstrStage<1, [LEONFPU]>], [2, 1]>,
+  InstrItinData<IIC_fpu_negs, [InstrStage<1, [LEONFPU]>], [2, 1]>,
+  InstrItinData<IIC_fpu_stod, [InstrStage<1, [LEONFPU]>], [1, 1]>
+]>;
+
+
+
 def LEON3Itineraries : ProcessorItineraries<
 [LEONIU, LEONFPU], [], [
   InstrItinData<IIC_iu_or_fpu_instr, [InstrStage<1, [LEONIU, LEONFPU]>], [1, 1]>,
diff --git a/llvm/lib/Target/Sparc/SparcSubtarget.cpp b/llvm/lib/Target/Sparc/SparcSubtarget.cpp
index abc47ef51563..e8584b42d397 100644
--- a/llvm/lib/Target/Sparc/SparcSubtarget.cpp
+++ b/llvm/lib/Target/Sparc/SparcSubtarget.cpp
@@ -47,8 +47,27 @@ SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU,
   InsertNOPLoad = false;
   FixAllFDIVSQRT = false;
   DetectRoundChange = false;
+  InsertNOPYDIV = false;
   HasLeonCycleCounter = false;
 
+  // daiteq features
+  for (int i=0;i<32;i++) {
+    UseSoftFPopsHalf[i] = false;
+    UseSoftFPopsSingle[i] = false;
+    UseSoftFPopsDouble[i] = false;
+  }
+  UseFPPackedHalf = false;    // must be explicitly enabled
+  UseFPPackedSingle = false;  // must be explicitly enabled
+  AllowUnalignedPackedFP = false; // must be explicitly enabled
+
+  AnySoftFloatHalf = false;
+  AnySoftFloatSingle = false;
+  AnySoftFloatDouble = false;
+
+  AnyHardFloatHalf = true;
+  AnyHardFloatSingle = true;
+  AnyHardFloatDouble = true;
+
   // Determine default and user specified characteristics
   std::string CPUName = std::string(CPU);
   if (CPUName.empty())
@@ -57,6 +76,58 @@ SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU,
   // Parse features string.
   ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS);
 
+  // Update soft-float flags according parsed features
+  // In this version - flags in UseSoftFPopsXXXX have higher priority (are allways set to all true if 'soft-float' is us
+  // -> should be updated for checking if daiteq-fpu flag is used on cmd line
+  //bool anyhardfp = false;
+  bool allsoftfp = true; // !allsoftfp = anyhardfp;
+  for (int i=0;i<32;i++) {
+    if (i==llvm::SoftFops::SOFTFP_PACK || i>llvm::SoftFops::SOFTFP_NEG) continue;
+    if (UseSoftFPopsHalf[i]) AnySoftFloatHalf = true; else allsoftfp = false;
+  }
+  if (allsoftfp) AnyHardFloatHalf = false;
+
+  allsoftfp = true;
+  for (int i=0;i<32;i++) {
+    if (i==llvm::SoftFops::SOFTFP_PACK || i>llvm::SoftFops::SOFTFP_NEG) continue;
+    if (UseSoftFPopsSingle[i]) AnySoftFloatSingle = true; else allsoftfp = false;
+  }
+  if (allsoftfp) AnyHardFloatSingle = false;
+
+  allsoftfp = true;
+  for (int i=0;i<32;i++) {
+    if (i==llvm::SoftFops::SOFTFP_PACK || i>llvm::SoftFops::SOFTFP_NEG) continue;
+    if (UseSoftFPopsDouble[i]) AnySoftFloatDouble = true; else allsoftfp = false;
+  }
+  if (allsoftfp) AnyHardFloatDouble = false;
+
+  // if -msoft-float is used - all is in soft-float
+  if (UseSoftFloat) {
+    for (int i=0;i<32;i++) {
+      UseSoftFPopsHalf[i] = true;
+      UseSoftFPopsSingle[i] = true;
+      UseSoftFPopsDouble[i] = true;
+    }
+    UseFPPackedHalf = false;
+    UseFPPackedSingle = false;
+    AnySoftFloatHalf = true;
+    AnySoftFloatSingle = true;
+    AnySoftFloatDouble = true;
+    AnyHardFloatHalf = false;
+    AnyHardFloatSingle = false;
+    AnyHardFloatDouble = false;
+  }
+
+  // correct soft-float flag if necessary
+//  if (UseSoftFloat) {
+//    if (!allsoftfp) UseSoftFloat = false; /* disable full soft-float */
+//  } else {
+//    if (AnySoftFloatHalf || AnySoftFloatSingle || AnySoftFloatDouble ||
+//        AnySoftFloatPackedHalf || AnySoftFloatPackedSingle)
+//      UseSoftFloat = true; /* enable soft-float if any soft-float FPop is required */
+//  }
+
+
   // Popc is a v9-only instruction.
   if (!IsV9)
     UsePopc = false;
diff --git a/llvm/lib/Target/Sparc/SparcSubtarget.h b/llvm/lib/Target/Sparc/SparcSubtarget.h
index 82a4aa510355..7fe2a1c6528c 100644
--- a/llvm/lib/Target/Sparc/SparcSubtarget.h
+++ b/llvm/lib/Target/Sparc/SparcSubtarget.h
@@ -39,7 +39,7 @@ class SparcSubtarget : public SparcGenSubtargetInfo {
   bool Is64Bit;
   bool HasHardQuad;
   bool UsePopc;
-  bool UseSoftFloat;
+  bool UseSoftFloat; /* this indicates soft-float for all instructions */
   bool HasNoFSMULD;
   bool HasNoFMULS;
 
@@ -50,8 +50,27 @@ class SparcSubtarget : public SparcGenSubtargetInfo {
   bool InsertNOPLoad;
   bool FixAllFDIVSQRT;
   bool DetectRoundChange;
+  bool InsertNOPYDIV;
   bool HasLeonCycleCounter;
 
+  // daiteq features - soft float FP operations
+  bool UseSoftFPopsHalf[32];
+  bool UseSoftFPopsSingle[32];
+  bool UseSoftFPopsDouble[32];
+
+  bool UseFPPackedHalf;
+  bool UseFPPackedSingle;
+
+  bool AnySoftFloatHalf;          /* if there is at least one half FPop in soft-float */
+  bool AnySoftFloatSingle;        /* if there is at least one single FPop in soft-float */
+  bool AnySoftFloatDouble;        /* if there is at least one double FPop in soft-float */
+
+  bool AnyHardFloatHalf;          /* if there is at least one half FPop in hard-float */
+  bool AnyHardFloatSingle;        /* if there is at least one single FPop in hard-float */
+  bool AnyHardFloatDouble;        /* if there is at least one double FPop in hard-float */
+
+  bool AllowUnalignedPackedFP;
+
   SparcInstrInfo InstrInfo;
   SparcTargetLowering TLInfo;
   SelectionDAGTargetInfo TSInfo;
@@ -97,8 +116,27 @@ public:
   bool insertNOPLoad() const { return InsertNOPLoad; }
   bool fixAllFDIVSQRT() const { return FixAllFDIVSQRT; }
   bool detectRoundChange() const { return DetectRoundChange; }
+  bool insertNOPYDIV() const { return InsertNOPYDIV; }
   bool hasLeonCycleCounter() const { return HasLeonCycleCounter; }
 
+  // daiteq options
+  bool useSoftFopHalf(unsigned softfp) const { return UseSoftFPopsHalf[softfp]; }
+  bool useSoftFopSingle(unsigned softfp) const { return UseSoftFPopsSingle[softfp]; }
+  bool useSoftFopDouble(unsigned softfp) const { return UseSoftFPopsDouble[softfp]; }
+
+  bool useSoftHalf() const { return AnySoftFloatHalf; }
+  bool useSoftSingle() const { return AnySoftFloatSingle; }
+  bool useSoftDouble() const { return AnySoftFloatDouble; }
+
+  bool useHardHalf() const { return AnyHardFloatHalf; }
+  bool useHardSingle() const { return AnyHardFloatSingle; }
+  bool useHardDouble() const { return AnyHardFloatDouble; }
+
+  bool usePackedHalf() const { return UseFPPackedHalf; }
+  bool usePackedSingle() const { return UseFPPackedSingle; }
+
+  bool isAllowedUnalignedFP() const { return AllowUnalignedPackedFP; }
+
   /// ParseSubtargetFeatures - Parses features string setting specified
   /// subtarget options.  Definition of function is auto generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
index 083339bc157c..7f3471507145 100644
--- a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
+++ b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
@@ -51,6 +51,9 @@ static std::string computeDataLayout(const Triple &T, bool is64Bit) {
   else
     Ret += "-S64";
 
+  if (T.getArch() == Triple::sparc && T.getVendor() == Triple::Daiteq)
+    Ret += "-f16:16";
+
   return Ret;
 }
 
@@ -114,6 +117,93 @@ SparcTargetMachine::getSubtargetImpl(const Function &F) const {
   std::string FS =
       FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
 
+  if (F.hasFnAttribute("soft-fops-half")) {
+    unsigned val = std::stoul(F.getFnAttribute("soft-fops-half").getValueAsString().str(), NULL, 0);
+    if (val>0) {
+      if (val & llvm::SoftFops::FPOP_ADD)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fadd"; }
+      if (val & llvm::SoftFops::FPOP_SUB)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fsub"; }
+      if (val & llvm::SoftFops::FPOP_MUL)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fmul"; }
+      if (val & llvm::SoftFops::FPOP_DIV)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fdiv"; }
+      if (val & llvm::SoftFops::FPOP_MULEX) { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fmulex"; }
+      if (val & llvm::SoftFops::FPOP_SQRT) { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fsqrt"; }
+      if (val & llvm::SoftFops::FPOP_CMP)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fcmp"; }
+      if (val & llvm::SoftFops::FPOP_CI2F) { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fci2f"; }
+      if (val & llvm::SoftFops::FPOP_CF2I) { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fcf2i"; }
+      if (val & llvm::SoftFops::FPOP_CFUP) { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fcfup"; }
+      if (val & llvm::SoftFops::FPOP_CFDN) { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fcfdn"; }
+      if (val & llvm::SoftFops::FPOP_ABS) { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fabs"; }
+      //if (val & llvm::SoftFops::FPOP_PACK) { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-pack"; }
+      if (val & llvm::SoftFops::FPOP_MOV) { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fmov"; }
+      if (val & llvm::SoftFops::FPOP_NEG) { if (!FS.empty()) FS += ","; FS += "+soft-fops-half-fneg"; }
+    }
+  }
+  if (F.hasFnAttribute("soft-fops-single")) {
+    unsigned val = std::stoul(F.getFnAttribute("soft-fops-single").getValueAsString().str(), NULL, 0);
+    if (val>0) {
+      if (val & llvm::SoftFops::FPOP_ADD)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fadd"; }
+      if (val & llvm::SoftFops::FPOP_SUB)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fsub"; }
+      if (val & llvm::SoftFops::FPOP_MUL)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fmul"; }
+      if (val & llvm::SoftFops::FPOP_DIV)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fdiv"; }
+      if (val & llvm::SoftFops::FPOP_MULEX) { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fmulex"; }
+      if (val & llvm::SoftFops::FPOP_SQRT) { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fsqrt"; }
+      if (val & llvm::SoftFops::FPOP_CMP)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fcmp"; }
+      if (val & llvm::SoftFops::FPOP_CI2F) { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fci2f"; }
+      if (val & llvm::SoftFops::FPOP_CF2I) { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fcf2i"; }
+      if (val & llvm::SoftFops::FPOP_CFUP) { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fcfup"; }
+      if (val & llvm::SoftFops::FPOP_CFDN) { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fcfdn"; }
+      if (val & llvm::SoftFops::FPOP_ABS) { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fabs"; }
+      //if (val & llvm::SoftFops::FPOP_PACK) { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-pack"; }
+      if (val & llvm::SoftFops::FPOP_MOV) { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fmov"; }
+      if (val & llvm::SoftFops::FPOP_NEG) { if (!FS.empty()) FS += ","; FS += "+soft-fops-single-fneg"; }
+    }
+  }
+  if (F.hasFnAttribute("soft-fops-double")) {
+    unsigned val = std::stoul(F.getFnAttribute("soft-fops-double").getValueAsString().str(), NULL, 0);
+    if (val>0) {
+      if (val & llvm::SoftFops::FPOP_ADD)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fadd"; }
+      if (val & llvm::SoftFops::FPOP_SUB)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fsub"; }
+      if (val & llvm::SoftFops::FPOP_MUL)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fmul"; }
+      if (val & llvm::SoftFops::FPOP_DIV)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fdiv"; }
+      if (val & llvm::SoftFops::FPOP_MULEX) { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fmulex"; }
+      if (val & llvm::SoftFops::FPOP_SQRT) { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fsqrt"; }
+      if (val & llvm::SoftFops::FPOP_CMP)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fcmp"; }
+      if (val & llvm::SoftFops::FPOP_CI2F) { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fci2f"; }
+      if (val & llvm::SoftFops::FPOP_CF2I) { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fcf2i"; }
+      if (val & llvm::SoftFops::FPOP_CFUP) { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fcfup"; }
+      if (val & llvm::SoftFops::FPOP_CFDN) { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fcfdn"; }
+      if (val & llvm::SoftFops::FPOP_ABS) { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fabs"; }
+      //if (val & llvm::SoftFops::FPOP_PACK) { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-pack"; }
+      if (val & llvm::SoftFops::FPOP_MOV) { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fmov"; }
+      if (val & llvm::SoftFops::FPOP_NEG) { if (!FS.empty()) FS += ","; FS += "+soft-fops-double-fneg"; }
+    }
+  }
+  if (F.hasFnAttribute("soft-fops-packhalf")) {
+    unsigned val = std::stoul(F.getFnAttribute("soft-fops-packhalf").getValueAsString().str(), NULL, 0);
+    if (val>0) {
+      if (val & llvm::SoftFops::FPOP_ADD)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packhalf-fadd"; }
+      if (val & llvm::SoftFops::FPOP_SUB)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packhalf-fsub"; }
+      if (val & llvm::SoftFops::FPOP_MUL)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packhalf-fmul"; }
+      if (val & llvm::SoftFops::FPOP_DIV)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packhalf-fdiv"; }
+      if (val & llvm::SoftFops::FPOP_SQRT) { if (!FS.empty()) FS += ","; FS += "+soft-fops-packhalf-fsqrt"; }
+      if (val & llvm::SoftFops::FPOP_PACK) { if (!FS.empty()) FS += ","; FS += "+soft-fops-packhalf-pack"; }
+      if (val & llvm::SoftFops::FPOP_CMP)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packhalf-fcmp"; }
+      if (val & llvm::SoftFops::FPOP_MOV)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packhalf-fmov"; }  /* FMOVHU, FMOVHL, FSWAPH */
+    }
+  }
+  if (F.hasFnAttribute("soft-fops-packsingle")) {
+    unsigned val = std::stoul(F.getFnAttribute("soft-fops-packsingle").getValueAsString().str(), NULL, 0);
+    if (val>0) {
+      if (val & llvm::SoftFops::FPOP_ADD)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packsingle-fadd"; }
+      if (val & llvm::SoftFops::FPOP_SUB)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packsingle-fsub"; }
+      if (val & llvm::SoftFops::FPOP_MUL)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packsingle-fmul"; }
+      if (val & llvm::SoftFops::FPOP_DIV)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packsingle-fdiv"; }
+      if (val & llvm::SoftFops::FPOP_SQRT) { if (!FS.empty()) FS += ","; FS += "+soft-fops-packsingle-fsqrt"; }
+      if (val & llvm::SoftFops::FPOP_PACK) { if (!FS.empty()) FS += ","; FS += "+soft-fops-packsingle-pack"; }
+      if (val & llvm::SoftFops::FPOP_CMP)  { if (!FS.empty()) FS += ","; FS += "+soft-fops-packsingle-fcmp"; }
+    }
+  }
+
+
   // FIXME: This is related to the code below to reset the target options,
   // we need to know whether or not the soft float flag is set on the
   // function, so we can enable it as a subtarget feature.
@@ -180,6 +270,10 @@ void SparcPassConfig::addPreEmitPass(){
   {
     addPass(new FixAllFDIVSQRT());
   }
+  if (this->getSparcTargetMachine().getSubtargetImpl()->insertNOPYDIV())
+  {
+    addPass(new InsertNOPYDIV());
+  }
 }
 
 void SparcV8TargetMachine::anchor() { }
diff --git a/llvm/lib/Transforms/IPO/GlobalOpt.cpp b/llvm/lib/Transforms/IPO/GlobalOpt.cpp
index 8750eb9ecc4e..1ab0ca630a5b 100644
--- a/llvm/lib/Transforms/IPO/GlobalOpt.cpp
+++ b/llvm/lib/Transforms/IPO/GlobalOpt.cpp
@@ -131,6 +131,7 @@ static bool isLeakCheckerRoot(GlobalVariable *GV) {
         return true;
       case Type::FixedVectorTyID:
       case Type::ScalableVectorTyID:
+      case Type::SubwordVectorTyID:
         if (cast<VectorType>(Ty)->getElementType()->isPointerTy())
           return true;
         break;
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp b/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
index 32b15376f898..78b520a20b03 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
@@ -1440,6 +1440,8 @@ Instruction *InstCombinerImpl::visitInsertElementInst(InsertElementInst &IE) {
     return new BitCastInst(NewInsElt, IE.getType());
   }
 
+  if (isa<SubwordVectorType>(IE.getType())) return nullptr;
+
   // If the inserted element was extracted from some other fixed-length vector
   // and both indexes are valid constants, try to turn this into a shuffle.
   // Can not handle scalable vector type, the number of elements needed to
diff --git a/llvm/lib/Transforms/Scalar/BDCE.cpp b/llvm/lib/Transforms/Scalar/BDCE.cpp
index c06125788f37..616a9eb45775 100644
--- a/llvm/lib/Transforms/Scalar/BDCE.cpp
+++ b/llvm/lib/Transforms/Scalar/BDCE.cpp
@@ -94,6 +94,7 @@ static bool bitTrackingDCE(Function &F, DemandedBits &DB) {
   SmallVector<Instruction*, 128> Worklist;
   bool Changed = false;
   for (Instruction &I : instructions(F)) {
+if (isa<SubwordVectorType>(I.getType())) continue;
     // If the instruction has side effects and no non-dbg uses,
     // skip it. This way we avoid computing known bits on an instruction
     // that will not help us.
diff --git a/llvm/lib/Transforms/Scalar/SROA.cpp b/llvm/lib/Transforms/Scalar/SROA.cpp
index fe160d5415bd..ffdf693dceef 100644
--- a/llvm/lib/Transforms/Scalar/SROA.cpp
+++ b/llvm/lib/Transforms/Scalar/SROA.cpp
@@ -1822,6 +1822,7 @@ static bool isVectorPromotionViableForSlice(Partition &P, const Slice &S,
   uint64_t BeginOffset =
       std::max(S.beginOffset(), P.beginOffset()) - P.beginOffset();
   uint64_t BeginIndex = BeginOffset / ElementSize;
+  if (Ty->getVectorIsSubword()) return false; /* SubwordVectors are not supported yet */
   if (BeginIndex * ElementSize != BeginOffset ||
       BeginIndex >= cast<FixedVectorType>(Ty)->getNumElements())
     return false;
diff --git a/llvm/lib/Transforms/Utils/FunctionComparator.cpp b/llvm/lib/Transforms/Utils/FunctionComparator.cpp
index 2696557a719f..85dee01b4dac 100644
--- a/llvm/lib/Transforms/Utils/FunctionComparator.cpp
+++ b/llvm/lib/Transforms/Utils/FunctionComparator.cpp
@@ -503,6 +503,17 @@ int FunctionComparator::cmpTypes(Type *TyL, Type *TyR) const {
                         STyR->getElementCount().getKnownMinValue());
     return cmpTypes(STyL->getElementType(), STyR->getElementType());
   }
+  case Type::SubwordVectorTyID: {
+    auto *STyL = cast<SubwordVectorType>(TyL);
+    auto *STyR = cast<SubwordVectorType>(TyR);
+    if (STyL->getPacking() != STyR->getPacking())
+      return cmpNumbers(STyL->getPacking(), STyR->getPacking());
+    if (STyL->getSigned() != STyR->getSigned())
+      return cmpNumbers(STyL->getSigned(), STyR->getSigned());
+    if (STyL->getNumElements() != STyR->getNumElements())
+      return cmpNumbers(STyL->getNumElements(), STyR->getNumElements());
+    return cmpTypes(STyL->getElementType(), STyR->getElementType());
+  }
   }
 }
 
diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
index 00bdd127e3c2..f5ed0d733267 100644
--- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
@@ -211,6 +211,9 @@ struct ClassInfo {
   /// Is this operand optional and not always required.
   bool IsOptional;
 
+  /// Register group for user defined replacement of register kinds
+  unsigned KindGroup;
+
   /// DefaultMethod - The name of the method that returns the default operand
   /// for optional operand
   std::string DefaultMethod;
@@ -1313,6 +1316,9 @@ buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters) {
     if (StringInit *SI = dyn_cast<StringInit>(DiagnosticString))
       CI->DiagnosticString = std::string(SI->getValue());
 
+    int KindGroup = Def->getValueAsInt("KindGroup");
+    CI->KindGroup = KindGroup;
+
     // If we have a diagnostic string but the diagnostic type is not specified
     // explicitly, create an anonymous diagnostic type.
     if (!CI->DiagnosticString.empty() && CI->DiagnosticType.empty())
@@ -1321,6 +1327,19 @@ buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters) {
     RegisterClassClasses.insert(std::make_pair(Def, CI));
   }
 
+  for (const RegisterSet &RS : RegisterSets) {
+    ClassInfo *CI = RegisterSetClasses[RS];
+    // check if the class is a superclass for another class
+      if (CI->SuperClasses.size()<=0) continue;
+      for (auto *Super : CI->SuperClasses) {
+        if (!CI->KindGroup && Super->KindGroup) {
+          CI->KindGroup = Super->KindGroup;
+          //fprintf(stderr,"  ~> set KG = %d\n", CI->KindGroup);
+        }
+      }
+    }
+
+
   // Populate the map for individual registers.
   for (auto &It : RegisterMap)
     RegisterClasses[It.first] = RegisterSetClasses[It.second];
@@ -2524,6 +2543,16 @@ static void emitIsSubclass(CodeGenTarget &Target,
       if (&A != &B && A.isSubsetOf(B))
         SuperClasses.push_back(B.Name);
     }
+/* Test equality of user kind group record item (Kindgroup must be non-zero),  */
+    if (A.KindGroup>0) {
+      for (const auto &B : Infos) {
+        if (B.Name==A.Name) continue;
+        if (B.KindGroup==A.KindGroup) {
+          if (std::find(SuperClasses.begin(), SuperClasses.end(), B.Name) == SuperClasses.end())
+            SuperClasses.push_back(B.Name);
+        }
+      }
+    }
 
     if (SuperClasses.empty())
       continue;
diff --git a/llvm/utils/TableGen/CodeGenTarget.cpp b/llvm/utils/TableGen/CodeGenTarget.cpp
index 137f99078faf..9c48a95be6f9 100644
--- a/llvm/utils/TableGen/CodeGenTarget.cpp
+++ b/llvm/utils/TableGen/CodeGenTarget.cpp
@@ -236,6 +236,23 @@ StringRef llvm::getEnumName(MVT::SimpleValueType T) {
   case MVT::nxv2f64:   return "MVT::nxv2f64";
   case MVT::nxv4f64:   return "MVT::nxv4f64";
   case MVT::nxv8f64:   return "MVT::nxv8f64";
+
+  //case MVT::vswp32:   return "MVT::vswp32";
+  //case MVT::vswp64:   return "MVT::vswp64";
+  case MVT::vswp32i1:   return "MVT::vswp32i1";
+  case MVT::vswp32i2:   return "MVT::vswp32i2";
+  case MVT::vswp32i3:   return "MVT::vswp32i3";
+  case MVT::vswp32i4:   return "MVT::vswp32i4";
+  case MVT::vswp32i8:   return "MVT::vswp32i8";
+  case MVT::vswp32i16:  return "MVT::vswp32i16";
+  case MVT::vswp64i1:   return "MVT::vswp64i1";
+  case MVT::vswp64i2:   return "MVT::vswp64i2";
+  case MVT::vswp64i3:   return "MVT::vswp64i3";
+  case MVT::vswp64i4:   return "MVT::vswp64i4";
+  case MVT::vswp64i8:   return "MVT::vswp64i8";
+  case MVT::vswp64i16:  return "MVT::vswp64i16";
+  case MVT::vswp64i32:  return "MVT::vswp64i32";
+
   case MVT::token:     return "MVT::token";
   case MVT::Metadata:  return "MVT::Metadata";
   case MVT::iPTR:      return "MVT::iPTR";
-- 
2.20.1